8 files changed, 46 insertions, 20 deletions
diff --git a/src/mainboard/google/glados/acpi/chromeos.asl b/src/mainboard/google/glados/acpi/chromeos.asl
index 09f7ed1de4..b8cef5ea91 100644
--- a/src/mainboard/google/glados/acpi/chromeos.asl
+++ b/src/mainboard/google/glados/acpi/chromeos.asl
@@ -17,11 +17,11 @@
  * Foundation, Inc.
  */
 
-#include <soc/gpio.h>
+#include <mainboard/google/glados/gpio.h>
 
 Name (OIPG, Package () {
 	/* No physical recovery GPIO. */
 	Package () { 0x0001, 0, 0xFFFFFFFF, "INT344B:00" },
 	/* Firmware write protect GPIO. */
-	Package () { 0x0003, 1, GPP_C23, "INT344B:00" },
+	Package () { 0x0003, 1, GPIO_PCH_WP, "INT344B:00" },
 })
diff --git a/src/mainboard/google/glados/acpi/ec.asl b/src/mainboard/google/glados/acpi/ec.asl
index 8e7532de34..321b2ce600 100644
--- a/src/mainboard/google/glados/acpi/ec.asl
+++ b/src/mainboard/google/glados/acpi/ec.asl
@@ -19,6 +19,7 @@
 
 /* mainboard configuration */
 #include <mainboard/google/glados/ec.h>
+#include <mainboard/google/glados/gpio.h>
 
 /* Enable EC backed PD MCU device in ACPI */
 #define EC_ENABLE_PD_MCU_DEVICE
diff --git a/src/mainboard/google/glados/acpi/mainboard.asl b/src/mainboard/google/glados/acpi/mainboard.asl
index e2a1b5f0f8..8e512596f5 100644
--- a/src/mainboard/google/glados/acpi/mainboard.asl
+++ b/src/mainboard/google/glados/acpi/mainboard.asl
@@ -17,15 +17,16 @@
  * Foundation, Inc.
  */
 
-#include <soc/gpio.h>
+#include <mainboard/google/glados/gpio.h>
 
 #define BOARD_TOUCHPAD_I2C_ADDR			0x15
-#define BOARD_TOUCHPAD_IRQ			GPP_B3_IRQ
+#define BOARD_TOUCHPAD_IRQ			TOUCHPAD_INT_L
 
 #define BOARD_TOUCHSCREEN_I2C_ADDR		0x10
-#define BOARD_TOUCHSCREEN_IRQ			GPP_E7_IRQ
+#define BOARD_TOUCHSCREEN_IRQ			TOUCHSCREEN_INT_L
 
 #define BOARD_HP_MIC_CODEC_I2C_ADDR		0x1a
+#define BOARD_HP_MIC_CODEC_IRQ			MIC_INT_L
 #define BOARD_LEFT_SPEAKER_AMP_I2C_ADDR		0x34
 #define BOARD_RIGHT_SPEAKER_AMP_I2C_ADDR	0x35
 
@@ -33,19 +34,18 @@ Scope (\_SB)
 {
 	Device (LID0)
 	{
-		Name (_HID, EisaId("PNP0C0D"))
+		Name (_HID, EisaId ("PNP0C0D"))
 		Method (_LID, 0)
 		{
 			Return (\_SB.PCI0.LPCB.EC0.LIDS)
 		}
 
-		/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
-		Name (_PRW, Package(){ GPE0_LAN_WAK, 5 })
+		Name (_PRW, Package () { GPE_EC_WAKE, 5 })
 	}
 
 	Device (PWRB)
 	{
-		Name(_HID, EisaId("PNP0C0C"))
+		Name (_HID, EisaId ("PNP0C0C"))
 	}
 
 	/* Keyboard Backlight interface via EC */
@@ -157,6 +157,10 @@ Scope (\_SB.PCI0.I2C4)
 				AddressingMode7Bit,
 				"\\_SB.PCI0.I2C4",
 			)
+			Interrupt (ResourceConsumer, Edge, ActiveLow)
+			{
+				BOARD_HP_MIC_CODEC_IRQ
+			}
 		})
 
 		Method (_STA)
diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c
index f7a8770dbd..13d0fcef8f 100644
--- a/src/mainboard/google/glados/chromeos.c
+++ b/src/mainboard/google/glados/chromeos.c
@@ -28,6 +28,7 @@
 #include <string.h>
 #include <ec/google/chromeec/ec.h>
 #include <vendorcode/google/chromeos/chromeos.h>
+#include <mainboard/google/glados/gpio.h>
 
 #include "ec.h"
 
@@ -90,5 +91,5 @@ int clear_recovery_mode_switch(void)
 int get_write_protect_state(void)
 {
 	/* Read PCH_WP GPIO. */
-	return gpio_get(GPP_C23);
+	return gpio_get(GPIO_PCH_WP);
 }
diff --git a/src/mainboard/google/glados/ec.h b/src/mainboard/google/glados/ec.h
index bfe4a110b5..6408815aad 100644
--- a/src/mainboard/google/glados/ec.h
+++ b/src/mainboard/google/glados/ec.h
@@ -22,12 +22,6 @@
 #define MAINBOARD_EC_H
 
 #include <ec/google/chromeec/ec_commands.h>
-#include <soc/gpio.h>
-#include <soc/gpe.h>
-
-/* GPP_E16 is EC_SCI_L. GPP_E group is routed to dword 2 in the GPE0 block. */
-#define EC_SCI_GPI	GPE0_DW2_16
-#define EC_SMI_GPI	GPP_E15
 
 #define MAINBOARD_EC_SCI_EVENTS \
 	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
diff --git a/src/mainboard/google/glados/gpio.h b/src/mainboard/google/glados/gpio.h
index c7cd5ae0c5..fc5ffffbac 100644
--- a/src/mainboard/google/glados/gpio.h
+++ b/src/mainboard/google/glados/gpio.h
@@ -20,8 +20,31 @@
 #ifndef MAINBOARD_GPIO_H
 #define MAINBOARD_GPIO_H
 
+#include <soc/gpe.h>
 #include <soc/gpio.h>
 
+/* BIOS Flash Write Protect */
+#define GPIO_PCH_WP		GPP_C23
+
+/* Memory configuration board straps */
+#define GPIO_MEM_CONFIG_0	GPP_C12
+#define GPIO_MEM_CONFIG_1	GPP_C13
+#define GPIO_MEM_CONFIG_2	GPP_C14
+#define GPIO_MEM_CONFIG_3	GPP_C15
+
+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
+#define GPE_EC_WAKE		GPE0_LAN_WAK
+
+/* Input device interrupt configuration */
+#define TOUCHPAD_INT_L		GPP_B3_IRQ
+#define TOUCHSCREEN_INT_L	GPP_E7_IRQ
+#define MIC_INT_L		GPP_F10_IRQ
+
+/* GPP_E16 is EC_SCI_L. GPP_E group is routed to dword 2 in the GPE0 block. */
+#define EC_SCI_GPI		GPE0_DW2_16
+#define EC_SMI_GPI		GPP_E15
+
+#ifndef __ACPI__
 static const struct pad_config gpio_table[] = {
 /* RCIN# */		PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
 /* LAD0 */		PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
@@ -193,5 +216,6 @@ static const struct pad_config gpio_table[] = {
 /* SLP_S5# */		PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
 /* LANPHYC */		/* GPD11 */
 };
+#endif
 
 #endif
diff --git a/src/mainboard/google/glados/smihandler.c b/src/mainboard/google/glados/smihandler.c
index f9f4707973..041d5dccea 100644
--- a/src/mainboard/google/glados/smihandler.c
+++ b/src/mainboard/google/glados/smihandler.c
@@ -28,6 +28,7 @@
 #include <soc/pm.h>
 #include <soc/smm.h>
 #include "ec.h"
+#include "gpio.h"
 
 int mainboard_io_trap_handler(int smif)
 {
diff --git a/src/mainboard/google/glados/spd/spd.c b/src/mainboard/google/glados/spd/spd.c
index d5d96b6ead..ad05b31ddf 100644
--- a/src/mainboard/google/glados/spd/spd.c
+++ b/src/mainboard/google/glados/spd/spd.c
@@ -25,6 +25,7 @@
 #include <string.h>
 #include <soc/pei_data.h>
 #include <soc/romstage.h>
+#include <mainboard/google/glados/gpio.h>
 #include "spd.h"
 
 static void mainboard_print_spd_info(uint8_t spd[])
@@ -86,10 +87,10 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
 	int spd_index;
 
 	gpio_t spd_gpios[] = {
-		GPP_C12,	/* PCH_MEM_CONFIG[0] */
-		GPP_C13,	/* PCH_MEM_CONFIG[1] */
-		GPP_C14,	/* PCH_MEM_CONFIG[2] */
-		GPP_C15,	/* PCH_MEM_CONFIG[3] */
+		GPIO_MEM_CONFIG_0,
+		GPIO_MEM_CONFIG_1,
+		GPIO_MEM_CONFIG_2,
+		GPIO_MEM_CONFIG_3,
 	};
 
 	spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));