diff options
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/emulation/qemu-i440fx/northbridge.c | 2 | ||||
| -rw-r--r-- | src/mainboard/emulation/qemu-q35/cpu.c | 9 | ||||
| -rw-r--r-- | src/mainboard/emulation/qemu-q35/memmap.c | 8 |
3 files changed, 16 insertions, 3 deletions
diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 06aa83af50..b55ace0986 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -247,7 +247,7 @@ extern const struct mp_ops mp_ops_with_smm; void mp_init_cpus(struct bus *cpu_bus) { - const struct mp_ops *ops = CONFIG(SMM_TSEG) ? &mp_ops_with_smm : &mp_ops_no_smm; + const struct mp_ops *ops = CONFIG(NO_SMM) ? &mp_ops_no_smm : &mp_ops_with_smm; /* TODO: Handle mp_init_with_smm failure? */ mp_init_with_smm(cpu_bus, ops); diff --git a/src/mainboard/emulation/qemu-q35/cpu.c b/src/mainboard/emulation/qemu-q35/cpu.c index fb31fc5963..fe3a571021 100644 --- a/src/mainboard/emulation/qemu-q35/cpu.c +++ b/src/mainboard/emulation/qemu-q35/cpu.c @@ -12,7 +12,14 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, { printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); + if (CONFIG(SMM_TSEG)) + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); + + if (CONFIG(SMM_ASEG)) { + smm_open_aseg(); + *perm_smbase = 0xa0000; + *perm_smsize = 0x10000; + } /* FIXME: on X86_64 the save state size is smaller than the size of the SMM stub */ *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); diff --git a/src/mainboard/emulation/qemu-q35/memmap.c b/src/mainboard/emulation/qemu-q35/memmap.c index 7d5180e819..e73e0dfa12 100644 --- a/src/mainboard/emulation/qemu-q35/memmap.c +++ b/src/mainboard/emulation/qemu-q35/memmap.c @@ -78,6 +78,12 @@ void smm_lock(void) */ printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_or_config8(PCI_DEV(0, 0, 0), ESMRAMC, T_EN); + if (CONFIG(SMM_TSEG)) + pci_or_config8(PCI_DEV(0, 0, 0), ESMRAMC, T_EN); pci_write_config8(PCI_DEV(0, 0, 0), SMRAMC, D_LCK | G_SMRAME | C_BASE_SEG); } + +void smm_open_aseg(void) +{ + pci_write_config8(PCI_DEV(0, 0, 0), SMRAMC, G_SMRAME | C_BASE_SEG | D_OPEN); +} |