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-rw-r--r--src/mainboard/google/brya/variants/orisa/gpio.c20
1 files changed, 10 insertions, 10 deletions
diff --git a/src/mainboard/google/brya/variants/orisa/gpio.c b/src/mainboard/google/brya/variants/orisa/gpio.c
index 49fc02558e..7d0fc28fe0 100644
--- a/src/mainboard/google/brya/variants/orisa/gpio.c
+++ b/src/mainboard/google/brya/variants/orisa/gpio.c
@@ -62,9 +62,9 @@ static const struct pad_config gpio_table[] = {
/* B4 : PROC_GP3 ==> EN_PP3300_UCAM_X */
PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG),
/* B5 : GPP_B5 ==> ISH_I2C0_SCL */
- PAD_CFG_NF_LOCK(GPP_B5, NONE, NF1, LOCK_CONFIG),
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B5, NONE, DEEP, NF1),
/* B6 : GPP_B6 ==> ISH_I2C0_SDA */
- PAD_CFG_NF_LOCK(GPP_B6, NONE, NF1, LOCK_CONFIG),
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B6, NONE, DEEP, NF1),
/* B7 : GPP_B7 ==> NC */
PAD_NC_LOCK(GPP_B7, NONE, LOCK_CONFIG),
/* B8 : GPP_B8 ==> NC */
@@ -118,9 +118,9 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
/* D0 : ISH_GP0 ==> SOC_GSEN1_INT# */
- PAD_CFG_NF_LOCK(GPP_D0, NONE, NF1, LOCK_CONFIG),
+ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),
/* D1 : ISH_GP1 ==> SOC_GSEN2_INT# */
- PAD_CFG_NF_LOCK(GPP_D1, NONE, NF1, LOCK_CONFIG),
+ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
/* D2 : ISH_GP2 ==> SEN_MODE_EC_PCH_INT_ODL */
PAD_CFG_GPI_LOCK(GPP_D2, NONE, LOCK_CONFIG),
/* D3 : NC */
@@ -144,9 +144,9 @@ static const struct pad_config gpio_table[] = {
/* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */
PAD_NC_LOCK(GPP_D12, NONE, LOCK_CONFIG),
/* D13 : UART0_ISH_RX_DBG_TX */
- PAD_CFG_NF_LOCK(GPP_D13, NONE, NF1, LOCK_CONFIG),
+ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
/* D14 : UART0_ISH_TX_DBG_RX */
- PAD_CFG_NF_LOCK(GPP_D14, NONE, NF1, LOCK_CONFIG),
+ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
/* D15 : GPP_D15 ==> SOC_TS_I2C_RST# */
PAD_CFG_GPO_LOCK(GPP_D15, 1, LOCK_CONFIG),
/* D16 : ISH_UART0_CTS# ==> SOC_TS_I2C_INT# */
@@ -280,10 +280,10 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
/* H11 : UART0_TXD ==> UART_2_CTXD_DRXD */
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
- /* H12 : UART0_RTS# ==> NC */
- PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
- /* H13 : UART0_CTS# ==> NC */
- PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
+ /* H12 : GPP_H12 ==> ISH_GP6B */
+ PAD_CFG_NF(GPP_H12, NONE, DEEP, NF4),
+ /* H13 : GPP_H13 ==> ISH_GP7B */
+ PAD_CFG_NF(GPP_H13, NONE, DEEP, NF4),
/* H14 : Not available */
PAD_NC(GPP_H14, NONE),
/* H15 : DDPB_CTRLCLK ==> SOC_DP2_CTRL_CLK */