diff options
Diffstat (limited to 'src/mainboard')
19 files changed, 1624 insertions, 0 deletions
diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index 9e5bc8a836..650ef9a63e 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -44,12 +44,14 @@ config VARIANT_DIR default "cyan" if BOARD_GOOGLE_CYAN default "edgar" if BOARD_GOOGLE_EDGAR default "reks" if BOARD_GOOGLE_REKS + default "terra" if BOARD_GOOGLE_TERRA config MAINBOARD_PART_NUMBER string default "Cyan" if BOARD_GOOGLE_CYAN default "Edgar" if BOARD_GOOGLE_EDGAR default "Reks" if BOARD_GOOGLE_REKS + default "Terra" if BOARD_GOOGLE_TERRA config MAINBOARD_VENDOR string @@ -60,6 +62,7 @@ config DEVICETREE default "variants/cyan/devicetree.cb" if BOARD_GOOGLE_CYAN default "variants/edgar/devicetree.cb" if BOARD_GOOGLE_EDGAR default "variants/reks/devicetree.cb" if BOARD_GOOGLE_REKS + default "variants/terra/devicetree.cb" if BOARD_GOOGLE_TERRA config VGA_BIOS_FILE string @@ -84,5 +87,6 @@ config GBB_HWID default "CYAN TEST A-A 1829" if BOARD_GOOGLE_CYAN default "EDGAR TEST A-A 2507" if BOARD_GOOGLE_EDGAR default "REKS TEST A-A 3004" if BOARD_GOOGLE_REKS + default "TERRA TEST A-A 1650" if BOARD_GOOGLE_TERRA endif # BOARD_GOOGLE_BASEBOARD_CYAN diff --git a/src/mainboard/google/cyan/Kconfig.name b/src/mainboard/google/cyan/Kconfig.name index 8c70a9c457..c6c4d20c08 100644 --- a/src/mainboard/google/cyan/Kconfig.name +++ b/src/mainboard/google/cyan/Kconfig.name @@ -9,3 +9,7 @@ config BOARD_GOOGLE_EDGAR config BOARD_GOOGLE_REKS bool "Reks" select BOARD_GOOGLE_BASEBOARD_CYAN + +config BOARD_GOOGLE_TERRA + bool "Terra" + select BOARD_GOOGLE_BASEBOARD_CYAN diff --git a/src/mainboard/google/cyan/acpi/dptf.asl b/src/mainboard/google/cyan/acpi/dptf.asl index d0eaadd94f..3ecb040440 100644 --- a/src/mainboard/google/cyan/acpi/dptf.asl +++ b/src/mainboard/google/cyan/acpi/dptf.asl @@ -18,4 +18,6 @@ #include <variant/acpi/dptf.asl> /* Include SoC DPTF */ +#if !IS_ENABLED(CONFIG_BOARD_GOOGLE_TERRA) #include <acpi/dptf/dptf.asl> +#endif diff --git a/src/mainboard/google/cyan/dsdt.asl b/src/mainboard/google/cyan/dsdt.asl index cb6d91a5b8..a49b1a91a0 100644 --- a/src/mainboard/google/cyan/dsdt.asl +++ b/src/mainboard/google/cyan/dsdt.asl @@ -36,7 +36,11 @@ DefinitionBlock( Device (PCI0) { #include <acpi/southcluster.asl> +#if IS_ENABLED(CONFIG_BOARD_GOOGLE_TERRA) + #include <variant/acpi/cpu.asl> +#else #include <acpi/dptf/cpu.asl> +#endif } /* Dynamic Platform Thermal Framework */ diff --git a/src/mainboard/google/cyan/spd/micron_2GiB_dimm_EDF8132A3MA-GD-F-R.spd.hex b/src/mainboard/google/cyan/spd/micron_2GiB_dimm_EDF8132A3MA-GD-F-R.spd.hex new file mode 100644 index 0000000000..44cd73c495 --- /dev/null +++ b/src/mainboard/google/cyan/spd/micron_2GiB_dimm_EDF8132A3MA-GD-F-R.spd.hex @@ -0,0 +1,32 @@ +91 20 F1 03 04 11 05 0B +03 11 01 08 0A 00 40 01 +78 78 90 50 90 11 50 E0 +10 04 3C 3C 01 90 00 00 +00 00 00 00 00 00 00 A8 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 02 FE 00 +00 00 00 00 00 00 00 00 +45 44 46 38 31 33 32 41 +33 4D 41 2D 47 44 2D 46 +20 20 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/cyan/spd/micron_2GiB_dimm_MT52L256M32D1PF-107WT.spd.hex b/src/mainboard/google/cyan/spd/micron_2GiB_dimm_MT52L256M32D1PF-107WT.spd.hex new file mode 100644 index 0000000000..5fd8b40a65 --- /dev/null +++ b/src/mainboard/google/cyan/spd/micron_2GiB_dimm_MT52L256M32D1PF-107WT.spd.hex @@ -0,0 +1,32 @@ +91 20 F1 03 05 19 05 03 +03 11 01 08 09 00 00 05 +78 78 90 50 90 11 50 E0 +90 06 3C 3C 01 90 00 00 +00 10 CA FA 00 00 00 A8 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2C 00 +00 00 00 00 00 00 75 8C +4D 54 35 32 4C 32 35 36 +4D 33 32 44 31 50 46 2D +31 30 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/cyan/variants/terra/Makefile.inc b/src/mainboard/google/cyan/variants/terra/Makefile.inc new file mode 100644 index 0000000000..48d1d96d2a --- /dev/null +++ b/src/mainboard/google/cyan/variants/terra/Makefile.inc @@ -0,0 +1,42 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2015 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += romstage.c +romstage-y += spd_util.c + +ramstage-y += gpio.c +ramstage-y += ramstage.c + +SPD_BIN = $(obj)/spd.bin + +SPD_SOURCES = samsung_dimm_K4E8E304EE-EGCE +SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF +SPD_SOURCES += micron_2GiB_dimm_EDF8132A3MA-GD-F-R +SPD_SOURCES += micron_2GiB_dimm_MT52L256M32D1PF-107WT + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/cyan/variants/terra/board_info.txt b/src/mainboard/google/cyan/variants/terra/board_info.txt new file mode 100644 index 0000000000..72fcabf9ca --- /dev/null +++ b/src/mainboard/google/cyan/variants/terra/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Terra +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/cyan/variants/terra/devicetree.cb b/src/mainboard/google/cyan/variants/terra/devicetree.cb new file mode 100644 index 0000000000..2feb1a399c --- /dev/null +++ b/src/mainboard/google/cyan/variants/terra/devicetree.cb @@ -0,0 +1,150 @@ +chip soc/intel/braswell + + ############################################################ + # Set the parameters for MemoryInit + ############################################################ + + register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB + + register "PcdMrcInitMmioSize" = "0x0800" + register "PcdMrcInitSpdAddr1" = "0xa0" + register "PcdMrcInitSpdAddr2" = "0xa2" + register "PcdIgdDvmt50PreAlloc" = "1" + register "PcdApertureSize" = "2" + register "PcdGttSize" = "1" + register "PcdDvfsEnable" = "1" + register "PcdCaMirrorEn" = "1" + + ############################################################ + # Set the parameters for SiliconInit + ############################################################ + + register "PcdSdcardMode" = "PCH_ACPI_MODE" + register "PcdEnableHsuart0" = "0" + register "PcdEnableHsuart1" = "1" + register "PcdEnableAzalia" = "1" + register "PcdEnableXhci" = "1" + register "PcdEnableLpe" = "1" + register "PcdEnableDma0" = "1" + register "PcdEnableDma1" = "1" + register "PcdEnableI2C0" = "0" + register "PcdEnableI2C1" = "1" + register "PcdEnableI2C2" = "0" + register "PcdEnableI2C3" = "0" + register "PcdEnableI2C4" = "1" + register "PcdEnableI2C5" = "1" + register "PcdEnableI2C6" = "0" + register "PunitPwrConfigDisable" = "0" # Enable SVID + register "ChvSvidConfig" = "SVID_PMIC_CONFIG" + register "PcdEmmcMode" = "PCH_ACPI_MODE" + register "PcdUsb3ClkSsc" = "1" + register "PcdDispClkSsc" = "1" + register "PcdSataClkSsc" = "1" + register "PcdEnableSata" = "0" # Disable SATA + register "Usb2Port0PerPortPeTxiSet" = "7" + register "Usb2Port0PerPortTxiSet" = "5" + register "Usb2Port0IUsbTxEmphasisEn" = "2" + register "Usb2Port0PerPortTxPeHalf" = "1" + register "Usb2Port1PerPortPeTxiSet" = "7" + register "Usb2Port1PerPortTxiSet" = "3" + register "Usb2Port1IUsbTxEmphasisEn" = "2" + register "Usb2Port1PerPortTxPeHalf" = "1" + register "Usb2Port2PerPortPeTxiSet" = "7" + register "Usb2Port2PerPortTxiSet" = "3" + register "Usb2Port2IUsbTxEmphasisEn" = "2" + register "Usb2Port2PerPortTxPeHalf" = "1" + register "Usb2Port3PerPortPeTxiSet" = "7" + register "Usb2Port3PerPortTxiSet" = "3" + register "Usb2Port3IUsbTxEmphasisEn" = "2" + register "Usb2Port3PerPortTxPeHalf" = "1" + register "Usb2Port4PerPortPeTxiSet" = "7" + register "Usb2Port4PerPortTxiSet" = "3" + register "Usb2Port4IUsbTxEmphasisEn" = "2" + register "Usb2Port4PerPortTxPeHalf" = "1" + register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a" + register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" + register "PcdSataInterfaceSpeed" = "3" + register "PcdPchSsicEnable" = "1" + register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM + register "PMIC_I2CBus" = "1" + register "ISPEnable" = "0" # Disable IUNIT + register "ISPPciDevConfig" = "3" + register "PcdSdDetectChk" = "0" # Disable SD card detect + register "I2C0Frequency" = "1" + register "I2C1Frequency" = "2" # Set the PMIC clock speed to 1Mhz + register "I2C2Frequency" = "1" + register "I2C3Frequency" = "1" + register "I2C4Frequency" = "1" + register "I2C5Frequency" = "1" + register "I2C6Frequency" = "1" + + # LPE audio codec settings + register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock + + # Enable devices in ACPI mode + register "lpss_acpi_mode" = "1" + register "emmc_acpi_mode" = "1" + register "sd_acpi_mode" = "1" + register "lpe_acpi_mode" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + # EDS Table 24-4, Figure 24-5 + device pci 00.0 on end # 8086 2280 - SoC transaction router + device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display + device pci 03.0 off end # 8086 22b8 - Camera and Image Processor + device pci 0b.0 on end # 8086 22dc - ? + device pci 10.0 on end # 8086 2294 - MMC Port + device pci 11.0 off end # 8086 0F15 - SDIO Port + device pci 12.0 on end # 8086 0F16 - SD Port + device pci 13.0 off end # 8086 22a3 - Sata controller + device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time + device pci 15.0 on end # 8086 22a8 - LP Engine Audio + device pci 16.0 off end # 8086 22b7 - USB device + device pci 18.0 on end # 8086 22c0 - SIO - DMA + device pci 18.1 off end # 8086 22c1 - I2C Port 1 + device pci 18.2 on end # 8086 22c2 - I2C Port 2 + device pci 18.3 off end # 8086 22c3 - I2C Port 3 + device pci 18.4 off end # 8086 22c4 - I2C Port 4 + device pci 18.5 on end # 8086 22c5 - I2C Port 5 + device pci 18.6 on end # 8086 22c6 - I2C Port 6 + device pci 18.7 off end # 8086 22c7 - I2C Port 7 + device pci 1a.0 off end # 8086 0F18 - Trusted Execution Engine + device pci 1b.0 on end # 8086 0F04 - HD Audio + device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1 + device pci 1c.1 off end # 8086 0000 - PCIe Root Port 2 + device pci 1c.2 on end # 8086 0000 - PCIe Root Port 3 + device pci 1c.3 off end # 8086 0000 - PCIe Root Port 4 + device pci 1e.0 on end # 8086 2286 - SIO - DMA + device pci 1e.1 off end # 8086 0F08 - PWM 1 + device pci 1e.2 off end # 8086 0F09 - PWM 2 + device pci 1e.3 on end # 8086 228a - HSUART 1 + device pci 1e.4 off end # 8086 228c - HSUART 2 + device pci 1e.5 on end # 8086 228e - SPI 1 + device pci 1e.6 off end # 8086 2290 - SPI 2 + device pci 1e.7 off end # 8086 22ac - SPI 3 + device pci 1f.0 on # 8086 229c - LPC bridge + chip drivers/pc80/tpm + # Rising edge interrupt + register "irq_polarity" = "2" + device pnp 0c31.0 on + irq 0x70 = 10 + end + end + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC Bridge + device pci 1f.3 off end # 8086 0F12 - SMBus 0 + end +end diff --git a/src/mainboard/google/cyan/variants/terra/gpio.c b/src/mainboard/google/cyan/variants/terra/gpio.c new file mode 100644 index 0000000000..200ef2b26a --- /dev/null +++ b/src/mainboard/google/cyan/variants/terra/gpio.c @@ -0,0 +1,257 @@ +/* + * This file is part of the coreboot project. + * + * Copyright(C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mainboard/google/cyan/irqroute.h> +#include <soc/gpio.h> +#include <stdlib.h> + +/* South East Community */ +static const struct soc_gpio_map gpse_gpio_map[] = { + Native_M1,/* MF_PLT_CLK0 */ + GPIO_NC, /* 01 PWM1 */ + GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */ + GPIO_NC, /* 03 MF_PLT_CLK4 */ + GPIO_NC, /* 04 MF_PLT_CLK3 */ + GPIO_NC, /* PWM0 05 */ + GPIO_NC, /* 06 MF_PLT_CLK5 */ + GPIO_NC, /* 07 MF_PLT_CLK2 */ + GPIO_NC, /* 15 SDMMC2_D3_CD_B */ + Native_M1, /* 16 SDMMC1_CLK */ + NATIVE_PU20K(1), /* 17 SDMMC1_D0 */ + GPIO_NC, /* 18 SDMMC2_D1 */ + GPIO_NC, /* 19 SDMMC2_CLK */ + NATIVE_PU20K(1),/* 20 SDMMC1_D2 */ + GPIO_NC, /* 21 SDMMC2_D2 */ + GPIO_NC, /* 22 SDMMC2_CMD */ + NATIVE_PU20K(1), /* 23 SDMMC1_CMD */ + NATIVE_PU20K(1), /* 24 SDMMC1_D1 */ + GPIO_NC, /* 25 SDMMC2_D0 */ + NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */ + NATIVE_PU20K(1), /* 30 SDMMC3_D1 */ + Native_M1, /* 31 SDMMC3_CLK */ + NATIVE_PU20K(1), /* 32 SDMMC3_D3 */ + NATIVE_PU20K(1), /* 33 SDMMC3_D2 */ + NATIVE_PU20K(1), /* 34 SDMMC3_CMD */ + NATIVE_PU20K(1), /* 35 SDMMC3_D0 */ + NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */ + NATIVE_PU20K(1), /* 46 LPC_CLKRUNB */ + NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */ + Native_M1, /* 48 LPC_FRAMEB */ + Native_M1, /* 49 MF_LPC_CLKOUT1 */ + NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */ + Native_M1, /* 51 MF_LPC_CLKOUT0 */ + NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */ + Native_M1,/* SPI1_MISO */ + Native_M1, /* 61 SPI1_CS0_B */ + Native_M1, /* SPI1_CLK */ + NATIVE_PU20K(1), /* 63 MMC1_D6 */ + Native_M1, /* 62 SPI1_MOSI */ + NATIVE_PU20K(1), /* 65 MMC1_D5 */ + GPIO_NC, /* SPI1_CS1_B 66 */ + NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */ + NATIVE_PU20K(1), /* 68 MMC1_D7 */ + GPIO_NC, /* 69 MMC1_RCLK */ + Native_M1, /* 75 GPO USB_OC1_B */ + Native_M1, /* 76 PMU_RESETBUTTON_B */ + GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA), + /* GPIO_ALERT 77 */ + Native_M1, /* 78 SDMMC3_PWR_EN_B */ + GPIO_NC, /* 79 GPI ILB_SERIRQ */ + Native_M1, /* 80 USB_OC0_B */ + NATIVE_INT_PU20K(1, L1), /* 81 SDMMC3_CD_B */ + GPIO_NC, /* 82 spkr asummed gpio number */ + Native_M1, /* 83 SUSPWRDNACK */ + SPARE_PIN,/* 84 spare pin */ + Native_M1, /* 85 SDMMC3_1P8_EN */ + GPIO_END +}; + + +/* South West Community */ +static const struct soc_gpio_map gpsw_gpio_map[] = { + GPIO_NC, /* 00 FST_SPI_D2 */ + Native_M1, /* 01 FST_SPI_D0 */ + Native_M1, /* 02 FST_SPI_CLK */ + GPIO_NC, /* 03 FST_SPI_D3 */ + GPIO_NC, /* GPO FST_SPI_CS1_B */ + Native_M1, /* 05 FST_SPI_D1 */ + Native_M1, /* 06 FST_SPI_CS0_B */ + GPIO_NC, /* 07 FST_SPI_CS2_B */ + GPIO_NC, /* 15 UART1_RTS_B */ + Native_M2, /* 16 UART1_RXD */ + GPIO_NC, /* 17 UART2_RXD */ + GPIO_NC, /* 18 UART1_CTS_B */ + GPIO_NC, /* 19 UART2_RTS_B */ + Native_M2, /* 20 UART1_TXD */ + GPIO_NC, /* 21 UART2_TXD */ + GPIO_NC, /* 22 UART2_CTS_B */ + GPIO_NC, /* 30 MF_HDA_CLK */ + GPIO_NC, /* 31 GPIO_SW31/MF_HDA_RSTB */ + GPIO_NC, /* 32 GPIO_SW32 /MF_HDA_SDI0 */ + GPIO_NC, /* 33 MF_HDA_SDO */ + GPIO_NC, /* 34 MF_HDA_DOCKRSTB */ + GPIO_NC, /* 35 MF_HDA_SYNC */ + GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ + GPIO_NC, /* 37 MF_HDA_DOCKENB */ + NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */ + Native_M2, /* 47 I2C6_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */ + GPIO_NC, /* 49 I2C_NFC_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 50 I2C4_SCL */ + GPIO_NC, /* 51 I2C6_SCL */ + GPIO_NC, /* 52 I2C_NFC_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */ + GPIO_NC, /* 61 I2C0_SDA */ + GPIO_NC, /* 62 I2C2_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 63 I2C1_SCL */ + GPIO_INPUT_NO_PULL, /* 64 I2C3_SDA RAMID3*/ + GPIO_NC, /* 65 I2C0_SCL */ + GPIO_NC, /* 66 I2C2_SCL */ + GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */ + GPIO_OUT_HIGH, /* 75 SATA_GP0 */ + GPIO_NC, /* 76 GPI SATA_GP1 */ + GPIO_INPUT_PU_20K, /* 77 SATA_LEDN, EC_IN_RW */ + GPIO_NC, /* 78 SATA_GP2 */ + GPIO_NC, /* 79 MF_SMB_ALERTB */ + GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ + Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ + /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */ + Native_M1, /* 90 PCIE_CLKREQ0B */ + GPIO_INPUT_PU_20K, /* 91 GPI PCIE_CLKREQ1B/LTE_WAKE# */ + Native_M1, /* 92 GP_SSP_2_CLK */ + NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ + Native_M1, /* 94 GP_SSP_2_RXD */ + GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ + Native_M1, /* 96 GP_SSP_2_FS */ + NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ + GPIO_END +}; + + +/* North Community */ +static const struct soc_gpio_map gpn_gpio_map[] = { + GPIO_NC, /* 00 GPIO_DFX0 */ + GPIO_NC, /* 01 GPIO_DFX3 */ + GPIO_NC, /* 02 GPIO_DFX7 */ + GPIO_NC, /* 03 GPIO_DFX1 */ + GPIO_NC, /* 04 GPIO_DFX5 */ + GPIO_NC, /* 05 GPIO_DFX4 */ + GPIO_NC, /* 06 GPIO_DFX8 */ + GPIO_NC, /* 07 GPIO_DFX2 */ + GPIO_NC, /* 08 GPIO_DFX6 */ + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , + UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ + GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ + GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), + /* 17 GPIO_SUS3 */ + GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 18 GPIO_SUS7 */ + GPIO_NC, /* 19 GPIO_SUS1 */ + GPIO_NC, /* 20 GPIO_SUS5 */ + GPIO_NC, /* 21 SEC_GPIO_SUS11 */ + GPIO_NC, /* 22 GPIO_SUS4 */ + GPIO_NC, + /* 23 SEC_GPIO_SUS8 */ + Native_M6, /* 24 GPIO_SUS2 */ + GPIO_INPUT_PU_5K,/* 25 GPIO_SUS6 */ + Native_M1, /* 26 CX_PREQ_B */ + GPIO_NC, /* 27 SEC_GPIO_SUS9 */ + Native_M1, /* 30 TRST_B */ + Native_M1, /* 31 TCK */ + GPIO_SKIP, /* 32 PROCHOT_B */ + GPIO_SKIP, /* 33 SVID0_DATA */ + Native_M1, /* 34 TMS */ + GPIO_NC, /* 35 CX_PRDY_B_2 */ + GPIO_NC, /* 36 TDO_2 */ + Native_M1, /* 37 CX_PRDY_B */ + GPIO_SKIP, /* 38 SVID0_ALERT_B */ + Native_M1, /* 39 TDO */ + GPIO_SKIP, /* 40 SVID0_CLK */ + Native_M1, /* 41 TDI */ + Native_M2, /* 45 GP_CAMERASB05 */ + Native_M2, /* 46 GP_CAMERASB02 */ + Native_M2, /* 47 GP_CAMERASB08 */ + Native_M2, /* 48 GP_CAMERASB00 */ + Native_M2, /* 49 GP_CAMERASBO6 */ + GPIO_NC, /* 50 GP_CAMERASB10 */ + Native_M2, /* 51 GP_CAMERASB03 */ + GPIO_NC, /* 52 GP_CAMERASB09 */ + Native_M2, /* 53 GP_CAMERASB01 */ + Native_M2, /* 54 GP_CAMERASB07 */ + GPIO_NC, /* 55 GP_CAMERASB11 */ + Native_M2, /* 56 GP_CAMERASB04 */ + GPIO_NC, /* 60 PANEL0_BKLTEN */ + GPIO_NC, /* 61 HV_DDI0_HPD */ + NATIVE_PU1K_M1, /* 62 HV_DDI2_DDC_SDA */ + Native_M1, /* 63 PANEL1_BKLTCTL */ + NATIVE_TX_RX_EN, /* 64 HV_DDI1_HPD */ + GPIO_NC, /* 65 PANEL0_BKLTCTL */ + GPIO_NC, /* 66 HV_DDI0_DDC_SDA */ + NATIVE_PU1K_M1, /* 67 HV_DDI2_DDC_SCL */ + NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */ + Native_M1, /* 69 PANEL1_VDDEN */ + Native_M1, /* 70 PANEL1_BKLTEN */ + GPIO_NC, /* 71 HV_DDI0_DDC_SCL */ + GPIO_NC, /* 72 PANEL0_VDDEN */ + GPIO_END +}; + + +/* East Community */ +static const struct soc_gpio_map gpe_gpio_map[] = { + Native_M1, /* 00 PMU_SLP_S3_B */ + GPIO_NC, /* 01 PMU_BATLOW_B */ + Native_M1, /* 02 SUS_STAT_B */ + Native_M1, /* 03 PMU_SLP_S0IX_B */ + Native_M1, /* 04 PMU_AC_PRESENT */ + Native_M1, /* 05 PMU_PLTRST_B */ + Native_M1, /* 06 PMU_SUSCLK */ + GPIO_NC, /* 07 PMU_SLP_LAN_B */ + Native_M1, /* 08 PMU_PWRBTN_B */ + Native_M1, /* 09 PMU_SLP_S4_B */ + NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */ + GPIO_NC, /* 11 PMU_WAKE_LAN_B */ + GPIO_NC, /* 15 MF_GPIO_3 */ + GPIO_NC, /* 16 MF_GPIO_7 */ + GPIO_NC, /* 17 MF_I2C1_SCL */ + GPIO_NC, /* 18 MF_GPIO_1 */ + GPIO_NC, /* 19 MF_GPIO_5 */ + GPIO_NC, /* 20 MF_GPIO_9 */ + GPIO_NC, /* 21 MF_GPIO_0 */ + GPIO_INPUT_PU_20K, /* 22 MF_GPIO_4 */ + GPIO_NC, /* 23 MF_GPIO_8 */ + GPIO_NC, /* 24 MF_GPIO_2 */ + GPIO_NC, /* 25 MF_GPIO_6 */ + GPIO_NC, /* 26 MF_I2C1_SDA */ + GPIO_END +}; + + +static struct soc_gpio_config gpio_config = { + /* BSW */ + .north = gpn_gpio_map, + .southeast = gpse_gpio_map, + .southwest = gpsw_gpio_map, + .east = gpe_gpio_map +}; + +struct soc_gpio_config *mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/charger.asl b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/charger.asl new file mode 100644 index 0000000000..ee247f2065 --- /dev/null +++ b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/charger.asl @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2105 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (TCHG) +{ + Name (_HID, "INT3403") + Name (_UID, 0) + Name (PTYP, 0x0B) + Name (_STR, Unicode("Battery Charger")) + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* Return charger performance states defined by Terra2 or Terra3 mainboard */ + Method (PPSS) + { + If (LEqual (\_SB.GPID, TERRA2_PROJECT_ID)) + { + Return (\_SB.CPT2) + } Else { + Return (\_SB.CPT3) + } + } + + /* Return maximum charger current limit */ + Method (PPPC) + { + /* Convert size of PPSS table to index */ + If (LEqual (\_SB.GPID, TERRA2_PROJECT_ID)) + { + Store (SizeOf (\_SB.CPT2), Local0) + } Else { + Store (SizeOf (\_SB.CPT3), Local0) + } + + Decrement (Local0) + + /* Check if charging is disabled (AC removed) */ + If (LEqual (\_SB.PCI0.LPCB.EC0.ACEX, Zero)) { + /* Return last power state */ + Return (Local0) + } Else { + /* Return highest power state */ + Return (0) + } + + Return (0) + } + + /* Set charger current limit */ + Method (SPPC, 1) + { + /* Retrieve Control (index 4) for specified PPSS level */ + /* Convert size of PPSS table to index */ + If (LEqual (\_SB.GPID, TERRA2_PROJECT_ID)) + { + Store (DeRefOf (Index (DeRefOf (Index + (\_SB.CPT2, ToInteger (Arg0))), 4)), Local0) + } Else { + Store (DeRefOf (Index (DeRefOf (Index + (\_SB.CPT3, ToInteger (Arg0))), 4)), Local0) + } + + /* Pass Control value to EC to limit charging */ + \_SB.PCI0.LPCB.EC0.CHGS (Local0) + } + + /* Initialize charger participant */ + Method (INIT) + { + /* Disable charge limit */ + \_SB.PCI0.LPCB.EC0.CHGD () + } +} diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl new file mode 100644 index 0000000000..bab215def1 --- /dev/null +++ b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl @@ -0,0 +1,227 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef DPTF_CPU_PASSIVE +#define DPTF_CPU_PASSIVE 80 +#endif + +#ifndef DPTF_CPU_CRITICAL +#define DPTF_CPU_CRITICAL 90 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC0 +#define DPTF_CPU_ACTIVE_AC0 90 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC1 +#define DPTF_CPU_ACTIVE_AC1 80 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC2 +#define DPTF_CPU_ACTIVE_AC2 70 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC3 +#define DPTF_CPU_ACTIVE_AC3 60 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC4 +#define DPTF_CPU_ACTIVE_AC4 50 +#endif + +External (\_PR.CP00._TSS, MethodObj) +External (\_PR.CP00._TPC, MethodObj) +External (\_PR.CP00._PTC, PkgObj) +External (\_PR.CP00._TSD, PkgObj) +External (\_PR.CP00._PSS, MethodObj) +External (\_SB.DPTF.CTOK, MethodObj) +External (\_SB.GPID, MethodObj) + +Device (B0DB) +{ + Name (_ADR, 0x000B0000) /* Bus 0, Device B, Function 0 */ + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* + * Processor Throttling Controls + */ + + Method (_TSS) + { + If (CondRefOf (\_PR.CP00._TSS)) { + Return (\_PR.CP00._TSS) + } Else { + Return (Package () + { + Package () { 0, 0, 0, 0, 0 } + }) + } + } + + Method (_TPC) + { + If (CondRefOf (\_PR.CP00._TPC)) { + Return (\_PR.CP00._TPC) + } Else { + Return (0) + } + } + + Method (_PTC) + { + If (CondRefOf (\_PR.CP00._PTC)) { + Return (\_PR.CP00._PTC) + } Else { + Return (Package () + { + Buffer () { 0 }, + Buffer () { 0 } + }) + } + } + + Method (_TSD) + { + If (CondRefOf (\_PR.CP00._TSD)) { + Return (\_PR.CP00._TSD) + } Else { + Return (Package () + { + Package () { 5, 0, 0, 0, 0 } + }) + } + } + + Method (_TDL) + { + If (CondRefOf (\_PR.CP00._TSS)) { + Store (SizeOf (\_PR.CP00._TSS ()), Local0) + Decrement (Local0) + Return (Local0) + } Else { + Return (0) + } + } + + /* + * Processor Performance Control + */ + + Method (_PPC) + { + Return (0) + } + + Method (SPPC, 1) + { + Store (Arg0, \PPCM) + + /* Notify OS to re-read _PPC limit on each CPU */ + \PPCN () + } + + Method (_PSS) + { + If (CondRefOf (\_PR.CP00._PSS)) { + Return (\_PR.CP00._PSS) + } Else { + Return (Package () + { + Package () { 0, 0, 0, 0, 0, 0 } + }) + } + } + + Method (_PDL) + { + /* Check for mainboard specific _PDL override */ + If (CondRefOf (\_SB.MPDL)) { + Return (\_SB.MPDL) + } ElseIf (CondRefOf (\_PR.CP00._PSS)) { + Store (SizeOf (\_PR.CP00._PSS ()), Local0) + Decrement (Local0) + Return (Local0) + } Else { + Return (0) + } + } + + /* Return PPCC table defined by Terra2 or Terra3 mainboard */ + Method (PPCC) + { + If (LEqual (\_SB.GPID, TERRA2_PROJECT_ID)) + { + Return (\_SB.PPT2) + } Else { + Return (\_SB.PPT3) + } + } + + /* Return critical thermal point defined by Terra2 or Terra3 mainboard */ + Method (_CRT) + { + If (Lequal(\_SB.GPID, TERRA2_PROJECT_ID)) + { + Return (\_SB.DPTF.CTOK(DPTF_TERRA2_CPU_CRITICAL)) + } Else { + Return (\_SB.DPTF.CTOK(DPTF_TERRA3_CPU_CRITICAL)) + } + } + + /* Return passive thermal point defined by Terra2 or Terra3 mainboard */ + Method (_PSV) + { + If (Lequal(\_SB.GPID, TERRA2_PROJECT_ID)) + { + Return (\_SB.DPTF.CTOK(DPTF_TERRA2_CPU_PASSIVE)) + } Else { + Return (\_SB.DPTF.CTOK(DPTF_TERRA3_CPU_PASSIVE)) + } + } + + Method (_AC0) + { + Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC0)) + } + + Method (_AC1) + { + Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC1)) + } + + Method (_AC2) + { + Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC2)) + } + + Method (_AC3) + { + Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC3)) + } + + Method (_AC4) + { + Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC4)) + } +} diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..775e27b816 --- /dev/null +++ b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/dptf.asl @@ -0,0 +1,235 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2105 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "TMP432_CPU" + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "TMP432_WLAN" + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CHARGER" + +#define DPTF_TERRA2_TSR0_PASSIVE 60 +#define DPTF_TERRA2_TSR0_CRITICAL 75 + +#define DPTF_TERRA2_TSR1_PASSIVE 53 +#define DPTF_TERRA2_TSR1_CRITICAL 75 + +#define DPTF_TERRA2_TSR2_PASSIVE 53 +#define DPTF_TERRA2_TSR2_CRITICAL 75 + +#define DPTF_TERRA3_TSR0_PASSIVE 50 +#define DPTF_TERRA3_TSR0_CRITICAL 75 + +#define DPTF_TERRA3_TSR1_PASSIVE 52 +#define DPTF_TERRA3_TSR1_CRITICAL 75 + +#define DPTF_TERRA3_TSR2_PASSIVE 53 +#define DPTF_TERRA3_TSR2_CRITICAL 75 + +#define DPTF_ENABLE_CHARGER + +/* Terra2 - Charger performance states, board-specific values from charger and EC */ +Name (CPT2, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x320, "mA", 0 }, /* 0.8A */ + Package () { 0, 0, 0, 0, 16, 0x258, "mA", 0 }, /* 0.6A */ + Package () { 0, 0, 0, 0, 8, 0x190, "mA", 0 }, /* 0.4A */ + Package () { 0, 0, 0, 0, 0, 0x64, "mA", 0 }, /* 0.1A */ +}) + +/* Terra3 - Charger performance states, board-specific values from charger and EC */ +Name (CPT3, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x320, "mA", 0 }, /* 0.8A */ + Package () { 0, 0, 0, 0, 16, 0x258, "mA", 0 }, /* 0.6A */ + Package () { 0, 0, 0, 0, 8, 0x190, "mA", 0 }, /* 0.4A */ + Package () { 0, 0, 0, 0, 0, 0x64, "mA", 0 }, /* 0.1A */ +}) + +/* Mainboard specific _PDL is 1GHz */ +Name (MPDL, 8) + +/* Terra2 - Thermal Relationship Table for method _TRT */ +Name (TRT2, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 10, 0, 0, 0, 0 }, +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 0 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 200, 100, 0, 0, 0, 0 }, +#endif + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 100, 0, 0, 0, 0 }, +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 100, 0, 0, 0, 0 }, +#endif + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR1, 200, 100, 0, 0, 0, 0 }, +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 2 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 100, 100, 0, 0, 0, 0 }, +#endif + /* CPU Effect on Temp Sensor 2 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR2, 200, 100, 0, 0, 0, 0 }, +}) + +/* Terra3 - Thermal Relationship Table for method _TRT */ +Name (TRT3, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 10, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 100, 0, 0, 0, 0 }, +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 100, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR1, 200, 100, 0, 0, 0, 0 }, + + /* Charger Effect on Temp Sensor 2 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 100, 100, 0, 0, 0, 0 }, +}) + +/* Terra2 - PPCC table defined by mainboard for method PPCC */ +Name (PPT2, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 1600, /* PowerLimitMinimum */ + 10000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 8000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) + +/* Terra3 - PPCC table defined by mainboard for method PPCC */ +Name (PPT3, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 1600, /* PowerLimitMinimum */ + 10000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 8000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) + +Device (DPTF) +{ + Name (_HID, EISAID ("INT3400")) + Name (_UID, 0) + + Name (IDSP, Package() + { + /* DPPM Passive Policy 1.0 */ + ToUUID ("42A441D6-AE6A-462B-A84B-4A8CE79027D3"), + + /* DPPM Critical Policy */ + ToUUID ("97C68AE7-15FA-499c-B8C9-5DA81D606E0A"), + + /* DPPM Cooling Policy */ + ToUUID ("16CAF1B7-DD38-40ED-B1C1-1B8A1913D531"), + }) + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* + * Arg0: Buffer containing UUID + * Arg1: Integer containing Revision ID of buffer format + * Arg2: Integer containing count of entries in Arg3 + * Arg3: Buffer containing list of DWORD capabilities + * Return: Buffer containing list of DWORD capabilities + */ + Method (_OSC, 4, Serialized) + { + /* Check for Passive Policy UUID */ + If (LEqual (DeRefOf (Index (IDSP, 0)), Arg0)) { + /* Initialize Thermal Devices */ + ^TINI () + +#ifdef DPTF_ENABLE_CHARGER + /* Initialize Charger Device */ + ^TCHG.INIT () +#endif + } + + Return (Arg3) + } + + /* Priority based _TRT */ + Name (TRTR, 1) + + /* Return TRT table defined by Terra2 or Terra3 mainboard */ + Method (_TRT) + { + If (Lequal(\_SB.GPID, TERRA2_PROJECT_ID)) + { + Return (\_SB.TRT2) + } Else { + Return (\_SB.TRT3) + } + } + + /* Convert from Degrees C to 1/10 Kelvin for ACPI */ + Method (CTOK, 1) { + /* 10th of Degrees C */ + Multiply (Arg0, 10, Local0) + + /* Convert to Kelvin */ + Add (Local0, 2732, Local0) + + Return (Local0) + } + + /* Include Thermal Participants */ + #include "thermal.asl" + +#ifdef DPTF_ENABLE_CHARGER + /* Include Charger Participant */ + #include "charger.asl" +#endif +} diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000000..32bdbfbb92 --- /dev/null +++ b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/mainboard.asl @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Matt DeVillier + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Elan trackpad */ +#include <acpi/trackpad_elan.asl> + +/* Realtek audio codec */ +#include <acpi/codec_realtek.asl> + +Scope (\_SB) +{ + Method (GPID, 0, Serialized) // GPID: Get Project ID for Terra2/Terra3 + { + And( ShiftRight (\BDID, 3, Local0), 0x01, Local0) + Return (Local0) + } +} diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl new file mode 100644 index 0000000000..6879076415 --- /dev/null +++ b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl @@ -0,0 +1,255 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2105 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Thermal Threshold Event Handler */ +Method (TEVT, 1, NotSerialized) +{ + Store (ToInteger (Arg0), Local0) + +#ifdef DPTF_TSR0_SENSOR_ID + If (LEqual (Local0, DPTF_TSR0_SENSOR_ID)) { + Notify (^TSR0, 0x90) + } +#endif +#ifdef DPTF_TSR1_SENSOR_ID + If (LEqual (Local0, DPTF_TSR1_SENSOR_ID)) { + Notify (^TSR1, 0x90) + } +#endif +#ifdef DPTF_TSR2_SENSOR_ID + If (LEqual (Local0, DPTF_TSR2_SENSOR_ID)) { + Notify (^TSR2, 0x90) + } +#endif +} + +/* Thermal device initialization - Disable Aux Trip Points */ +Method (TINI) +{ +#ifdef DPTF_TSR0_SENSOR_ID + ^TSR0.PATD () +#endif +#ifdef DPTF_TSR1_SENSOR_ID + ^TSR1.PATD () +#endif +#ifdef DPTF_TSR2_SENSOR_ID + ^TSR2.PATD () +#endif +} + +#ifdef DPTF_TSR0_SENSOR_ID +Device (TSR0) +{ + Name (_HID, EISAID ("INT3403")) + Name (_UID, 1) + Name (PTYP, 0x03) + Name (TMPI, DPTF_TSR0_SENSOR_ID) + Name (_STR, Unicode (DPTF_TSR0_SENSOR_NAME)) + Name (GTSH, 20) /* 2 degree hysteresis */ + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Method (_TMP, 0, Serialized) + { + Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI)) + } + + /* Return passive thermal point defined by Terra2 or Terra3 mainboard */ + Method (_PSV) + { + If (LEqual (\_SB.GPID, TERRA2_PROJECT_ID)) + { + Return (CTOK (DPTF_TERRA2_TSR0_PASSIVE)) + } Else { + Return (CTOK (DPTF_TERRA3_TSR0_PASSIVE)) + } + } + + /* Return critical thermal point defined by Terra2 or Terra3 mainboard */ + Method (_CRT) + { + If (LEqual (\_SB.GPID, TERRA2_PROJECT_ID)) + { + Return (CTOK (DPTF_TERRA2_TSR0_CRITICAL)) + } Else { + Return (CTOK (DPTF_TERRA3_TSR0_CRITICAL)) + } + } + + Name (PATC, 2) + + /* Set Aux Trip Point */ + Method (PAT0, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0) + } + + /* Set Aux Trip Point */ + Method (PAT1, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0) + } + + /* Disable Aux Trip Point */ + Method (PATD, 0, Serialized) + { + \_SB.PCI0.LPCB.EC0.PATD (TMPI) + } +} +#endif + +#ifdef DPTF_TSR1_SENSOR_ID +Device (TSR1) +{ + Name (_HID, EISAID ("INT3403")) + Name (_UID, 2) + Name (PTYP, 0x03) + Name (TMPI, DPTF_TSR1_SENSOR_ID) + Name (_STR, Unicode (DPTF_TSR1_SENSOR_NAME)) + Name (GTSH, 20) /* 2 degree hysteresis */ + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Method (_TMP, 0, Serialized) + { + Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI)) + } + + /* Return passive thermal point defined by Terra2 or Terra3 mainboard */ + Method (_PSV) + { + If (LEqual (\_SB.GPID, TERRA2_PROJECT_ID)) + { + Return (CTOK (DPTF_TERRA2_TSR1_PASSIVE)) + } Else { + Return (CTOK (DPTF_TERRA3_TSR1_PASSIVE)) + } + } + + /* Return critical thermal point defined by Terra2 or Terra3 mainboard */ + Method (_CRT) + { + If (LEqual (\_SB.GPID, TERRA2_PROJECT_ID)) + { + Return (CTOK (DPTF_TERRA2_TSR1_CRITICAL)) + } Else { + Return (CTOK (DPTF_TERRA3_TSR1_CRITICAL)) + } + } + + Name (PATC, 2) + + /* Set Aux Trip Point */ + Method (PAT0, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0) + } + + /* Set Aux Trip Point */ + Method (PAT1, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0) + } + + /* Disable Aux Trip Point */ + Method (PATD, 0, Serialized) + { + \_SB.PCI0.LPCB.EC0.PATD (TMPI) + } +} +#endif + +#ifdef DPTF_TSR2_SENSOR_ID +Device (TSR2) +{ + Name (_HID, EISAID ("INT3403")) + Name (_UID, 3) + Name (PTYP, 0x03) + Name (TMPI, DPTF_TSR2_SENSOR_ID) + Name (_STR, Unicode (DPTF_TSR2_SENSOR_NAME)) + Name (GTSH, 20) /* 2 degree hysteresis */ + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Method (_TMP, 0, Serialized) + { + Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI)) + } + + /* Return passive thermal point defined by Terra2 or Terra3 mainboard */ + Method (_PSV) + { + If (LEqual (\_SB.GPID, TERRA2_PROJECT_ID)) + { + Return (CTOK (DPTF_TERRA2_TSR2_PASSIVE)) + } Else { + Return (CTOK (DPTF_TERRA3_TSR2_PASSIVE)) + } + } + + /* Return critical thermal point defined by Terra2 or Terra3 mainboard */ + Method (_CRT) + { + If (LEqual (\_SB.GPID, TERRA2_PROJECT_ID)) + { + Return (CTOK (DPTF_TERRA2_TSR2_CRITICAL)) + } Else { + Return (CTOK (DPTF_TERRA3_TSR2_CRITICAL)) + } + } + + Name (PATC, 2) + + /* Set Aux Trip Point */ + Method (PAT0, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0) + } + + /* Set Aux Trip Point */ + Method (PAT1, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0) + } + + /* Disable Aux Trip Point */ + Method (PATD, 0, Serialized) + { + \_SB.PCI0.LPCB.EC0.PATD (TMPI) + } +} +#endif diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/onboard.h b/src/mainboard/google/cyan/variants/terra/include/variant/onboard.h new file mode 100644 index 0000000000..613039b98f --- /dev/null +++ b/src/mainboard/google/cyan/variants/terra/include/variant/onboard.h @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/cyan/irqroute.h> + +/* + * Calculation of gpio based irq. + * Gpio banks ordering : GPSW, GPNC, GPEC, GPSE + * Max direct irq (MAX_DIRECT_IRQ) is 114. + * Size of gpio banks are + * GPSW_SIZE = 98 + * GPNC_SIZE = 73 + * GPEC_SIZE = 27 + * GPSE_SIZE = 86 + */ + +/* KBD: Gpio index in N bank */ +#define BOARD_I8042_GPIO_INDEX 17 +/* Audio: Gpio index in SW bank */ +#define JACK_DETECT_GPIO_INDEX 95 +/* SCI: Gpio index in N bank */ +#define BOARD_SCI_GPIO_INDEX 15 +/* Trackpad: Gpio index in N bank */ +#define BOARD_TRACKPAD_GPIO_INDEX 18 + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 5 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +/* SD CARD gpio */ +#define SDCARD_CD 81 + +#define AUDIO_CODEC_HID "10EC5650" +#define AUDIO_CODEC_CID "10EC5650" +#define AUDIO_CODEC_DDN "RTEK Codec Controller" +#define AUDIO_CODEC_I2C_ADDR 0x1A + +#define TERRA2_PROJECT_ID 0x00 + +#define DPTF_TERRA2_CPU_PASSIVE 80 +#define DPTF_TERRA2_CPU_CRITICAL 90 +#define DPTF_TERRA3_CPU_PASSIVE 80 +#define DPTF_TERRA3_CPU_CRITICAL 90 + +/* I2C data hold time */ +#define BOARD_I2C5_DATA_HOLD_TIME 0x1E +#define BOARD_I2C6_DATA_HOLD_TIME 0x1E + +#endif diff --git a/src/mainboard/google/cyan/variants/terra/ramstage.c b/src/mainboard/google/cyan/variants/terra/ramstage.c new file mode 100644 index 0000000000..6ef4360377 --- /dev/null +++ b/src/mainboard/google/cyan/variants/terra/ramstage.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> +#include <boardid.h> +#include <variant/onboard.h> + +void mainboard_silicon_init_params(SILICON_INIT_UPD *params) +{ + uint8_t boardid = 0; + uint8_t projectid = 0; + + boardid = board_id(); + projectid = (boardid >> 3) & 0x01; + + if (projectid == TERRA2_PROJECT_ID) { + params->Usb2Port0PerPortPeTxiSet = 7; + params->Usb2Port0PerPortTxiSet = 6; + params->Usb2Port0IUsbTxEmphasisEn = 3; + params->Usb2Port0PerPortTxPeHalf = 1; + params->Usb2Port1PerPortPeTxiSet = 7; + params->Usb2Port1PerPortTxiSet = 6; + params->Usb2Port1IUsbTxEmphasisEn = 3; + params->Usb2Port1PerPortTxPeHalf = 1; + params->Usb2Port2PerPortPeTxiSet = 7; + params->Usb2Port2PerPortTxiSet = 6; + params->Usb2Port2IUsbTxEmphasisEn = 3; + params->Usb2Port2PerPortTxPeHalf = 1; + params->Usb2Port3PerPortPeTxiSet = 7; + params->Usb2Port3PerPortTxiSet = 6; + params->Usb2Port3IUsbTxEmphasisEn = 3; + params->Usb2Port3PerPortTxPeHalf = 1; + params->Usb2Port4PerPortPeTxiSet = 7; + params->Usb2Port4PerPortTxiSet = 6; + params->Usb2Port4IUsbTxEmphasisEn = 3; + params->Usb2Port4PerPortTxPeHalf = 1; + } else { + params->Usb2Port0PerPortPeTxiSet = 7; + params->Usb2Port0PerPortTxiSet = 6; + params->Usb2Port0IUsbTxEmphasisEn = 3; + params->Usb2Port0PerPortTxPeHalf = 1; + params->Usb2Port1PerPortPeTxiSet = 7; + params->Usb2Port1PerPortTxiSet = 6; + params->Usb2Port1IUsbTxEmphasisEn = 3; + params->Usb2Port1PerPortTxPeHalf = 1; + params->Usb2Port2PerPortPeTxiSet = 7; + params->Usb2Port2PerPortTxiSet = 3; + params->Usb2Port2IUsbTxEmphasisEn = 2; + params->Usb2Port2PerPortTxPeHalf = 1; + params->Usb2Port3PerPortPeTxiSet = 7; + params->Usb2Port3PerPortTxiSet = 6; + params->Usb2Port3IUsbTxEmphasisEn = 3; + params->Usb2Port3PerPortTxPeHalf = 1; + params->Usb2Port4PerPortPeTxiSet = 7; + params->Usb2Port4PerPortTxiSet = 3; + params->Usb2Port4IUsbTxEmphasisEn = 2; + params->Usb2Port4PerPortTxPeHalf = 1; + } +} diff --git a/src/mainboard/google/cyan/variants/terra/romstage.c b/src/mainboard/google/cyan/variants/terra/romstage.c new file mode 100644 index 0000000000..e670461ff8 --- /dev/null +++ b/src/mainboard/google/cyan/variants/terra/romstage.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> +#include <chip.h> +#include <mainboard/google/cyan/spd/spd_util.h> + +void mainboard_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *memory_params) +{ + int ram_id = get_ramid(); + + /* + * RAMID = 3 - 2GiB Micron MT52L256M32D1PF-107 + * RAMID = 11 - 4GiB Micron MT52L256M32D1PF-107 + */ + if (ram_id == 3 || ram_id == 11) { + + /* + * For new micron part, it requires read/receive + * enable training before sending cmds to get MR8. + * To override dram geometry settings as below: + * + * PcdDramWidth = x32 + * PcdDramDensity = 8Gb + * PcdDualRankDram = disable + */ + memory_params->PcdRxOdtLimitChannel0 = 1; + memory_params->PcdRxOdtLimitChannel1 = 1; + memory_params->PcdDisableAutoDetectDram = 1; + memory_params->PcdDramWidth = 2; + memory_params->PcdDramDensity = 3; + memory_params->PcdDualRankDram = 0; + } + + /* Update SPD data */ + memory_params->PcdMemoryTypeEnable = MEM_LPDDR3; + memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0; + memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config; + memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config; +} diff --git a/src/mainboard/google/cyan/variants/terra/spd_util.c b/src/mainboard/google/cyan/variants/terra/spd_util.c new file mode 100644 index 0000000000..7b4629d05a --- /dev/null +++ b/src/mainboard/google/cyan/variants/terra/spd_util.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2017 Matt DeVillier + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <mainboard/google/cyan/spd/spd_util.h> + +/* + * RAMID3 -1: Dual channel SKU, 0: Single channel SKU + * 0b0010 - 2GiB total - 1 x 2GiB Micron EDF8132A3MA-GD-F-R 1600MHz + * 0b0011 - 2GiB total - 1 x 2GiB Micron MT52L256M32D1PF-107WT 1866MHz + * 0b0100 - 2GiB total - 1 x 2GiB Samsung K4E8E304EE-EGCE 1600MHz + * 0b0101 - 2GiB total - 1 x 2GiB Samsung K4E8E324EB-EGCF 1866MHz + * + * 0b1010 - 4GiB total - 2 x 2GiB Micron EDF8132A3MA-GD-F-R 1600MHz + * 0b1011 - 4GiB total - 2 x 2GiB Micron MT52L256M32D1PF-107WT 1866MHz + * 0b1100 - 4GiB total - 2 x 2GiB Samsung K4E8E304EE-EGCE 1600MHz + * 0b1101 - 4GiB total - 2 x 2GiB Samsung K4E8E324EB-EGCF 1866MHz + */ + +int get_variant_spd_index(int ram_id, int *dual) +{ + int spd_index = ram_id & 0x03; + + /* Determine if single or dual channel memory system */ + /* RAMID3 is deterministic for terra */ + *dual = ((ram_id > 3) & 0x1) ? 1 : 0; + + /* Display the RAM type */ + printk(BIOS_DEBUG, dual ? "4GiB " : "2GiB "); + switch (spd_index) { + case 0: + printk(BIOS_DEBUG, "Samsung K4E8E304EE-EGCE 1600MHz\n"); + break; + case 1: + printk(BIOS_DEBUG, "Samsung K4E8E324EB-EGCF 1866MHz\n"); + break; + case 2: + printk(BIOS_DEBUG, "Micron EDF8132A3MA-GD-F-R 1600MHz\n"); + break; + case 3: + printk(BIOS_DEBUG, "Micron MT52L256M32D1PF-107WT 1866MHz\n"); + break; + } + + return spd_index; +} |