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-rw-r--r--src/mainboard/iwill/dk8x/Kconfig2
-rw-r--r--src/mainboard/iwill/dk8x/devicetree.cb6
-rw-r--r--src/mainboard/lanner/em8510/Kconfig2
-rw-r--r--src/mainboard/lanner/em8510/devicetree.cb3
-rw-r--r--src/mainboard/lanner/em8510/romstage.c6
-rw-r--r--src/mainboard/msi/ms7135/Kconfig2
-rw-r--r--src/mainboard/msi/ms7135/devicetree.cb7
-rw-r--r--src/mainboard/msi/ms7135/romstage.c6
8 files changed, 16 insertions, 18 deletions
diff --git a/src/mainboard/iwill/dk8x/Kconfig b/src/mainboard/iwill/dk8x/Kconfig
index 209cc563c5..16eab8dbee 100644
--- a/src/mainboard/iwill/dk8x/Kconfig
+++ b/src/mainboard/iwill/dk8x/Kconfig
@@ -8,7 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
select SOUTHBRIDGE_AMD_AMD8111
select SOUTHBRIDGE_AMD_AMD8131
- select SUPERIO_WINBOND_W83627THF
+ select SUPERIO_WINBOND_W83627THG
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
diff --git a/src/mainboard/iwill/dk8x/devicetree.cb b/src/mainboard/iwill/dk8x/devicetree.cb
index 58646f307c..3888805476 100644
--- a/src/mainboard/iwill/dk8x/devicetree.cb
+++ b/src/mainboard/iwill/dk8x/devicetree.cb
@@ -25,18 +25,18 @@ chip northbridge/amd/amdk8/root_complex
device pci 1.0 off end
end
device pci 1.0 on
- chip superio/winbond/w83627thf
+ # TODO: This is incomplete.
+ chip superio/winbond/w83627thg
device pnp 2e.0 on end
device pnp 2e.1 on end
device pnp 2e.2 on end
device pnp 2e.3 on end
- device pnp 2e.4 on end
device pnp 2e.5 on end
- device pnp 2e.6 on end
device pnp 2e.7 on end
device pnp 2e.8 on end
device pnp 2e.9 on end
device pnp 2e.a on end
+ device pnp 2e.b on end
end
end
device pci 1.1 on end
diff --git a/src/mainboard/lanner/em8510/Kconfig b/src/mainboard/lanner/em8510/Kconfig
index b4d03f78eb..2ffdb842ea 100644
--- a/src/mainboard/lanner/em8510/Kconfig
+++ b/src/mainboard/lanner/em8510/Kconfig
@@ -6,7 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select CPU_INTEL_SOCKET_MPGA479M
select NORTHBRIDGE_INTEL_I855
select SOUTHBRIDGE_INTEL_I82801DX
- select SUPERIO_WINBOND_W83627THF
+ select SUPERIO_WINBOND_W83627THG
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_HARD_RESET
diff --git a/src/mainboard/lanner/em8510/devicetree.cb b/src/mainboard/lanner/em8510/devicetree.cb
index 7df1443066..5784a16981 100644
--- a/src/mainboard/lanner/em8510/devicetree.cb
+++ b/src/mainboard/lanner/em8510/devicetree.cb
@@ -13,7 +13,7 @@ chip northbridge/intel/i855
register "enable_usb" = "0"
register "enable_native_ide" = "0"
device pci 1f.0 on
- chip superio/winbond/w83627thf # link 1
+ chip superio/winbond/w83627thg # link 1
device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
@@ -37,7 +37,6 @@ chip northbridge/intel/i855
irq 0x70 = 1
irq 0x72 = 12
end
- device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # GAME_MIDI_GIPO1
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
diff --git a/src/mainboard/lanner/em8510/romstage.c b/src/mainboard/lanner/em8510/romstage.c
index 6d79e0b3e5..fe4fd69327 100644
--- a/src/mainboard/lanner/em8510/romstage.c
+++ b/src/mainboard/lanner/em8510/romstage.c
@@ -34,11 +34,11 @@
#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
#include "northbridge/intel/i855/raminit.h"
#include "northbridge/intel/i855/debug.c"
-#include "superio/winbond/w83627thf/w83627thf_early_serial.c"
+#include "superio/winbond/w83627thg/w83627thg_early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-#define SERIAL_DEV PNP_DEV(0x2e, W83627THF_SP1)
+#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -65,7 +65,7 @@ void main(unsigned long bist)
#endif
}
- w83627thf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
diff --git a/src/mainboard/msi/ms7135/Kconfig b/src/mainboard/msi/ms7135/Kconfig
index 2de546b730..d8581f731c 100644
--- a/src/mainboard/msi/ms7135/Kconfig
+++ b/src/mainboard/msi/ms7135/Kconfig
@@ -7,7 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_AMD_AMDK8
select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
select SOUTHBRIDGE_NVIDIA_CK804
- select SUPERIO_WINBOND_W83627THF
+ select SUPERIO_WINBOND_W83627THG
select HAVE_BUS_CONFIG
select HAVE_HARD_RESET
select HAVE_OPTION_TABLE
diff --git a/src/mainboard/msi/ms7135/devicetree.cb b/src/mainboard/msi/ms7135/devicetree.cb
index e796b94650..14c6bad1d3 100644
--- a/src/mainboard/msi/ms7135/devicetree.cb
+++ b/src/mainboard/msi/ms7135/devicetree.cb
@@ -11,7 +11,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex
chip southbridge/nvidia/ck804 # Southbridge
device pci 0.0 on end # HT
device pci 1.0 on # LPC
- chip superio/winbond/w83627thf # Super I/O
+ chip superio/winbond/w83627thg # Super I/O
device pnp 4e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
@@ -30,14 +30,13 @@ chip northbridge/amd/amdk8/root_complex # Root complex
io 0x60 = 0x2f8
irq 0x70 = 3
end
- device pnp 4e.5 on # PS/2 keyboard
+ device pnp 4e.5 on # PS/2 keyboard & mouse
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
- device pnp 4e.6 off end # XXX keep allocator happy
- device pnp 4e.7 off end # Game, MIDI, GPIO 1, GPIO 5
+ device pnp 4e.7 off end # Game port, MIDI, GPIO 1 & 5
device pnp 4e.8 off end # GPIO 2
device pnp 4e.9 off end # GPIO 3, GPIO 4
device pnp 4e.a off end # ACPI
diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c
index a4b9cb6567..f6dbb0ae6d 100644
--- a/src/mainboard/msi/ms7135/romstage.c
+++ b/src/mainboard/msi/ms7135/romstage.c
@@ -22,7 +22,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define SERIAL_DEV PNP_DEV(0x4e, W83627THF_SP1)
+#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
#if CONFIG_LOGICAL_CPUS == 1
#define SET_NB_CFG_54 1
@@ -38,7 +38,7 @@
#include <pc80/mc146818rtc.h>
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/winbond/w83627thf/w83627thf_early_serial.c"
+#include "superio/winbond/w83627thg/w83627thg_early_serial.c"
#include <cpu/amd/model_fxx_rev.h>
#include <console/console.h>
@@ -123,7 +123,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
bsp_apicid = init_cpus(cpu_init_detectedx);
}
- w83627thf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 15:56:58 +0000