summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/facebook/fbg1701/devicetree.cb10
-rw-r--r--src/mainboard/google/cyan/devicetree.cb10
-rw-r--r--src/mainboard/intel/strago/devicetree.cb10
-rw-r--r--src/mainboard/portwell/m107/devicetree.cb10
-rw-r--r--src/mainboard/protectli/vault_bsw/devicetree.cb10
5 files changed, 0 insertions, 50 deletions
diff --git a/src/mainboard/facebook/fbg1701/devicetree.cb b/src/mainboard/facebook/fbg1701/devicetree.cb
index 70e950c65e..a340fdc37c 100644
--- a/src/mainboard/facebook/fbg1701/devicetree.cb
+++ b/src/mainboard/facebook/fbg1701/devicetree.cb
@@ -4,14 +4,9 @@ chip soc/intel/braswell
# Set the parameters for MemoryInit
############################################################
- register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB
-
- register "PcdMrcInitMmioSize" = "0x0800"
register "PcdMrcInitSpdAddr1" = "0xa0"
register "PcdMrcInitSpdAddr2" = "0xa2"
register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_64MB"
- register "PcdApertureSize" = "2"
- register "PcdGttSize" = "1"
register "PcdDvfsEnable" = "0"
register "PcdCaMirrorEn" = "1"
@@ -37,9 +32,6 @@ chip soc/intel/braswell
register "PunitPwrConfigDisable" = "0" # Enable SVID
register "ChvSvidConfig" = "1"
register "PcdEmmcMode" = "PCH_PCI_MODE"
- register "PcdUsb3ClkSsc" = "1"
- register "PcdDispClkSsc" = "1"
- register "PcdSataClkSsc" = "1"
register "PcdEnableSata" = "0" # Disable SATA
register "Usb2Port0PerPortPeTxiSet" = "7"
register "Usb2Port0PerPortTxiSet" = "5"
@@ -65,9 +57,7 @@ chip soc/intel/braswell
register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"
register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"
register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"
- register "PcdSataInterfaceSpeed" = "3"
register "PcdPchSsicEnable" = "1"
- register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM
register "PMIC_I2CBus" = "0"
register "ISPEnable" = "0" # Disable IUNIT
register "ISPPciDevConfig" = "3"
diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb
index 91e9795f9b..cec1682ed1 100644
--- a/src/mainboard/google/cyan/devicetree.cb
+++ b/src/mainboard/google/cyan/devicetree.cb
@@ -7,14 +7,9 @@ chip soc/intel/braswell
# Set the parameters for MemoryInit
############################################################
- register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB
-
- register "PcdMrcInitMmioSize" = "0x0800"
register "PcdMrcInitSpdAddr1" = "0xa0"
register "PcdMrcInitSpdAddr2" = "0xa2"
register "PcdIgdDvmt50PreAlloc" = "1"
- register "PcdApertureSize" = "2"
- register "PcdGttSize" = "1"
register "PcdDvfsEnable" = "1"
register "PcdCaMirrorEn" = "1"
@@ -40,9 +35,6 @@ chip soc/intel/braswell
register "PunitPwrConfigDisable" = "0" # Enable SVID
register "ChvSvidConfig" = "SVID_PMIC_CONFIG"
register "PcdEmmcMode" = "PCH_PCI_MODE"
- register "PcdUsb3ClkSsc" = "1"
- register "PcdDispClkSsc" = "1"
- register "PcdSataClkSsc" = "1"
register "PcdEnableSata" = "0" # Disable SATA
register "Usb2Port0PerPortPeTxiSet" = "7"
register "Usb2Port0PerPortTxiSet" = "5"
@@ -68,9 +60,7 @@ chip soc/intel/braswell
register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"
register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"
register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"
- register "PcdSataInterfaceSpeed" = "3"
register "PcdPchSsicEnable" = "1"
- register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM
register "PMIC_I2CBus" = "1"
register "ISPEnable" = "0" # Disable IUNIT
register "ISPPciDevConfig" = "3"
diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb
index 91337878c2..77b07d2e38 100644
--- a/src/mainboard/intel/strago/devicetree.cb
+++ b/src/mainboard/intel/strago/devicetree.cb
@@ -4,14 +4,9 @@ chip soc/intel/braswell
# Set the parameters for MemoryInit
############################################################
- register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB
-
- register "PcdMrcInitMmioSize" = "0x0800"
register "PcdMrcInitSpdAddr1" = "0xa0"
register "PcdMrcInitSpdAddr2" = "0xa2"
register "PcdIgdDvmt50PreAlloc" = "1"
- register "PcdApertureSize" = "2"
- register "PcdGttSize" = "1"
register "PcdDvfsEnable" = "0"
register "PcdCaMirrorEn" = "1"
@@ -37,9 +32,6 @@ chip soc/intel/braswell
register "PunitPwrConfigDisable" = "0" # Enable SVID
register "ChvSvidConfig" = "SVID_PMIC_CONFIG"
register "PcdEmmcMode" = "PCH_ACPI_MODE"
- register "PcdUsb3ClkSsc" = "1"
- register "PcdDispClkSsc" = "1"
- register "PcdSataClkSsc" = "1"
register "PcdEnableSata" = "0" # Disable SATA
register "Usb2Port0PerPortPeTxiSet" = "7"
register "Usb2Port0PerPortTxiSet" = "5"
@@ -65,9 +57,7 @@ chip soc/intel/braswell
register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"
register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"
register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"
- register "PcdSataInterfaceSpeed" = "3"
register "PcdPchSsicEnable" = "1"
- register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM
register "PMIC_I2CBus" = "0"
register "ISPEnable" = "0" # Disable IUNIT
register "ISPPciDevConfig" = "3"
diff --git a/src/mainboard/portwell/m107/devicetree.cb b/src/mainboard/portwell/m107/devicetree.cb
index f68b071a12..d77967264f 100644
--- a/src/mainboard/portwell/m107/devicetree.cb
+++ b/src/mainboard/portwell/m107/devicetree.cb
@@ -4,14 +4,9 @@ chip soc/intel/braswell
# Set the parameters for MemoryInit
############################################################
- register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB
-
- register "PcdMrcInitMmioSize" = "0x0800"
register "PcdMrcInitSpdAddr1" = "0xa0"
register "PcdMrcInitSpdAddr2" = "0xa2"
register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_32MB"
- register "PcdApertureSize" = "2"
- register "PcdGttSize" = "1"
register "PcdDvfsEnable" = "0"
register "PcdCaMirrorEn" = "1"
@@ -37,9 +32,6 @@ chip soc/intel/braswell
register "PunitPwrConfigDisable" = "0" # Enable SVID
register "ChvSvidConfig" = "1"
register "PcdEmmcMode" = "PCH_PCI_MODE"
- register "PcdUsb3ClkSsc" = "1"
- register "PcdDispClkSsc" = "1"
- register "PcdSataClkSsc" = "1"
register "PcdEnableSata" = "1"
register "Usb2Port0PerPortPeTxiSet" = "7"
register "Usb2Port0PerPortTxiSet" = "5"
@@ -65,9 +57,7 @@ chip soc/intel/braswell
register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"
register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"
register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"
- register "PcdSataInterfaceSpeed" = "3"
register "PcdPchSsicEnable" = "1"
- register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM
register "PMIC_I2CBus" = "0"
register "ISPEnable" = "0" # Disable IUNIT
register "ISPPciDevConfig" = "3"
diff --git a/src/mainboard/protectli/vault_bsw/devicetree.cb b/src/mainboard/protectli/vault_bsw/devicetree.cb
index 94c083d13a..4b750c00f0 100644
--- a/src/mainboard/protectli/vault_bsw/devicetree.cb
+++ b/src/mainboard/protectli/vault_bsw/devicetree.cb
@@ -4,14 +4,9 @@ chip soc/intel/braswell
# Set the parameters for MemoryInit
############################################################
- register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB
-
- register "PcdMrcInitMmioSize" = "0x0800"
register "PcdMrcInitSpdAddr1" = "0xa0"
register "PcdMrcInitSpdAddr2" = "0xa2"
register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_32MB"
- register "PcdApertureSize" = "2"
- register "PcdGttSize" = "1"
register "PcdDvfsEnable" = "0"
register "PcdCaMirrorEn" = "1"
@@ -37,9 +32,6 @@ chip soc/intel/braswell
register "PunitPwrConfigDisable" = "1" # Disable SVID
register "ChvSvidConfig" = "SVID_PMIC_CONFIG"
register "PcdEmmcMode" = "PCH_DISABLED"
- register "PcdUsb3ClkSsc" = "1"
- register "PcdDispClkSsc" = "1"
- register "PcdSataClkSsc" = "1"
register "PcdEnableSata" = "1"
register "Usb2Port0PerPortPeTxiSet" = "7"
register "Usb2Port0PerPortTxiSet" = "6"
@@ -65,9 +57,7 @@ chip soc/intel/braswell
register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"
register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"
register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"
- register "PcdSataInterfaceSpeed" = "3"
register "PcdPchSsicEnable" = "1"
- register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM
register "PMIC_I2CBus" = "0"
register "ISPEnable" = "0" # Disable IUNIT
register "ISPPciDevConfig" = "3"
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 05:15:03 +0000