diff options
Diffstat (limited to 'src/mainboard')
39 files changed, 219 insertions, 211 deletions
diff --git a/src/mainboard/google/brya/variants/agah/overridetree.cb b/src/mainboard/google/brya/variants/agah/overridetree.cb index 2f79831fe6..97fa9905e4 100644 --- a/src/mainboard/google/brya/variants/agah/overridetree.cb +++ b/src/mainboard/google/brya/variants/agah/overridetree.cb @@ -30,8 +30,8 @@ chip soc/intel/alderlake }, }" - register "SaGv" = "SaGv_Enabled" - register "TcssAuxOri" = "1" + register "sagv" = "SaGv_Enabled" + register "tcss_aux_ori" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1 @@ -43,7 +43,7 @@ chip soc/intel/alderlake register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A2 register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable M.2 WWAN - register "SerialIoI2cMode" = "{ + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, @@ -52,7 +52,7 @@ chip soc/intel/alderlake [PchSerialIoIndexI2C5] = PchSerialIoPci, }" - register "SerialIoGSpiMode" = "{ + register "serial_io_gspi_mode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, }" diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb index 9934dee8e3..67b9f95b14 100644 --- a/src/mainboard/google/brya/variants/anahera/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb @@ -22,13 +22,13 @@ fw_config end end chip soc/intel/alderlake - register "SaGv" = "SaGv_Enabled" + register "sagv" = "SaGv_Enabled" # Acoustic settings - register "AcousticNoiseMitigation" = "1" - register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" - register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" - register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb index 0d36ddf6c8..20defe7505 100644 --- a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb @@ -22,13 +22,13 @@ fw_config end end chip soc/intel/alderlake - register "SaGv" = "SaGv_Enabled" + register "sagv" = "SaGv_Enabled" # Acoustic settings - register "AcousticNoiseMitigation" = "1" - register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" - register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" - register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/brya/variants/banshee/overridetree.cb b/src/mainboard/google/brya/variants/banshee/overridetree.cb index 08550d2542..8729b3a599 100644 --- a/src/mainboard/google/brya/variants/banshee/overridetree.cb +++ b/src/mainboard/google/brya/variants/banshee/overridetree.cb @@ -36,7 +36,7 @@ chip soc/intel/alderlake register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC3)" # I2C Port Config - register "SerialIoI2cMode" = "{ + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoDisabled, @@ -45,7 +45,7 @@ chip soc/intel/alderlake [PchSerialIoIndexI2C5] = PchSerialIoPci, }" - register "SerialIoGSpiMode" = "{ + register "serial_io_gspi_mode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, }" diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index 9eb8bb2adb..a57289b46a 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -20,7 +20,7 @@ chip soc/intel/alderlake register "tcc_offset" = "10" # TCC of 90 # Enable CNVi BT - register "CnviBtCore" = "true" + register "cnvi_bt_core" = "true" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C1 @@ -41,7 +41,7 @@ chip soc/intel/alderlake register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)" register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC2)" - register "SerialIoI2cMode" = "{ + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoDisabled, @@ -50,12 +50,12 @@ chip soc/intel/alderlake [PchSerialIoIndexI2C5] = PchSerialIoDisabled, }" - register "SerialIoGSpiMode" = "{ + register "serial_io_gspi_mode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, [PchSerialIoIndexGSPI1] = PchSerialIoPci, }" - register "SerialIoUartMode" = "{ + register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoPci, [PchSerialIoIndexUART1] = PchSerialIoDisabled, [PchSerialIoIndexUART2] = PchSerialIoDisabled, @@ -68,13 +68,13 @@ chip soc/intel/alderlake register "pch_reset_power_cycle_duration" = "POWER_CYCLE_DURATION_1S" # HD Audio - register "PchHdaDspEnable" = "1" - register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T" - register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ" - register "PchHdaIDispCodecEnable" = "1" + register "pch_hda_dsp_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" - # FIVR RFI Spread Spectrum 1.5% - register "FivrSpreadSpectrum" = "FIVR_SS_1_5" + # FIVR RFI Spread Spectrum 1.5% + register "fivr_spread_spectrum" = "FIVR_SS_1_5" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/brya/variants/baseboard/brask/ramstage.c b/src/mainboard/google/brya/variants/baseboard/brask/ramstage.c index 9628b447b0..4d30b8e237 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/ramstage.c +++ b/src/mainboard/google/brya/variants/baseboard/brask/ramstage.c @@ -146,7 +146,7 @@ void variant_update_psys_power_limits(const struct cpu_power_limits *limits, /* voltage unit is milliVolts and current is in milliAmps */ soc_config->psys_pmax = (u16)(((u32)config_psys->psys_imax_ma * volts_mv) / 1000000); - conf->PsysPmax = soc_config->psys_pmax; + conf->platform_pmax = soc_config->psys_pmax; soc_config->tdp_pl2_override = pl2; soc_config->tdp_psyspl2 = psyspl2; diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index d67fd4b7a2..9ceda11873 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -20,7 +20,7 @@ chip soc/intel/alderlake register "tcc_offset" = "10" # TCC of 90 # Enable CNVi BT - register "CnviBtCore" = "true" + register "cnvi_bt_core" = "true" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C1 @@ -37,7 +37,7 @@ chip soc/intel/alderlake register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)" register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC2)" - register "SerialIoI2cMode" = "{ + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, @@ -46,12 +46,12 @@ chip soc/intel/alderlake [PchSerialIoIndexI2C5] = PchSerialIoPci, }" - register "SerialIoGSpiMode" = "{ + register "serial_io_gspi_mode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, [PchSerialIoIndexGSPI1] = PchSerialIoPci, }" - register "SerialIoUartMode" = "{ + register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoPci, [PchSerialIoIndexUART1] = PchSerialIoDisabled, [PchSerialIoIndexUART2] = PchSerialIoDisabled, @@ -64,13 +64,13 @@ chip soc/intel/alderlake register "pch_reset_power_cycle_duration" = "POWER_CYCLE_DURATION_1S" # HD Audio - register "PchHdaDspEnable" = "1" - register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T" - register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ" - register "PchHdaIDispCodecEnable" = "1" + register "pch_hda_dsp_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" # FIVR RFI Spread Spectrum 1.5% - register "FivrSpreadSpectrum" = "FIVR_SS_1_5" + register "fivr_spread_spectrum" = "FIVR_SS_1_5" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index d85e230e5d..c4c4fb3c58 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -15,7 +15,7 @@ chip soc/intel/alderlake register "s0ix_enable" = "1" # Enable CNVi BT - register "CnviBtCore" = "true" + register "cnvi_bt_core" = "true" # eMMC HS400 register "emmc_enable_hs400_mode" = "1" @@ -32,7 +32,7 @@ chip soc/intel/alderlake register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" - register "SerialIoI2cMode" = "{ + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, @@ -41,22 +41,22 @@ chip soc/intel/alderlake [PchSerialIoIndexI2C5] = PchSerialIoPci, }" - register "SerialIoGSpiMode" = "{ + register "serial_io_gspi_mode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, }" - register "SerialIoUartMode" = "{ + register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoPci, [PchSerialIoIndexUART1] = PchSerialIoDisabled, [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" # HD Audio - register "PchHdaDspEnable" = "1" - register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T" - register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ" - register "PchHdaIDispCodecEnable" = "1" + register "pch_hda_dsp_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/brya/variants/brask/variant.c b/src/mainboard/google/brya/variants/brask/variant.c index 8e3578c84b..04105db2ea 100644 --- a/src/mainboard/google/brya/variants/brask/variant.c +++ b/src/mainboard/google/brya/variants/brask/variant.c @@ -6,5 +6,6 @@ void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { - config->CnviBtAudioOffload = fw_config_probe(FW_CONFIG(AUDIO, NAU88L25B_I2S)); + config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO, + NAU88L25B_I2S)); } diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index f621b127aa..63ffe2f4cb 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -35,9 +35,9 @@ fw_config end chip soc/intel/alderlake - register "SaGv" = "SaGv_Enabled" + register "sagv" = "SaGv_Enabled" - register "PsysPmax" = "145" + register "platform_pmax" = "145" register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port diff --git a/src/mainboard/google/brya/variants/brya0/variant.c b/src/mainboard/google/brya/variants/brya0/variant.c index 8d4471ba2e..e9ae51ea0f 100644 --- a/src/mainboard/google/brya/variants/brya0/variant.c +++ b/src/mainboard/google/brya/variants/brya0/variant.c @@ -6,5 +6,6 @@ void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { - config->CnviBtAudioOffload = fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682_SNDW)); + config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO, + MAX98373_ALC5682_SNDW)); } diff --git a/src/mainboard/google/brya/variants/brya4es/overridetree.cb b/src/mainboard/google/brya/variants/brya4es/overridetree.cb index e6a2d7e54c..6a12c704d8 100644 --- a/src/mainboard/google/brya/variants/brya4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya4es/overridetree.cb @@ -35,9 +35,9 @@ fw_config end chip soc/intel/alderlake - register "SaGv" = "SaGv_Enabled" + register "sagv" = "SaGv_Enabled" - register "PsysPmax" = "145" + register "platform_pmax" = "145" register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port diff --git a/src/mainboard/google/brya/variants/brya4es/variant.c b/src/mainboard/google/brya/variants/brya4es/variant.c index 8d4471ba2e..e9ae51ea0f 100644 --- a/src/mainboard/google/brya/variants/brya4es/variant.c +++ b/src/mainboard/google/brya/variants/brya4es/variant.c @@ -6,5 +6,6 @@ void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { - config->CnviBtAudioOffload = fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682_SNDW)); + config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO, + MAX98373_ALC5682_SNDW)); } diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index acd96dd6b4..a89ad95243 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -16,7 +16,7 @@ fw_config end chip soc/intel/alderlake - register "SaGv" = "SaGv_Enabled" + register "sagv" = "SaGv_Enabled" # FIVR configurations for brya are disabled since the board doesn't have V1p05 and Vnn # bypass rails implemented. @@ -30,7 +30,7 @@ chip soc/intel/alderlake register "tcss_ports[0]" = "TCSS_PORT_EMPTY" - register "SerialIoI2cMode" = "{ + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoDisabled, @@ -39,7 +39,7 @@ chip soc/intel/alderlake [PchSerialIoIndexI2C5] = PchSerialIoPci, }" - register "SerialIoGSpiMode" = "{ + register "serial_io_gspi_mode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, }" diff --git a/src/mainboard/google/brya/variants/felwinter/variant.c b/src/mainboard/google/brya/variants/felwinter/variant.c index 8b270de04e..b0bf99ac56 100644 --- a/src/mainboard/google/brya/variants/felwinter/variant.c +++ b/src/mainboard/google/brya/variants/felwinter/variant.c @@ -15,6 +15,6 @@ void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) if (fw_config_probe(FW_CONFIG(DB_USB, USB3_PS8815))) { config->typec_aux_bias_pads[2].pad_auxp_dc = GPP_A19; config->typec_aux_bias_pads[2].pad_auxn_dc = GPP_A20; - config->TcssAuxOri = 0x10; + config->tcss_aux_ori = 0x10; } } diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index 0d8b49b47e..07458e9a8d 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -21,15 +21,15 @@ fw_config end end chip soc/intel/alderlake - register "SaGv" = "SaGv_Enabled" - register "PsysPmax" = "143" - register "TcssAuxOri" = "1" + register "sagv" = "SaGv_Enabled" + register "platform_pmax" = "143" + register "tcss_aux_ori" = "1" # Acoustic settings - register "AcousticNoiseMitigation" = "1" - register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" - register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" - register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "usb2_ports[1]" = "USB2_PORT_MAX_TYPE_C(OC1)" # set MAX to USB2_C1 for eye diagram diff --git a/src/mainboard/google/brya/variants/gimble/variant.c b/src/mainboard/google/brya/variants/gimble/variant.c index 96ccf88ae7..48a3f21909 100644 --- a/src/mainboard/google/brya/variants/gimble/variant.c +++ b/src/mainboard/google/brya/variants/gimble/variant.c @@ -12,6 +12,6 @@ const char *get_wifi_sar_cbfs_filename(void) void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { - config->CnviBtAudioOffload = fw_config_probe(FW_CONFIG(AUDIO, + config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO, MAX98390_ALC5682I_I2S_SSP1)); } diff --git a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb index 1ab9a7e6be..3df3e024a7 100644 --- a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb @@ -21,15 +21,15 @@ fw_config end end chip soc/intel/alderlake - register "SaGv" = "SaGv_Enabled" - register "PsysPmax" = "143" - register "TcssAuxOri" = "1" + register "sagv" = "SaGv_Enabled" + register "platform_pmax" = "143" + register "tcss_aux_ori" = "1" # Acoustic settings - register "AcousticNoiseMitigation" = "1" - register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" - register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" - register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "usb2_ports[1]" = "USB2_PORT_MAX_TYPE_C(OC1)" # set MAX to USB2_C1 for eye diagram diff --git a/src/mainboard/google/brya/variants/gimble4es/variant.c b/src/mainboard/google/brya/variants/gimble4es/variant.c index 96ccf88ae7..48a3f21909 100644 --- a/src/mainboard/google/brya/variants/gimble4es/variant.c +++ b/src/mainboard/google/brya/variants/gimble4es/variant.c @@ -12,6 +12,6 @@ const char *get_wifi_sar_cbfs_filename(void) void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { - config->CnviBtAudioOffload = fw_config_probe(FW_CONFIG(AUDIO, + config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO, MAX98390_ALC5682I_I2S_SSP1)); } diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index 39cca42b4f..41c3cf2c8b 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -17,7 +17,7 @@ fw_config end end chip soc/intel/alderlake - register "SaGv" = "SaGv_Enabled" + register "sagv" = "SaGv_Enabled" # GPE configuration register "pmc_gpe0_dw1" = "GPP_D" diff --git a/src/mainboard/google/brya/variants/kano/variant.c b/src/mainboard/google/brya/variants/kano/variant.c index 0db43aa06d..86c65c7ea7 100644 --- a/src/mainboard/google/brya/variants/kano/variant.c +++ b/src/mainboard/google/brya/variants/kano/variant.c @@ -12,5 +12,6 @@ const char *get_wifi_sar_cbfs_filename(void) void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { - config->CnviBtAudioOffload = fw_config_probe(FW_CONFIG(AUDIO, MAX98373_NAU88L25B_I2S)); + config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO, + MAX98373_NAU88L25B_I2S)); } diff --git a/src/mainboard/google/brya/variants/kinox/overridetree.cb b/src/mainboard/google/brya/variants/kinox/overridetree.cb index f850d11fe9..4168c4f7ef 100644 --- a/src/mainboard/google/brya/variants/kinox/overridetree.cb +++ b/src/mainboard/google/brya/variants/kinox/overridetree.cb @@ -31,7 +31,7 @@ chip soc/intel/alderlake register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable Port2 # I2C Port Config - register "SerialIoI2cMode" = "{ + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoDisabled, @@ -40,7 +40,7 @@ chip soc/intel/alderlake [PchSerialIoIndexI2C5] = PchSerialIoDisabled, }" - register "SerialIoGSpiMode" = "{ + register "serial_io_gspi_mode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, }" diff --git a/src/mainboard/google/brya/variants/nereid/overridetree.cb b/src/mainboard/google/brya/variants/nereid/overridetree.cb index 9cb27e88d7..50c98ceed7 100644 --- a/src/mainboard/google/brya/variants/nereid/overridetree.cb +++ b/src/mainboard/google/brya/variants/nereid/overridetree.cb @@ -7,7 +7,7 @@ fw_config end chip soc/intel/alderlake - register "SaGv" = "SaGv_Enabled" + register "sagv" = "SaGv_Enabled" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" diff --git a/src/mainboard/google/brya/variants/nivviks/overridetree.cb b/src/mainboard/google/brya/variants/nivviks/overridetree.cb index d5d062103c..c2eac2d97a 100644 --- a/src/mainboard/google/brya/variants/nivviks/overridetree.cb +++ b/src/mainboard/google/brya/variants/nivviks/overridetree.cb @@ -7,7 +7,7 @@ fw_config end chip soc/intel/alderlake - register "SaGv" = "SaGv_Enabled" + register "sagv" = "SaGv_Enabled" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index 6b88822248..88323813f8 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -23,14 +23,15 @@ fw_config end chip soc/intel/alderlake - register "SaGv" = "SaGv_Enabled" - register "MaxDramSpeed" = "3733" + register "sagv" = "SaGv_Enabled" + register "max_dram_speed" = "3733" + # Acoustic settings - register "AcousticNoiseMitigation" = "1" - register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" - register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" - register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/brya/variants/primus4es/overridetree.cb b/src/mainboard/google/brya/variants/primus4es/overridetree.cb index d6400c2462..940c63f005 100644 --- a/src/mainboard/google/brya/variants/primus4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus4es/overridetree.cb @@ -23,14 +23,15 @@ fw_config end chip soc/intel/alderlake - register "SaGv" = "SaGv_Enabled" - register "MaxDramSpeed" = "3733" + register "sagv" = "SaGv_Enabled" + register "max_dram_speed" = "3733" + # Acoustic settings - register "AcousticNoiseMitigation" = "1" - register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" - register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" - register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index 3f9c81d4dd..a44cb40521 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -31,17 +31,17 @@ fw_config end end chip soc/intel/alderlake - register "SaGv" = "SaGv_Enabled" - register "CnviBtAudioOffload" = "true" + register "sagv" = "SaGv_Enabled" + register "cnvi_bt_audio_offload" = "true" # FIVR RFI Spread Spectrum 6% - register "FivrSpreadSpectrum" = "FIVR_SS_6" + register "fivr_spread_spectrum" = "FIVR_SS_6" # Acoustic settings - register "AcousticNoiseMitigation" = "1" - register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" - register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" - register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" register "usb2_ports[1]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "USB2_PORT_EMPTY" diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb index 0c9c174fa3..9c51512c57 100644 --- a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb @@ -31,17 +31,17 @@ fw_config end end chip soc/intel/alderlake - register "SaGv" = "SaGv_Enabled" - register "CnviBtAudioOffload" = "true" + register "sagv" = "SaGv_Enabled" + register "cnvi_bt_audio_offload" = "true" # FIVR RFI Spread Spectrum 6% - register "FivrSpreadSpectrum" = "FIVR_SS_6" + register "fivr_spread_spectrum" = "FIVR_SS_6" # Acoustic settings - register "AcousticNoiseMitigation" = "1" - register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" - register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" - register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" register "usb2_ports[1]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "USB2_PORT_EMPTY" diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index ac83e583af..75672ae362 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -41,11 +41,11 @@ fw_config end chip soc/intel/alderlake # Acoustic settings - register "AcousticNoiseMitigation" = "1" - register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" - register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" - register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" register "ext_fivr_settings" = "{ .configure_ext_fivr = 1, .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, @@ -59,9 +59,9 @@ chip soc/intel/alderlake .v1p05_icc_max_ma = 500, .vnn_sx_voltage_mv = 1250, }" - register "TcssAuxOri" = "1" + register "tcss_aux_ori" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" - register "SaGv" = "SaGv_Enabled" + register "sagv" = "SaGv_Enabled" register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable Port 1 register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # DB USB2_C1 @@ -115,7 +115,7 @@ chip soc/intel/alderlake }, }" # I2C Port Config - register "SerialIoI2cMode" = "{ + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, diff --git a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb index 11d572f96f..0de40448c5 100644 --- a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb @@ -40,11 +40,12 @@ fw_config end chip soc/intel/alderlake # Acoustic settings - register "AcousticNoiseMitigation" = "1" - register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" - register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" - register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" + register "ext_fivr_settings" = "{ .configure_ext_fivr = 1, .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, @@ -58,9 +59,10 @@ chip soc/intel/alderlake .v1p05_icc_max_ma = 500, .vnn_sx_voltage_mv = 1250, }" - register "TcssAuxOri" = "1" + + register "tcss_aux_ori" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" - register "SaGv" = "SaGv_Enabled" + register "sagv" = "SaGv_Enabled" register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable Port 1 register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # DB USB2_C1 @@ -107,7 +109,7 @@ chip soc/intel/alderlake }, }" # I2C Port Config - register "SerialIoI2cMode" = "{ + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, diff --git a/src/mainboard/google/brya/variants/taniks/overridetree.cb b/src/mainboard/google/brya/variants/taniks/overridetree.cb index f80f5d67fc..ddafa15dff 100644 --- a/src/mainboard/google/brya/variants/taniks/overridetree.cb +++ b/src/mainboard/google/brya/variants/taniks/overridetree.cb @@ -49,11 +49,11 @@ chip soc/intel/alderlake .v1p05_icc_max_ma = 500, .vnn_sx_voltage_mv = 1250, }" - register "TcssAuxOri" = "1" + register "tcss_aux_ori" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" - register "SaGv" = "SaGv_Enabled" + register "sagv" = "SaGv_Enabled" - register "PsysPmax" = "145" + register "platform_pmax" = "145" register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable Port 1 register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # DB USB2_C1 @@ -94,7 +94,7 @@ chip soc/intel/alderlake }, }" # I2C Port Config - register "SerialIoI2cMode" = "{ + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoDisabled, diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index 5f2780e161..4199cec6a6 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -51,10 +51,10 @@ chip soc/intel/alderlake }" register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC3)" # USB2_C3 register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" - register "SaGv" = "SaGv_Enabled" + register "sagv" = "SaGv_Enabled" # I2C Port Config - register "SerialIoI2cMode" = "{ + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, diff --git a/src/mainboard/google/brya/variants/volmar/overridetree.cb b/src/mainboard/google/brya/variants/volmar/overridetree.cb index f54753b7af..d8bcdbdc72 100644 --- a/src/mainboard/google/brya/variants/volmar/overridetree.cb +++ b/src/mainboard/google/brya/variants/volmar/overridetree.cb @@ -21,9 +21,9 @@ fw_config end end chip soc/intel/alderlake - register "SaGv" = "SaGv_Enabled" + register "sagv" = "SaGv_Enabled" - register "TcssAuxOri" = "1" + register "tcss_aux_ori" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1 diff --git a/src/mainboard/google/brya/variants/volmar/variant.c b/src/mainboard/google/brya/variants/volmar/variant.c index fef03f2b3e..e21ab5a91c 100644 --- a/src/mainboard/google/brya/variants/volmar/variant.c +++ b/src/mainboard/google/brya/variants/volmar/variant.c @@ -6,5 +6,6 @@ void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { - config->CnviBtAudioOffload = fw_config_probe(FW_CONFIG(AUDIO, MAX98373_NAU88L25B_I2S)); + config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO, + MAX98373_NAU88L25B_I2S)); } diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 9bd99b18f7..a4f85947a9 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -11,10 +11,10 @@ chip soc/intel/alderlake # FSP configuration # Enable CNVi BT - register "CnviBtCore" = "true" + register "cnvi_bt_core" = "true" # Sagv Configuration - register "SaGv" = "SaGv_Enabled" + register "sagv" = "SaGv_Enabled" register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port2 @@ -72,7 +72,7 @@ chip soc/intel/alderlake }" # Hybrid storage mode - register "HybridStorageMode" = "1" + register "hybrid_storage_mode" = "1" # Enable CPU PCIE RP 1 using CLK 0 register "cpu_pcie_rp[CPU_RP(1)]" = "{ @@ -95,16 +95,16 @@ chip soc/intel/alderlake .flags = PCIE_RP_LTR | PCIE_RP_AER, }" - register "SataSalpSupport" = "1" + register "sata_salp_support" = "1" - register "SataPortsEnable" = "{ + register "sata_ports_enable" = "{ [0] = 1, [1] = 1, [2] = 1, [3] = 1, }" - register "SataPortsDevSlp" = "{ + register "sata_ports_dev_slp" = "{ [0] = 1, [1] = 1, [2] = 1, @@ -112,19 +112,19 @@ chip soc/intel/alderlake }" # Enable EDP in PortA - register "DdiPortAConfig" = "1" + register "ddi_portA_config" = "1" # Enable HDMI in Port B register "ddi_ports_config" = "{ [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, }" # TCSS USB3 - register "TcssAuxOri" = "0" + register "tcss_aux_ori" = "0" register "s0ix_enable" = "1" register "dptf_enable" = "1" - register "SerialIoI2cMode" = "{ + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, @@ -133,40 +133,40 @@ chip soc/intel/alderlake [PchSerialIoIndexI2C5] = PchSerialIoPci, }" - register "SerialIoGSpiMode" = "{ + register "serial_io_gspi_mode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoPci, [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, }" - register "SerialIoGSpiCsMode" = "{ + register "serial_io_gspi_cs_mode" = "{ [PchSerialIoIndexGSPI0] = 0, [PchSerialIoIndexGSPI1] = 0, [PchSerialIoIndexGSPI2] = 0, [PchSerialIoIndexGSPI3] = 0, }" - register "SerialIoGSpiCsState" = "{ + register "serial_io_gspi_cs_state" = "{ [PchSerialIoIndexGSPI0] = 0, [PchSerialIoIndexGSPI1] = 0, [PchSerialIoIndexGSPI2] = 0, [PchSerialIoIndexGSPI3] = 0, }" - register "SerialIoUartMode" = "{ + register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoSkipInit, [PchSerialIoIndexUART1] = PchSerialIoDisabled, [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" # HD Audio - register "PchHdaDspEnable" = "1" - register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T" - register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ" - register "PchHdaIDispCodecEnable" = "1" + register "pch_hda_dsp_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" - register "CnviBtAudioOffload" = "true" + register "cnvi_bt_audio_offload" = "true" # Intel Common SoC Config register "common_soc_config" = "{ diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index c637ec3d54..4a41df61f7 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -36,10 +36,10 @@ chip soc/intel/alderlake register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WLAN # Sagv Configuration - register "SaGv" = "SaGv_Enabled" + register "sagv" = "SaGv_Enabled" # Enable CNVi Bluetooth - register "CnviBtCore" = "true" + register "cnvi_bt_core" = "true" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" @@ -80,7 +80,7 @@ chip soc/intel/alderlake }" # Hybrid storage mode - register "HybridStorageMode" = "1" + register "hybrid_storage_mode" = "1" # Enable CPU PCIE RP 1 using CLK 0 register "cpu_pcie_rp[CPU_RP(1)]" = "{ @@ -90,18 +90,18 @@ chip soc/intel/alderlake }" # Enable EDP in PortA - register "DdiPortAConfig" = "1" + register "ddi_portA_config" = "1" # Enable HDMI in Port B register "ddi_ports_config" = "{ [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, }" # TCSS USB3 - register "TcssAuxOri" = "0" + register "tcss_aux_ori" = "0" register "s0ix_enable" = "1" - register "SerialIoI2cMode" = "{ + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoDisabled, @@ -110,38 +110,38 @@ chip soc/intel/alderlake [PchSerialIoIndexI2C5] = PchSerialIoPci, }" - register "SerialIoGSpiMode" = "{ + register "serial_io_gspi_mode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoPci, [PchSerialIoIndexGSPI1] = PchSerialIoPci, [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, }" - register "SerialIoGSpiCsMode" = "{ + register "serial_io_gspi_cs_mode" = "{ [PchSerialIoIndexGSPI0] = 0, [PchSerialIoIndexGSPI1] = 1, [PchSerialIoIndexGSPI2] = 0, [PchSerialIoIndexGSPI3] = 0, }" - register "SerialIoGSpiCsState" = "{ + register "serial_io_gspi_cs_state" = "{ [PchSerialIoIndexGSPI0] = 0, [PchSerialIoIndexGSPI1] = 0, [PchSerialIoIndexGSPI2] = 0, [PchSerialIoIndexGSPI3] = 0, }" - register "SerialIoUartMode" = "{ + register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoSkipInit, [PchSerialIoIndexUART1] = PchSerialIoDisabled, [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" # HD Audio - register "PchHdaDspEnable" = "1" - register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T" - register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ" - register "PchHdaIDispCodecEnable" = "1" + register "pch_hda_dsp_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" # Intel Common SoC Config register "common_soc_config" = "{ diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb index f7da2d16c8..d38c010704 100644 --- a/src/mainboard/intel/adlrvp/devicetree_n.cb +++ b/src/mainboard/intel/adlrvp/devicetree_n.cb @@ -11,10 +11,10 @@ chip soc/intel/alderlake # FSP configuration # Enable CNVi BT - register "CnviBtCore" = "true" + register "cnvi_bt_core" = "true" # Sagv Configuration - register "SaGv" = "SaGv_Enabled" + register "sagv" = "SaGv_Enabled" # eMMC HS400 register "emmc_enable_hs400_mode" = "1" @@ -54,16 +54,16 @@ chip soc/intel/alderlake .flags = PCIE_RP_CLK_REQ_DETECT, }" - register "SataSalpSupport" = "1" + register "sata_salp_support" = "1" - register "SataPortsEnable" = "{ + register "sata_ports_enable" = "{ [0] = 1, [1] = 1, [2] = 1, [3] = 1, }" - register "SataPortsDevSlp" = "{ + register "sata_ports_dev_slp" = "{ [0] = 1, [1] = 1, [2] = 1, @@ -71,19 +71,19 @@ chip soc/intel/alderlake }" # Enable EDP in PortA - register "DdiPortAConfig" = "1" + register "ddi_portA_config" = "1" # Enable HDMI in Port B register "ddi_ports_config" = "{ [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, }" # TCSS USB3 - register "TcssAuxOri" = "4" + register "tcss_aux_ori" = "4" register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_E20, .pad_auxn_dc = GPP_E21}" register "s0ix_enable" = "1" - register "SerialIoI2cMode" = "{ + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, @@ -92,40 +92,40 @@ chip soc/intel/alderlake [PchSerialIoIndexI2C5] = PchSerialIoPci, }" - register "SerialIoGSpiMode" = "{ + register "serial_io_gspi_mode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoPci, [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, }" - register "SerialIoGSpiCsMode" = "{ + register "serial_io_gspi_cs_mode" = "{ [PchSerialIoIndexGSPI0] = 0, [PchSerialIoIndexGSPI1] = 0, [PchSerialIoIndexGSPI2] = 0, [PchSerialIoIndexGSPI3] = 0, }" - register "SerialIoGSpiCsState" = "{ + register "serial_io_gspi_cs_state" = "{ [PchSerialIoIndexGSPI0] = 0, [PchSerialIoIndexGSPI1] = 0, [PchSerialIoIndexGSPI2] = 0, [PchSerialIoIndexGSPI3] = 0, }" - register "SerialIoUartMode" = "{ + register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoSkipInit, [PchSerialIoIndexUART1] = PchSerialIoDisabled, [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" # HD Audio - register "PchHdaDspEnable" = "1" - register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T" - register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ" - register "PchHdaIDispCodecEnable" = "1" + register "pch_hda_dsp_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" - register "CnviBtAudioOffload" = "true" + register "cnvi_bt_audio_offload" = "true" # Intel Common SoC Config register "common_soc_config" = "{ diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index 63d3da423b..e68afe24f3 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -13,14 +13,14 @@ chip soc/intel/alderlake register "pmc_gpe0_dw2" = "GPP_E" # TCSS - register "TcssAuxOri" = "1" + register "tcss_aux_ori" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_A5, .pad_auxn_dc = GPP_A6}" # Enable CNVi Bluetooth - register "CnviBtCore" = "true" + register "cnvi_bt_core" = "true" # FSP configuration - register "SaGv" = "SaGv_Enabled" + register "sagv" = "SaGv_Enabled" # S0ix enable register "s0ix_enable" = "1" @@ -65,16 +65,15 @@ chip soc/intel/alderlake }" # Enable SATA - register "SataEnable" = "1" - register "SataMode" = "0" - register "SataSalpSupport" = "1" - register "SataPortsEnable[0]" = "0" - register "SataPortsEnable[1]" = "1" - register "SataPortsDevSlp[0]" = "0" - register "SataPortsDevSlp[1]" = "1" - register "SataPortsEnableDitoConfig[1]" = "1" + register "sata_mode" = "0" + register "sata_salp_support" = "1" + register "sata_ports_enable[0]" = "0" + register "sata_ports_enable[1]" = "1" + register "sata_ports_dev_slp[0]" = "0" + register "sata_ports_dev_slp[1]" = "1" + register "sata_ports_enable_dito_config[1]" = "1" - register "SerialIoI2cMode" = "{ + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, @@ -83,36 +82,36 @@ chip soc/intel/alderlake [PchSerialIoIndexI2C5] = PchSerialIoPci, }" - register "SerialIoGSpiMode" = "{ + register "serial_io_gspi_mode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoPci, [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, }" - register "SerialIoGSpiCsMode" = "{ + register "serial_io_gspi_cs_mode" = "{ [PchSerialIoIndexGSPI0] = 1, }" - register "SerialIoGSpiCsState" = "{ + register "serial_io_gspi_cs_state" = "{ [PchSerialIoIndexGSPI0] = 1, }" - register "SerialIoUartMode" = "{ + register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoSkipInit, [PchSerialIoIndexUART1] = PchSerialIoDisabled, [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" # HD Audio - register "PchHdaDspEnable" = "1" - register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T" - register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ" - register "PchHdaIDispCodecEnable" = "1" + register "pch_hda_dsp_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" # DP port - register "DdiPortAConfig" = "1" # eDP - register "DdiPortBConfig" = "0" + register "ddi_portA_config" = "1" # eDP + register "ddi_portB_config" = "0" # Enable Display Port Configuration register "ddi_ports_config" = "{ diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb index 7b094e4fc0..8476c482eb 100644 --- a/src/mainboard/prodrive/atlas/devicetree.cb +++ b/src/mainboard/prodrive/atlas/devicetree.cb @@ -23,19 +23,19 @@ chip soc/intel/alderlake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" - register "SataSalpSupport" = "1" + register "sata_salp_support" = "1" - register "SataPortsEnable" = "{ + register "sata_ports_enable" = "{ [0] = 1, [1] = 1, }" - register "SataPortsDevSlp" = "{ + register "sata_ports_dev_slp" = "{ [0] = 1, [1] = 1, }" - register "SerialIoUartMode" = "{ + register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoSkipInit, [PchSerialIoIndexUART1] = PchSerialIoPci, [PchSerialIoIndexUART2] = PchSerialIoDisabled, |