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-rw-r--r--src/mainboard/advantech/pcm-5820/Options.lb2
-rw-r--r--src/mainboard/amd/db800/Options.lb2
-rw-r--r--src/mainboard/amd/db800/irq_tables.c39
-rw-r--r--src/mainboard/amd/norwich/Options.lb2
-rw-r--r--src/mainboard/amd/norwich/irq_tables.c39
-rw-r--r--src/mainboard/artecgroup/dbe61/Options.lb3
-rw-r--r--src/mainboard/artecgroup/dbe61/irq_tables.c41
-rw-r--r--src/mainboard/asi/mb_5blmp/Options.lb3
-rw-r--r--src/mainboard/axus/tc320/Options.lb2
-rw-r--r--src/mainboard/bcom/winnet100/Options.lb2
-rw-r--r--src/mainboard/digitallogic/msm800sev/Options.lb2
-rw-r--r--src/mainboard/digitallogic/msm800sev/irq_tables.c38
-rw-r--r--src/mainboard/eaglelion/5bcm/Options.lb2
-rw-r--r--src/mainboard/iei/juki-511p/Options.lb2
-rw-r--r--src/mainboard/iei/nova4899r/Options.lb2
-rw-r--r--src/mainboard/pcengines/alix1c/Options.lb3
-rw-r--r--src/mainboard/pcengines/alix1c/irq_tables.c43
17 files changed, 32 insertions, 195 deletions
diff --git a/src/mainboard/advantech/pcm-5820/Options.lb b/src/mainboard/advantech/pcm-5820/Options.lb
index b8199f1a54..9d579879b7 100644
--- a/src/mainboard/advantech/pcm-5820/Options.lb
+++ b/src/mainboard/advantech/pcm-5820/Options.lb
@@ -63,6 +63,7 @@ uses CONFIG_VIDEO_MB
uses CONFIG_SPLASH_GRAPHIC
uses CONFIG_GX1_VIDEO
uses CONFIG_GX1_VIDEOMODE
+uses PIRQ_ROUTE
## Enable VGA with a splash screen (only 640x480 to run on most monitors).
## We want to support up to 1024x768@16 so we need 2MiB video memory.
@@ -75,6 +76,7 @@ default CONFIG_VIDEO_MB = 2
default ROM_SIZE = 256 * 1024
default HAVE_PIRQ_TABLE = 1
default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb.
+default PIRQ_ROUTE = 1
default HAVE_FALLBACK_BOOT = 1
default HAVE_MP_TABLE = 0
default HAVE_HARD_RESET = 0
diff --git a/src/mainboard/amd/db800/Options.lb b/src/mainboard/amd/db800/Options.lb
index 6a0dc3f8c0..ef62ec3eec 100644
--- a/src/mainboard/amd/db800/Options.lb
+++ b/src/mainboard/amd/db800/Options.lb
@@ -48,6 +48,7 @@ uses CONFIG_VIDEO_MB
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
+uses PIRQ_ROUTE
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
@@ -84,6 +85,7 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=4
+default PIRQ_ROUTE=1
#object irq_tables.o
##
diff --git a/src/mainboard/amd/db800/irq_tables.c b/src/mainboard/amd/db800/irq_tables.c
index 9fcc5eb3b6..f9a6312fa8 100644
--- a/src/mainboard/amd/db800/irq_tables.c
+++ b/src/mainboard/amd/db800/irq_tables.c
@@ -65,42 +65,5 @@ const struct irq_routing_table intel_irq_routing_table = {
unsigned long write_pirq_routing_table(unsigned long addr)
{
- int i, j, k, num_entries;
- unsigned char pirq[4];
- uint16_t chipset_irq_map;
- uint32_t pciAddr, pirtable_end;
- struct irq_routing_table *pirq_tbl;
-
- pirtable_end = copy_pirq_routing_table(addr);
-
- /* Set up chipset IRQ steering. */
- pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
- chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
- printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
- chipset_irq_map);
- outl(pciAddr & ~3, 0xCF8);
- outl(chipset_irq_map, 0xCFC);
-
- pirq_tbl = (struct irq_routing_table *)(addr);
- num_entries = (pirq_tbl->size - 32) / 16;
-
- /* Set PCI IRQs. */
- for (i = 0; i < num_entries; i++) {
- printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
- pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
- for (j = 0; j < 4; j++) {
- printk_debug("INT: %c bitmap: %x ", 'A' + j,
- pirq_tbl->slots[i].irq[j].bitmap);
- for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++) ; /* Finds lsb in bitmap to IRQ#. */
- pirq[j] = k;
- printk_debug("PIRQ: %d\n", k);
- }
-
- /* Bus, device, slots IRQs for {A,B,C,D}. */
- pci_assign_irqs(pirq_tbl->slots[i].bus,
- pirq_tbl->slots[i].devfn >> 3, pirq);
- }
-
- /* Put the PIR table in memory and checksum. */
- return pirtable_end;
+ return copy_pirq_routing_table(addr);
}
diff --git a/src/mainboard/amd/norwich/Options.lb b/src/mainboard/amd/norwich/Options.lb
index 0d4b2239ff..29d89d6c17 100644
--- a/src/mainboard/amd/norwich/Options.lb
+++ b/src/mainboard/amd/norwich/Options.lb
@@ -48,6 +48,7 @@ uses CONFIG_VIDEO_MB
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
+uses PIRQ_ROUTE
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
@@ -84,6 +85,7 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=6
+default PIRQ_ROUTE=1
#object irq_tables.o
##
diff --git a/src/mainboard/amd/norwich/irq_tables.c b/src/mainboard/amd/norwich/irq_tables.c
index afea876ba1..5e408b7241 100644
--- a/src/mainboard/amd/norwich/irq_tables.c
+++ b/src/mainboard/amd/norwich/irq_tables.c
@@ -67,42 +67,5 @@ const struct irq_routing_table intel_irq_routing_table = {
unsigned long write_pirq_routing_table(unsigned long addr)
{
- int i, j, k, num_entries;
- unsigned char pirq[4];
- uint16_t chipset_irq_map;
- uint32_t pciAddr, pirtable_end;
- struct irq_routing_table *pirq_tbl;
-
- pirtable_end = copy_pirq_routing_table(addr);
-
- /* Set up chipset IRQ steering. */
- pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
- chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
- printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
- chipset_irq_map);
- outl(pciAddr & ~3, 0xCF8);
- outl(chipset_irq_map, 0xCFC);
-
- pirq_tbl = (struct irq_routing_table *)(addr);
- num_entries = (pirq_tbl->size - 32) / 16;
-
- /* Set PCI IRQs. */
- for (i = 0; i < num_entries; i++) {
- printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
- pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
- for (j = 0; j < 4; j++) {
- printk_debug("INT: %c bitmap: %x ", 'A' + j,
- pirq_tbl->slots[i].irq[j].bitmap);
- for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++) ; /* Finds lsb in bitmap to IRQ#. */
- pirq[j] = k;
- printk_debug("PIRQ: %d\n", k);
- }
-
- /* Bus, device, slots IRQs for {A,B,C,D}. */
- pci_assign_irqs(pirq_tbl->slots[i].bus,
- pirq_tbl->slots[i].devfn >> 3, pirq);
- }
-
- /* Put the PIR table in memory and checksum. */
- return pirtable_end;
+ return copy_pirq_routing_table(addr);
}
diff --git a/src/mainboard/artecgroup/dbe61/Options.lb b/src/mainboard/artecgroup/dbe61/Options.lb
index d95f0a9bf7..9a35425463 100644
--- a/src/mainboard/artecgroup/dbe61/Options.lb
+++ b/src/mainboard/artecgroup/dbe61/Options.lb
@@ -48,6 +48,7 @@ uses CONFIG_VIDEO_MB
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
+uses PIRQ_ROUTE
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
@@ -84,7 +85,7 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=3
-
+default PIRQ_ROUTE=1
#object irq_tables.o
##
diff --git a/src/mainboard/artecgroup/dbe61/irq_tables.c b/src/mainboard/artecgroup/dbe61/irq_tables.c
index 1c06e1d8c7..b42c4b514e 100644
--- a/src/mainboard/artecgroup/dbe61/irq_tables.c
+++ b/src/mainboard/artecgroup/dbe61/irq_tables.c
@@ -64,42 +64,5 @@ const struct irq_routing_table intel_irq_routing_table = {
unsigned long write_pirq_routing_table(unsigned long addr)
{
- int i, j, k, num_entries;
- unsigned char pirq[4];
- uint16_t chipset_irq_map;
- uint32_t pciAddr, pirtable_end;
- struct irq_routing_table *pirq_tbl;
-
- pirtable_end = copy_pirq_routing_table(addr);
-
- /* Set up chipset IRQ steering. */
- pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
- chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
- printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
- chipset_irq_map);
- outl(pciAddr & ~3, 0xCF8);
- outl(chipset_irq_map, 0xCFC);
-
- pirq_tbl = (struct irq_routing_table *)(addr);
- num_entries = (pirq_tbl->size - 32) / 16;
-
- /* Set PCI IRQs. */
- for (i = 0; i < num_entries; i++) {
- printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
- pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
- for (j = 0; j < 4; j++) {
- printk_debug("INT: %c bitmap: %x ", 'A' + j,
- pirq_tbl->slots[i].irq[j].bitmap);
- for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++) ; /* Finds lsb in bitmap to IRQ#. */
- pirq[j] = k;
- printk_debug("PIRQ: %d\n", k);
- }
-
- /* Bus, device, slots IRQs for {A,B,C,D}. */
- pci_assign_irqs(pirq_tbl->slots[i].bus,
- pirq_tbl->slots[i].devfn >> 3, pirq);
- }
-
- /* Put the PIR table in memory and checksum. */
- return pirtable_end;
-} \ No newline at end of file
+ return copy_pirq_routing_table(addr);
+}
diff --git a/src/mainboard/asi/mb_5blmp/Options.lb b/src/mainboard/asi/mb_5blmp/Options.lb
index c1bf6cd517..1cdd4f8695 100644
--- a/src/mainboard/asi/mb_5blmp/Options.lb
+++ b/src/mainboard/asi/mb_5blmp/Options.lb
@@ -42,7 +42,7 @@ uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
# uses CONFIG_CONSOLE_VGA
# uses CONFIG_PCI_ROM_RUN
uses CONFIG_VIDEO_MB
-
+uses PIRQ_ROUTE
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256 * 1024
@@ -71,6 +71,7 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=5 # TODO?
+default PIRQ_ROUTE=1
##
## Build code to export a CMOS option table
diff --git a/src/mainboard/axus/tc320/Options.lb b/src/mainboard/axus/tc320/Options.lb
index 36fde166bc..ed56fd923f 100644
--- a/src/mainboard/axus/tc320/Options.lb
+++ b/src/mainboard/axus/tc320/Options.lb
@@ -63,6 +63,7 @@ uses CONFIG_VIDEO_MB
uses CONFIG_SPLASH_GRAPHIC
uses CONFIG_GX1_VIDEO
uses CONFIG_GX1_VIDEOMODE
+uses PIRQ_ROUTE
## Enable VGA with a splash screen (only 640x480 to run on most monitors).
## We want to support up to 1024x768@16 so we need 2MiB video memory.
@@ -82,6 +83,7 @@ default CONFIG_UDELAY_TSC = 1
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
default HAVE_PIRQ_TABLE = 1
default IRQ_SLOT_COUNT = 2 # Soldered NIC, internal USB, no real slots
+default PIRQ_ROUTE = 1
default HAVE_OPTION_TABLE = 0
default ROM_IMAGE_SIZE = 64 * 1024
default FALLBACK_SIZE = 128 * 1024
diff --git a/src/mainboard/bcom/winnet100/Options.lb b/src/mainboard/bcom/winnet100/Options.lb
index 4e4e21fc25..c6346e22cb 100644
--- a/src/mainboard/bcom/winnet100/Options.lb
+++ b/src/mainboard/bcom/winnet100/Options.lb
@@ -63,6 +63,7 @@ uses CONFIG_VIDEO_MB
uses CONFIG_SPLASH_GRAPHIC
uses CONFIG_GX1_VIDEO
uses CONFIG_GX1_VIDEOMODE
+uses PIRQ_ROUTE
## Enable VGA with a splash screen (only 640x480 to run on most monitors).
## We want to support up to 1024x768@16 so we need 2MiB video memory.
@@ -82,6 +83,7 @@ default CONFIG_UDELAY_TSC = 1
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
default HAVE_PIRQ_TABLE = 1
default IRQ_SLOT_COUNT = 2 # Soldered NIC, internal USB, no real slots
+default PIRQ_ROUTE = 1
default HAVE_OPTION_TABLE = 0
default ROM_IMAGE_SIZE = 64 * 1024
default FALLBACK_SIZE = 128 * 1024
diff --git a/src/mainboard/digitallogic/msm800sev/Options.lb b/src/mainboard/digitallogic/msm800sev/Options.lb
index cdab41a892..559a524698 100644
--- a/src/mainboard/digitallogic/msm800sev/Options.lb
+++ b/src/mainboard/digitallogic/msm800sev/Options.lb
@@ -48,6 +48,7 @@ uses CONFIG_VIDEO_MB
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
+uses PIRQ_ROUTE
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
@@ -84,6 +85,7 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=6
+default PIRQ_ROUTE=1
#object irq_tables.o
##
diff --git a/src/mainboard/digitallogic/msm800sev/irq_tables.c b/src/mainboard/digitallogic/msm800sev/irq_tables.c
index 6b5fe810a7..724d163a0a 100644
--- a/src/mainboard/digitallogic/msm800sev/irq_tables.c
+++ b/src/mainboard/digitallogic/msm800sev/irq_tables.c
@@ -69,39 +69,7 @@ const struct irq_routing_table intel_irq_routing_table = {
}
};
-
-unsigned long write_pirq_routing_table(unsigned long addr){
- int i, j, k, num_entries;
- unsigned int pirq[4];
- uint16_t chipset_irq_map;
- uint32_t pciAddr, pirtable_end;
- struct irq_routing_table *pirq_tbl;
-
- pirtable_end = copy_pirq_routing_table(addr);
-
- /* Set up chipset IRQ steering */
- pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
- chipset_irq_map = (11 << 12 | 10 << 8 | 11 << 4 | 10);
- printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr, chipset_irq_map);
- outl(pciAddr & ~3, 0xCF8);
- outl(chipset_irq_map, 0xCFC);
-
- pirq_tbl = (struct irq_routing_table *)(addr);
- num_entries = (pirq_tbl->size - 32)/16;
-
- /* Set PCI IRQs */
- for (i=0; i < num_entries; i++){
- printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i, pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
- for (j = 0; j < 4; j++){
- printk_debug("INT: %c bitmap: %x ", 'A'+j, pirq_tbl->slots[i].irq[j].bitmap);
- for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++); /* finds lsb in bitmap to IRQ# */
- pirq[j] = k;
- printk_debug("PIRQ: %d\n", k);
- }
- pci_assign_irqs(pirq_tbl->slots[i].bus, pirq_tbl->slots[i].devfn, pirq); /* bus, device, slots IRQs for {A,B,C,D} */
- }
-
- /* put the PIR table in memory and checksum */
- return pirtable_end;
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr);
}
-
diff --git a/src/mainboard/eaglelion/5bcm/Options.lb b/src/mainboard/eaglelion/5bcm/Options.lb
index 280f582845..c10b7b9cc0 100644
--- a/src/mainboard/eaglelion/5bcm/Options.lb
+++ b/src/mainboard/eaglelion/5bcm/Options.lb
@@ -42,6 +42,7 @@ uses TTYS0_LCS
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses CONFIG_VIDEO_MB
+uses PIRQ_ROUTE
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
@@ -75,6 +76,7 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=2
+default PIRQ_ROUTE=1
#object irq_tables.o
##
diff --git a/src/mainboard/iei/juki-511p/Options.lb b/src/mainboard/iei/juki-511p/Options.lb
index cd5be9cad3..ea703f1b86 100644
--- a/src/mainboard/iei/juki-511p/Options.lb
+++ b/src/mainboard/iei/juki-511p/Options.lb
@@ -43,6 +43,7 @@ uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses CONFIG_VIDEO_MB
+uses PIRQ_ROUTE
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
@@ -72,6 +73,7 @@ default CONFIG_UDELAY_IO=1
##
default HAVE_PIRQ_TABLE=0
default IRQ_SLOT_COUNT=2
+default PIRQ_ROUTE=1
#object irq_tables.o
##
diff --git a/src/mainboard/iei/nova4899r/Options.lb b/src/mainboard/iei/nova4899r/Options.lb
index 778cf737fc..3f2b8e3747 100644
--- a/src/mainboard/iei/nova4899r/Options.lb
+++ b/src/mainboard/iei/nova4899r/Options.lb
@@ -45,6 +45,7 @@ uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
uses CONFIG_PRECOMPRESSED_PAYLOAD
uses CONFIG_VIDEO_MB
+uses PIRQ_ROUTE
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
@@ -82,6 +83,7 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=7
+default PIRQ_ROUTE=1
#object irq_tables.o
##
diff --git a/src/mainboard/pcengines/alix1c/Options.lb b/src/mainboard/pcengines/alix1c/Options.lb
index 3e5c0456cc..2888259e88 100644
--- a/src/mainboard/pcengines/alix1c/Options.lb
+++ b/src/mainboard/pcengines/alix1c/Options.lb
@@ -68,6 +68,7 @@ uses CONFIG_VIDEO_MB
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
+uses PIRQ_ROUTE
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 512*1024
@@ -104,7 +105,7 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=5
-
+default PIRQ_ROUTE=1
##
## Build code to export a CMOS option table
##
diff --git a/src/mainboard/pcengines/alix1c/irq_tables.c b/src/mainboard/pcengines/alix1c/irq_tables.c
index ff30328ae1..a7fd6deea7 100644
--- a/src/mainboard/pcengines/alix1c/irq_tables.c
+++ b/src/mainboard/pcengines/alix1c/irq_tables.c
@@ -106,46 +106,5 @@ const struct irq_routing_table intel_irq_routing_table = {
unsigned long write_pirq_routing_table(unsigned long addr)
{
- int i, j, k, num_entries;
- unsigned char pirq[4];
- uint16_t chipset_irq_map;
- uint32_t pciAddr, pirtable_end;
- struct irq_routing_table *pirq_tbl;
-
- pirtable_end = copy_pirq_routing_table(addr);
-
- /* Set up chipset IRQ steering. */
- pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
- chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
- printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
- chipset_irq_map);
- outl(pciAddr & ~3, 0xCF8);
- outl(chipset_irq_map, 0xCFC);
-
- pirq_tbl = (struct irq_routing_table *) (addr);
- num_entries = (pirq_tbl->size - 32) / 16;
-
- /* Set PCI IRQs. */
- for (i = 0; i < num_entries; i++) {
- printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
- pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
- for (j = 0; j < 4; j++) {
- printk_debug("INT: %c bitmap: %x ", 'A' + j,
- pirq_tbl->slots[i].irq[j].bitmap);
- /* Finds lsb in bitmap to IRQ#. */
- for (k = 0;
- (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1))
- && (pirq_tbl->slots[i].irq[j].bitmap != 0);
- k++);
- pirq[j] = k;
- printk_debug("PIRQ: %d\n", k);
- }
-
- /* Bus, device, slots IRQs for {A,B,C,D}. */
- pci_assign_irqs(pirq_tbl->slots[i].bus,
- pirq_tbl->slots[i].devfn >> 3, pirq);
- }
-
- /* Put the PIR table in memory and checksum. */
- return pirtable_end;
+ return copy_pirq_routing_table(addr);
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-24 07:37:32 +0000