summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
index dad18e7ff7..baf951015e 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
@@ -10,6 +10,24 @@ chip soc/intel/cannonlake
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[8]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"
+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
+
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device