diff options
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/nyan/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/google/nyan_big/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/google/nyan_blaze/romstage.c | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index f3304ae392..b94d2dc780 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -55,7 +55,7 @@ static void __attribute__((noinline)) romstage(void) /* Device memory below DRAM is uncached. */ mmu_config_range(0, dram_start_mb, DCACHE_OFF); /* SRAM is cached. MMU code will round size up to page size. */ - mmu_config_range((uintptr_t)_sram/MiB, div_round_up(_sram_size, MiB), + mmu_config_range((uintptr_t)_sram/MiB, DIV_ROUND_UP(_sram_size, MiB), DCACHE_WRITEBACK); /* DRAM is cached. */ mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK); diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index f3304ae392..b94d2dc780 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -55,7 +55,7 @@ static void __attribute__((noinline)) romstage(void) /* Device memory below DRAM is uncached. */ mmu_config_range(0, dram_start_mb, DCACHE_OFF); /* SRAM is cached. MMU code will round size up to page size. */ - mmu_config_range((uintptr_t)_sram/MiB, div_round_up(_sram_size, MiB), + mmu_config_range((uintptr_t)_sram/MiB, DIV_ROUND_UP(_sram_size, MiB), DCACHE_WRITEBACK); /* DRAM is cached. */ mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK); diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index 602989df27..e44381f238 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -57,7 +57,7 @@ static void __attribute__((noinline)) romstage(void) /* Device memory below DRAM is uncached. */ mmu_config_range(0, dram_start_mb, DCACHE_OFF); /* SRAM is cached. MMU code will round size up to page size. */ - mmu_config_range((uintptr_t)_sram/MiB, div_round_up(_sram_size, MiB), + mmu_config_range((uintptr_t)_sram/MiB, DIV_ROUND_UP(_sram_size, MiB), DCACHE_WRITEBACK); /* The space above DRAM is uncached. */ if (dram_end_mb < 4096) |