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-rw-r--r--src/mainboard/advansus/a785e-i/romstage.c3
-rw-r--r--src/mainboard/amd/bimini_fam10/romstage.c3
-rw-r--r--src/mainboard/amd/mahogany/romstage.c3
-rw-r--r--src/mainboard/amd/mahogany_fam10/romstage.c3
-rw-r--r--src/mainboard/amd/tilapia_fam10/romstage.c3
-rw-r--r--src/mainboard/asrock/939a785gmh/romstage.c3
-rw-r--r--src/mainboard/asus/m4a78-em/romstage.c3
-rw-r--r--src/mainboard/asus/m4a785-m/romstage.c3
-rw-r--r--src/mainboard/asus/m5a88-v/romstage.c3
-rw-r--r--src/mainboard/avalue/eax-785e/romstage.c3
-rw-r--r--src/mainboard/gigabyte/ma785gm/romstage.c3
-rw-r--r--src/mainboard/gigabyte/ma785gmt/romstage.c3
-rw-r--r--src/mainboard/gigabyte/ma78gm/romstage.c3
-rw-r--r--src/mainboard/iei/kino-780am2-fam10/romstage.c3
-rw-r--r--src/mainboard/jetway/pa78vm5/romstage.c3
15 files changed, 15 insertions, 30 deletions
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index 2c7ec83dd1..e59773f5ad 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -41,7 +41,7 @@
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <southbridge/amd/sb800/smbus.h>
#include <southbridge/amd/sb800/sb800.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "southbridge/amd/sb800/early_setup.c"
#include <arch/early_variables.h>
#include <cbmem.h>
@@ -205,7 +205,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
amdmct_cbmem_store_info(sysinfo);
- rs780_before_pci_init();
sb800_before_pci_init();
post_code(0x42);
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index 1ca1d81b26..0c26416e75 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -41,7 +41,7 @@
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "southbridge/amd/sb800/early_setup.c"
#include <spd.h>
@@ -200,7 +200,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
amdmct_cbmem_store_info(sysinfo);
- rs780_before_pci_init();
sb800_before_pci_init();
post_code(0x42);
diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
index 7cc45bf36e..979904a06f 100644
--- a/src/mainboard/amd/mahogany/romstage.c
+++ b/src/mainboard/amd/mahogany/romstage.c
@@ -47,7 +47,7 @@ int spd_read_byte(u32 device, u32 address)
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include <northbridge/amd/amdk8/amdk8.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "lib/generic_sdram.c"
@@ -142,6 +142,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
}
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index d292205a49..e5766c8ae9 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -46,7 +46,7 @@
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
@@ -216,7 +216,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("After MCT init before CAR disabled.");
- rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
post_code(0x42);
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index e7e1e2fa15..89d170cb5a 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -45,7 +45,7 @@
#include <arch/early_variables.h>
#include <cbmem.h>
#include <spd.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
@@ -201,7 +201,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
amdmct_cbmem_store_info(sysinfo);
- rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
post_code(0x42);
diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
index 135db10dd2..d6a85ccee8 100644
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ b/src/mainboard/asrock/939a785gmh/romstage.c
@@ -49,7 +49,7 @@ int spd_read_byte(u32 device, u32 address)
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include <northbridge/amd/amdk8/amdk8.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
@@ -208,6 +208,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
}
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index f616d570fc..6392f8f459 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -46,7 +46,7 @@
#include <arch/early_variables.h>
#include <cbmem.h>
#include <spd.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
@@ -216,7 +216,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("After MCT init before CAR disabled.");
- rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
post_code(0x42);
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index d6cc5784ec..dd61c8f7a4 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -47,7 +47,7 @@
#include <arch/early_variables.h>
#include <cbmem.h>
#include <spd.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
@@ -217,7 +217,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("After MCT init before CAR disabled.");
- rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
post_code(0x42);
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index 2993cb4676..e3f3f3cfee 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -44,7 +44,7 @@
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "southbridge/amd/sb800/early_setup.c"
#include "spd.h"
#include <reset.h>
@@ -221,7 +221,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("After MCT init before CAR disabled.");
- rs780_before_pci_init();
sb800_before_pci_init();
post_code(0x42);
diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
index 913b4602ce..993d078999 100644
--- a/src/mainboard/avalue/eax-785e/romstage.c
+++ b/src/mainboard/avalue/eax-785e/romstage.c
@@ -44,7 +44,7 @@
#include <cbmem.h>
#include "spd.h"
#include <reset.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "southbridge/amd/sb800/early_setup.c"
#include "resourcemap.c"
@@ -205,7 +205,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
amdmct_cbmem_store_info(sysinfo);
- rs780_before_pci_init();
sb800_before_pci_init();
post_code(0x42);
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
index b578739106..98bc00fd03 100644
--- a/src/mainboard/gigabyte/ma785gm/romstage.c
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -43,7 +43,7 @@
#include <arch/early_variables.h>
#include <cbmem.h>
#include <spd.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
@@ -212,7 +212,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("After MCT init before CAR disabled.");
- rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
post_code(0x42);
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index a21cf70049..81d4c6b36b 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -43,7 +43,7 @@
#include <arch/early_variables.h>
#include <cbmem.h>
#include <spd.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
@@ -212,7 +212,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("After MCT init before CAR disabled.");
- rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
post_code(0x42);
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index 98d038f5a9..9f4dd441d4 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -46,7 +46,7 @@
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
@@ -214,7 +214,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("After MCT init before CAR disabled.");
- rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
post_code(0x42);
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index 141b22bc38..866a9a89bb 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -46,7 +46,7 @@
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
@@ -214,7 +214,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("After MCT init before CAR disabled.");
- rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
post_code(0x42);
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 163b2ebe9d..760fc13aed 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -47,7 +47,7 @@
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
@@ -219,7 +219,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("After MCT init before CAR disabled.");
- rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
post_code(0x42);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 03:04:40 +0000