diff options
Diffstat (limited to 'src/mainboard')
12 files changed, 24 insertions, 24 deletions
diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index 09593b7b53..26a53366b4 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -26,7 +26,7 @@ chip soc/intel/broadwell device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # EC range is 0x800-0x9ff register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x00fc0901" @@ -83,6 +83,6 @@ chip soc/intel/broadwell device pci 1f.2 on end # SATA Controller device pci 1f.3 off end # SMBus device pci 1f.6 on end # Thermal -# end + end end end diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb index f5f3eeacdf..81110408c1 100644 --- a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb @@ -8,12 +8,12 @@ chip soc/intel/broadwell register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x5" register "sata_port1_gen3_dtle" = "0x5" device pci 1f.2 on end # SATA Controller -# end + end end end diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb index 5a64648cd1..eb33d433e8 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb @@ -8,12 +8,12 @@ chip soc/intel/broadwell register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x7" register "sata_port1_gen3_dtle" = "0x5" device pci 1f.2 on end # SATA Controller -# end + end end end diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index 5b6ab9f858..60fb08cbf7 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -10,7 +10,7 @@ chip soc/intel/broadwell register "s0ix_enable" = "0" device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch register "sata_devslp_disable" = "0x1" register "sio_i2c0_voltage" = "1" # 1.8V @@ -36,6 +36,6 @@ chip soc/intel/broadwell device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2) device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus -# end + end end end diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb index 924e7d3c90..c7e2421ee8 100644 --- a/src/mainboard/google/auron/variants/gandof/overridetree.cb +++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb @@ -8,12 +8,12 @@ chip soc/intel/broadwell register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x5" register "sata_port1_gen3_dtle" = "0x5" device pci 1f.2 on end # SATA Controller -# end + end end end diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb index f5f3eeacdf..81110408c1 100644 --- a/src/mainboard/google/auron/variants/lulu/overridetree.cb +++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb @@ -8,12 +8,12 @@ chip soc/intel/broadwell register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x5" register "sata_port1_gen3_dtle" = "0x5" device pci 1f.2 on end # SATA Controller -# end + end end end diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index 93445756e2..d8aec0ae04 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -17,7 +17,7 @@ chip soc/intel/broadwell register "s0ix_enable" = "0" device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch register "sata_port0_gen3_tx" = "0x72" # Set I2C0 to 1.8V @@ -37,6 +37,6 @@ chip soc/intel/broadwell device pci 1c.2 on end # PCIe Port #3 device pci 1d.0 off end # USB2 EHCI device pci 1f.2 on end # SATA Controller -# end + end end end diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index e5508228c9..94fd8044c1 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -18,7 +18,7 @@ chip soc/intel/broadwell device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # SuperIO range is 0x700-0x73f register "gen2_dec" = "0x003c0701" @@ -113,6 +113,6 @@ chip soc/intel/broadwell device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus device pci 1f.6 on end # Thermal -# end + end end end diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb index 927a60344c..29041aaeca 100644 --- a/src/mainboard/intel/wtm2/devicetree.cb +++ b/src/mainboard/intel/wtm2/devicetree.cb @@ -17,7 +17,7 @@ chip soc/intel/broadwell device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch register "alt_gp_smi_en" = "0x0000" register "gpe0_en_1" = "0x00000400" register "gpe0_en_2" = "0x00000000" @@ -55,6 +55,6 @@ chip soc/intel/broadwell device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus device pci 1f.6 on end # Thermal -# end + end end end diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb index 4f34f7d6d4..0d0fc720f7 100644 --- a/src/mainboard/purism/librem_bdw/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -24,7 +24,7 @@ chip soc/intel/broadwell device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # EC host command ranges are in 0x380-0x383 & 0x80-0x8f register "gen1_dec" = "0x00000381" register "gen2_dec" = "0x000c0081" @@ -57,6 +57,6 @@ chip soc/intel/broadwell device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus device pci 1f.6 off end # Thermal -# end + end end end diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb index 237e6979ec..256077cbd9 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/broadwell device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # Port 0 is HDD # Port 3 is M.2 NGFF register "sata_port_map" = "0x9" @@ -11,6 +11,6 @@ chip soc/intel/broadwell register "sata_port3_gen3_dtle" = "9" device pci 1c.2 on end # PCIe Port #3 - LAN -# end + end end end diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb index b9b29cd6ff..d88c19c26a 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/broadwell device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # Port 0 is HDD # Port 1 is M.2 NGFF register "sata_port_map" = "0x3" @@ -11,6 +11,6 @@ chip soc/intel/broadwell register "sata_port1_gen3_dtle" = "9" device pci 1d.0 on end # USB2 EHCI -# end + end end end |