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-rw-r--r--src/mainboard/51nb/Kconfig19
-rw-r--r--src/mainboard/51nb/Kconfig.name2
-rw-r--r--src/mainboard/51nb/x210/Kconfig53
-rw-r--r--src/mainboard/51nb/x210/Kconfig.name2
-rw-r--r--src/mainboard/51nb/x210/Makefile.inc4
-rw-r--r--src/mainboard/51nb/x210/acpi/battery.asl93
-rw-r--r--src/mainboard/51nb/x210/acpi/ec.asl115
-rw-r--r--src/mainboard/51nb/x210/acpi/graphics.asl60
-rw-r--r--src/mainboard/51nb/x210/acpi/mainboard.asl42
-rw-r--r--src/mainboard/51nb/x210/acpi/platform.asl37
-rw-r--r--src/mainboard/51nb/x210/acpi/superio.asl4
-rw-r--r--src/mainboard/51nb/x210/board.fmd15
-rw-r--r--src/mainboard/51nb/x210/board_info.txt8
-rw-r--r--src/mainboard/51nb/x210/devicetree.cb167
-rw-r--r--src/mainboard/51nb/x210/dsdt.asl34
-rw-r--r--src/mainboard/51nb/x210/gpio.h182
-rw-r--r--src/mainboard/51nb/x210/hda_verb.c40
-rw-r--r--src/mainboard/51nb/x210/mainboard.c22
-rw-r--r--src/mainboard/51nb/x210/romstage.c45
19 files changed, 944 insertions, 0 deletions
diff --git a/src/mainboard/51nb/Kconfig b/src/mainboard/51nb/Kconfig
new file mode 100644
index 0000000000..2b3a493c7a
--- /dev/null
+++ b/src/mainboard/51nb/Kconfig
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This file is part of the coreboot project.
+
+if VENDOR_51NB
+
+choice
+ prompt "Mainboard model"
+
+source "src/mainboard/51nb/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/51nb/*/Kconfig"
+
+config MAINBOARD_VENDOR
+ string "Mainboard Vendor"
+ default "51NB"
+
+endif # VENDOR_51NB
diff --git a/src/mainboard/51nb/Kconfig.name b/src/mainboard/51nb/Kconfig.name
new file mode 100644
index 0000000000..6f99514dff
--- /dev/null
+++ b/src/mainboard/51nb/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_51NB
+ bool "51NB"
diff --git a/src/mainboard/51nb/x210/Kconfig b/src/mainboard/51nb/x210/Kconfig
new file mode 100644
index 0000000000..70b3da86f9
--- /dev/null
+++ b/src/mainboard/51nb/x210/Kconfig
@@ -0,0 +1,53 @@
+if BOARD_51NB_X210
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_8192
+ select EC_51NB_NPCE985LA0DX
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+ select SOC_INTEL_KABYLAKE
+ select SPD_READ_BY_WORD
+ select SYSTEM_TYPE_LAPTOP
+
+config MAINBOARD_FAMILY
+ string
+ default "X210"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "X210"
+
+config MAINBOARD_VERSION
+ string
+ default "1.0"
+
+config MAINBOARD_DIR
+ string
+ default "51nb/x210"
+
+config MAX_CPUS
+ int
+ default 8
+
+config VGA_BIOS_ID
+ string
+ default "8086,5917"
+
+config DIMM_MAX
+ int
+ default 2
+
+config DIMM_SPD_SIZE
+ int
+ default 512
+
+config FMDFILE
+ string
+ default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd"
+
+config NO_POST
+ default y
+
+endif
diff --git a/src/mainboard/51nb/x210/Kconfig.name b/src/mainboard/51nb/x210/Kconfig.name
new file mode 100644
index 0000000000..1cae5dda0a
--- /dev/null
+++ b/src/mainboard/51nb/x210/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_51NB_X210
+ bool "51NB X210"
diff --git a/src/mainboard/51nb/x210/Makefile.inc b/src/mainboard/51nb/x210/Makefile.inc
new file mode 100644
index 0000000000..6555e990e6
--- /dev/null
+++ b/src/mainboard/51nb/x210/Makefile.inc
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This file is part of the coreboot project.
+
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c
diff --git a/src/mainboard/51nb/x210/acpi/battery.asl b/src/mainboard/51nb/x210/acpi/battery.asl
new file mode 100644
index 0000000000..9064ad5cee
--- /dev/null
+++ b/src/mainboard/51nb/x210/acpi/battery.asl
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+Device (BAT)
+{
+ Name (_HID, EisaId ("PNP0C0A"))
+ Name (_UID, 1)
+ Name (_PCL, Package () { \_SB })
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If (B1SS)
+ {
+ Return (0x1F)
+ }
+ Else
+ {
+ Return (0x0F)
+ }
+ }
+
+ Name (PBIF, Package () {
+ 0x00000001, /* 0x00: Power Unit: mAH */
+ 0xFFFFFFFF, /* 0x01: Design Capacity */
+ 0xFFFFFFFF, /* 0x02: Last Full Charge Capacity */
+ 0x00000001, /* 0x03: Battery Technology: Rechargeable */
+ 0xFFFFFFFF, /* 0x04: Design Voltage */
+ 0x00000000, /* 0x05: Design Capacity of Warning */
+ 0xFFFFFFFF, /* 0x06: Design Capacity of Low */
+ 0x00000001, /* 0x07: Capacity Granularity 1 */
+ 0x00000001, /* 0x08: Capacity Granularity 2 */
+ "Y91", /* 0x09: Model Number */
+ "", /* 0x0a: Serial Number */
+ "LION", /* 0x0b: Battery Type */
+ "CJOYIN" /* 0x0c: OEM Information */
+ })
+
+ Method (_BIF, 0, Serialized)
+ {
+ /* Design Capacity */
+ Store (DGCP, Index (PBIF, 1))
+
+ /* Last Full Charge Capacity */
+ Store (FLCP, Index (PBIF, 2))
+
+ /* Design Voltage */
+ Store (DGVO, Index (PBIF, 4))
+
+ /* Design Capacity of Warning */
+ Store (BDW, Index (PBIF, 5))
+
+ /* Design Capacity of Low */
+ Store (BDL, Index (PBIF, 6))
+
+ Return (PBIF)
+ }
+
+ Name (PBST, Package () {
+ 0x00000000, /* 0x00: Battery State */
+ 0xFFFFFFFF, /* 0x01: Battery Present Rate */
+ 0xFFFFFFFF, /* 0x02: Battery Remaining Capacity */
+ 0xFFFFFFFF, /* 0x03: Battery Present Voltage */
+ })
+
+ Method (_BST, 0, NotSerialized) // _BST: Battery Status
+ {
+ /*
+ * 0: BATTERY STATE
+ *
+ * bit 0 = discharging
+ * bit 1 = charging
+ * bit 2 = critical level
+ */
+ Store (BSTS, Index (PBST, 0))
+
+ /*
+ * 1: BATTERY PRESENT RATE
+ */
+ Store (BPR, Index (PBST, 1))
+
+ /*
+ * 2: BATTERY REMAINING CAPACITY
+ */
+ Store (BRC, Index (PBST, 2))
+
+ /*
+ * 3: BATTERY PRESENT VOLTAGE
+ */
+ Store (BPV, Index (PBST, 3))
+
+ Return (PBST)
+ }
+}
diff --git a/src/mainboard/51nb/x210/acpi/ec.asl b/src/mainboard/51nb/x210/acpi/ec.asl
new file mode 100644
index 0000000000..5ebc0aca4c
--- /dev/null
+++ b/src/mainboard/51nb/x210/acpi/ec.asl
@@ -0,0 +1,115 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+Device (EC)
+{
+ Name (_HID, EisaId ("PNP0C09"))
+ Name (_UID, 0)
+
+ Name (_GPE, 0x4F) // _GPE: General Purpose Events
+ Name (_CRS, ResourceTemplate () {
+ IO (Decode16, 0x62, 0x62, 1, 1)
+ IO (Decode16, 0x66, 0x66, 1, 1)
+ })
+
+ OperationRegion (ERAM, EmbeddedControl, Zero, 0xFF)
+ Field (ERAM, ByteAcc, Lock, Preserve)
+ {
+ Offset (0x50),
+ CTMP, 8,
+ CFAN, 8,
+ B1SS, 1,
+ BSTS, 2,
+ ACIN, 1,
+ Offset (0x53),
+ BKLG, 8,
+ TOUP, 1,
+ WIRE, 1,
+ BLTH, 1,
+ LIDC, 1,
+ APFG, 1,
+ WRST, 1,
+ BTST, 1,
+ ACEB, 1,
+ CAME, 1,
+ Offset (0x60),
+ DGCP, 16,
+ FLCP, 16,
+ DGVO, 16,
+ BDW, 16,
+ BDL, 16,
+ BPR, 16,
+ BRC, 16,
+ BPV, 16
+ }
+
+ Method (_REG, 2, NotSerialized)
+ {
+ /* Initialize AC power state */
+ Store (ACIN, \PWRS)
+
+ /* Initialize LID switch state */
+ Store (LIDC, \LIDS)
+ }
+
+ /* KEY_BRIGHTNESSUP */
+ Method (_Q04)
+ {
+ Notify(\_SB.PCI0.GFX0.LCD, 0x86)
+ }
+
+ /* KEY_BRIGHTNESSDOWN */
+ Method (_Q05)
+ {
+ Notify(\_SB.PCI0.GFX0.LCD, 0x87)
+ }
+
+ /* Battery Information Event */
+ Method (_Q0C)
+ {
+ Notify (BAT, 0x81)
+ }
+
+ /* AC event */
+ Method (_Q0D)
+ {
+ Store (ACIN, \PWRS)
+ Notify (AC, 0x80)
+ }
+
+ /* Lid event */
+ Method (_Q0E)
+ {
+ Store (LIDC, \LIDS)
+ Notify (LID0, 0x80)
+ }
+
+ /* Battery Information Event */
+ Method (_Q13)
+ {
+ Notify (BAT, 0x81)
+ }
+
+ /* Battery Status Event */
+ Method (_Q14)
+ {
+ Notify (BAT, 0x80)
+ }
+
+ Device (AC)
+ {
+ Name (_HID, "ACPI0003")
+ Name (_PCL, Package () { \_SB })
+
+ Method (_STA)
+ {
+ Return (0x0F)
+ }
+ Method (_PSR)
+ {
+ Return (\PWRS)
+ }
+ }
+
+ #include "battery.asl"
+}
diff --git a/src/mainboard/51nb/x210/acpi/graphics.asl b/src/mainboard/51nb/x210/acpi/graphics.asl
new file mode 100644
index 0000000000..218b95758f
--- /dev/null
+++ b/src/mainboard/51nb/x210/acpi/graphics.asl
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+Device (GFX0)
+{
+ Name (_ADR, 0x00020000)
+ Method (_DOS, 1, NotSerialized)
+ {
+ /* We never do anything in firmware, so _DOS is a noop */
+ }
+ Method (_DOD, 0, NotSerialized)
+ {
+ return (Package (0x03)
+ {
+ 0x80000410, /* LCD */
+ 0x80000120, /* VGA */
+ 0x80000330 /* DP */
+ })
+ }
+ Device (LCD)
+ {
+ Method (_ADR, 0, Serialized)
+ {
+ Return (0x800000410)
+ }
+
+ Method (_BCL, 0, NotSerialized)
+ {
+ Return (Package (0x12)
+ {
+ 0x0A,
+ 0x0F,
+ 0x00,
+ 0x01,
+ 0x02,
+ 0x03,
+ 0x04,
+ 0x05,
+ 0x06,
+ 0x07,
+ 0x08,
+ 0x09,
+ 0x0A,
+ 0x0B,
+ 0x0C,
+ 0x0D,
+ 0x0E,
+ 0x0F
+ })
+ }
+ Method (_BCM, 1, NotSerialized)
+ {
+ \_SB.PCI0.LPCB.EC.BKLG = Arg0
+ }
+ Method (_BQC, 0, NotSerialized)
+ {
+ Return (\_SB.PCI0.LPCB.EC.BKLG)
+ }
+ }
+}
diff --git a/src/mainboard/51nb/x210/acpi/mainboard.asl b/src/mainboard/51nb/x210/acpi/mainboard.asl
new file mode 100644
index 0000000000..fb389a40ad
--- /dev/null
+++ b/src/mainboard/51nb/x210/acpi/mainboard.asl
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+Scope (\_SB)
+{
+ Device (LID0)
+ {
+ Name (_HID, EisaId ("PNP0C0D"))
+
+ Method (_STA)
+ {
+ Return (0xF)
+ }
+
+ Method (_LID)
+ {
+ Return (\LIDS)
+ }
+ }
+
+ Device (PWRB)
+ {
+ Name (_HID, EisaId ("PNP0C0C"))
+
+ Method (_STA)
+ {
+ Return (0xF)
+ }
+
+ Name (_PRW, Package () { 27, 4 })
+ }
+
+ Device (SLPB)
+ {
+ Name (_HID, EisaId ("PNP0C0E"))
+
+ Method (_STA)
+ {
+ Return (0xF)
+ }
+ }
+}
diff --git a/src/mainboard/51nb/x210/acpi/platform.asl b/src/mainboard/51nb/x210/acpi/platform.asl
new file mode 100644
index 0000000000..d0e34b6254
--- /dev/null
+++ b/src/mainboard/51nb/x210/acpi/platform.asl
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+/* Enable ACPI _SWS methods */
+#include <soc/intel/common/acpi/acpi_wake_source.asl>
+
+/*
+ * The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method (_PIC, 1)
+{
+ /* Remember the OS' IRQ routing choice. */
+ Store (Arg0, PICM)
+}
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method (_PTS, 1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method (_WAK, 1)
+{
+ Store(\_SB.PCI0.LPCB.EC.LIDC, \LIDS)
+ Store(\_SB.PCI0.LPCB.EC.ACIN, \PWRS)
+ Return (Package (){ 0, 0 })
+}
diff --git a/src/mainboard/51nb/x210/acpi/superio.asl b/src/mainboard/51nb/x210/acpi/superio.asl
new file mode 100644
index 0000000000..cb77a3c7a8
--- /dev/null
+++ b/src/mainboard/51nb/x210/acpi/superio.asl
@@ -0,0 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/51nb/x210/board.fmd b/src/mainboard/51nb/x210/board.fmd
new file mode 100644
index 0000000000..1955a05409
--- /dev/null
+++ b/src/mainboard/51nb/x210/board.fmd
@@ -0,0 +1,15 @@
+#
+# Manually defined FMD in order to ensure that space is reserved for the EC
+# at the base of the BIOS region.
+#
+
+FLASH 8M {
+ BIOS@0x200000 0x600000 {
+ EC@0x0 0x10000
+ RW_MRC_CACHE@0x10000 0x10000
+ SMMSTORE@0x20000 0x40000
+ CONSOLE@0x60000 0x20000
+ FMAP@0x80000 0x200
+ COREBOOT(CBFS)
+ }
+}
diff --git a/src/mainboard/51nb/x210/board_info.txt b/src/mainboard/51nb/x210/board_info.txt
new file mode 100644
index 0000000000..65c46089bc
--- /dev/null
+++ b/src/mainboard/51nb/x210/board_info.txt
@@ -0,0 +1,8 @@
+Vendor name: 51NB
+Board name: Thinkpad X210
+Category: laptop
+ROM package: SOIC8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2017
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb
new file mode 100644
index 0000000000..7ee3b2c87e
--- /dev/null
+++ b/src/mainboard/51nb/x210/devicetree.cb
@@ -0,0 +1,167 @@
+chip soc/intel/skylake
+
+ # Enable deep Sx states
+ register "deep_s3_enable_ac" = "1"
+ register "deep_s3_enable_dc" = "1"
+ register "deep_s5_enable_ac" = "1"
+ register "deep_s5_enable_dc" = "1"
+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
+
+ register "eist_enable" = "1"
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "gpe0_dw0" = "GPP_C"
+ register "gpe0_dw1" = "GPP_D"
+ register "gpe0_dw2" = "GPP_E"
+
+ register "gen1_dec" = "0x000c0081"
+ register "gen2_dec" = "0x000c0681"
+ register "gen3_dec" = "0x000c1641"
+
+ # Enable "Intel Speed Shift Technology"
+ register "speed_shift_enable" = "1"
+
+ # Disable DPTF
+ register "dptf_enable" = "0"
+
+ # FSP Configuration
+ register "ProbelessTrace" = "0"
+ register "EnableLan" = "0"
+ register "EnableSata" = "1"
+ register "SataSalpSupport" = "1"
+ register "SataMode" = "0"
+
+ # The X210 has 3 SATA ports: a full SATA port, mSATA, and SATA over M.2
+ register "SataPortsEnable[0]" = "1"
+ register "SataPortsEnable[1]" = "1"
+ register "SataPortsEnable[2]" = "1"
+ register "SataPortsDevSlp[0]" = "1"
+ register "SataPortsDevSlp[1]" = "1"
+ register "SataPortsDevSlp[2]" = "1"
+ register "SataPwrOptEnable" = "1"
+ register "EnableAzalia" = "1"
+ register "DspEnable" = "0"
+ register "IoBufferOwnership" = "0"
+ register "EnableTraceHub" = "0"
+ register "SsicPortEnable" = "0"
+ register "SmbusEnable" = "1"
+ register "Cio2Enable" = "0"
+ register "ScsEmmcEnabled" = "0"
+ register "ScsEmmcHs400Enabled" = "0"
+ register "ScsSdCardEnabled" = "0"
+ register "PttSwitch" = "0"
+ register "SkipExtGfxScan" = "1"
+ register "Device4Enable" = "1"
+ register "HeciEnabled" = "1"
+ register "SaGv" = "SaGv_Enabled"
+ register "PmConfigSlpS3MinAssert" = "2" # 50ms
+ register "PmConfigSlpS4MinAssert" = "1" # 1s
+ register "PmConfigSlpSusMinAssert" = "3" # 500ms
+ register "PmConfigSlpAMinAssert" = "3" # 2s
+ register "PmTimerDisabled" = "0"
+
+ register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+ register "pirqa_routing" = "PCH_IRQ11"
+ register "pirqb_routing" = "PCH_IRQ10"
+ register "pirqc_routing" = "PCH_IRQ11"
+ register "pirqd_routing" = "PCH_IRQ11"
+ register "pirqe_routing" = "PCH_IRQ11"
+ register "pirqf_routing" = "PCH_IRQ11"
+ register "pirqg_routing" = "PCH_IRQ11"
+ register "pirqh_routing" = "PCH_IRQ11"
+
+ register "PmConfigPciClockRun" = "1"
+
+ # Enable Root Ports 3, 4 and 9
+ register "PcieRpEnable[2]" = "1" # Ethernet controller
+ register "PcieRpClkReqSupport[2]" = "1"
+ register "PcieRpClkReqNumber[2]" = "0"
+ register "PcieRpClkSrcNumber[2]" = "0"
+ register "PcieRpAdvancedErrorReporting[2]" = "1"
+ register "PcieRpLtrEnable[2]" = "1"
+
+ register "PcieRpEnable[3]" = "1" # Wireless controller
+ register "PcieRpClkReqSupport[3]" = "1"
+ register "PcieRpClkReqNumber[3]" = "1"
+ register "PcieRpClkSrcNumber[3]" = "1"
+ register "PcieRpAdvancedErrorReporting[3]" = "1"
+ register "PcieRpLtrEnable[3]" = "1"
+
+ register "PcieRpEnable[8]" = "1" # NVMe controller
+ register "PcieRpClkReqSupport[8]" = "0"
+ register "PcieRpClkReqNumber[8]" = "2"
+ register "PcieRpClkSrcNumber[8]" = "2"
+ register "PcieRpAdvancedErrorReporting[8]" = "1"
+ register "PcieRpLtrEnable[8]" = "1"
+
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (left)
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left)
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Port (right)
+ register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # Webcam
+ register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # WiFi PCIe port USB
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left)
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left)
+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right)
+
+ # PL1 override 25W
+ register "tdp_pl1_override" = "25"
+
+ # PL2 override 44W
+ register "tdp_pl2_override" = "44"
+
+ # Send an extra VR mailbox command for the PS4 exit issue
+ register "SendVrMbxCmd" = "2"
+
+ # Lock Down
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ }"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 14.0 on end # USB xHCI
+ device pci 14.1 off end # USB xDCI (OTG)
+ device pci 14.2 on end # Thermal Subsystem
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 17.0 on end # SATA
+ device pci 1c.0 off end # PCI Express Port 1
+ device pci 1c.1 off end # PCI Express Port 2
+ device pci 1c.2 on end # PCI Express Port 3
+ device pci 1c.3 on end # PCI Express Port 4
+ device pci 1c.4 off end # PCI Express Port 5
+ device pci 1c.5 off end # PCI Express Port 6
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 off end # PCI Express Port 8
+ device pci 1d.0 on end # PCI Express Port 9
+ device pci 1d.1 off end # PCI Express Port 10
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
+ device pci 1f.0 on
+ chip ec/51nb/npce985la0dx
+ device pnp 0c09.0 on end
+ device pnp 4e.5 on end
+ device pnp 4e.6 on end
+ device pnp 4e.11 on end
+ end
+ end # LPC Interface
+ device pci 1f.1 off end # P2SB
+ device pci 1f.2 on end # Power Management Controller
+ device pci 1f.3 on end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 off end # PCH SPI
+ device pci 1f.6 off end # GbE
+ end
+end
diff --git a/src/mainboard/51nb/x210/dsdt.asl b/src/mainboard/51nb/x210/dsdt.asl
new file mode 100644
index 0000000000..441a80dd4a
--- /dev/null
+++ b/src/mainboard/51nb/x210/dsdt.asl
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+#include <arch/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x05, // DSDT revision: ACPI v5.0
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725 // OEM revision
+)
+{
+ Name(\DSEN, 1)
+
+ #include "acpi/platform.asl"
+
+ #include <soc/intel/skylake/acpi/globalnvs.asl>
+
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <soc/intel/skylake/acpi/systemagent.asl>
+ #include <soc/intel/skylake/acpi/pch.asl>
+ #include "acpi/graphics.asl"
+ }
+
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ // Mainboard specific
+ #include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/51nb/x210/gpio.h b/src/mainboard/51nb/x210/gpio.h
new file mode 100644
index 0000000000..3e22ddee27
--- /dev/null
+++ b/src/mainboard/51nb/x210/gpio.h
@@ -0,0 +1,182 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+#ifndef __ACPI__
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+/* RCIN# */_PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x0),
+/* LAD0 */_PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00),
+/* LAD1 */_PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00),
+/* LAD2 */_PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00),
+/* LAD3 */_PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00),
+/* LFRAME# */_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0),
+/* SERIRQ */_PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_A7, 0x44000201, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_A8, 0x44000300, 0x3000),
+/* CLKOUT_LPC0 */_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000),
+/* CLKOUT_LPC1 */_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000),
+/* GPIO */_PAD_CFG_STRUCT(GPP_A11, 0x44000200, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_A12, 0x4000200, 0x0),
+/* SUSWARN#/SUSPWRDNACK */_PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0),
+/* SUS_STAT# */_PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0),
+/* SUS_ACK# */_PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x3000),
+/* CLKOUT_48 */_PAD_CFG_STRUCT(GPP_A16, 0x44000500, 0x0),
+/* ISH_GP7 */_PAD_CFG_STRUCT(GPP_A17, 0x44000700, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_A18, 0x44000300, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_A19, 0x44000300, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_A22, 0x44000201, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_A23, 0x44000100, 0x1000),
+/* n/a */_PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0),
+/* n/a */_PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B3, 0x84000102, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B4, 0x44000201, 0x0),
+/* SRCCLKREQ0# */_PAD_CFG_STRUCT(GPP_B5, 0x44000700, 0x0),
+/* SRCCLKREQ1# */_PAD_CFG_STRUCT(GPP_B6, 0x44000700, 0x0),
+/* SRCCLKREQ2# */_PAD_CFG_STRUCT(GPP_B7, 0x44000702, 0x0),
+/* SRCCLKREQ3# */_PAD_CFG_STRUCT(GPP_B8, 0x44000702, 0x0),
+/* SRCCLKREQ4# */_PAD_CFG_STRUCT(GPP_B9, 0x44000700, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B10, 0x44000102, 0x0),
+/* n/a */_PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0),
+/* SLP_S0# */_PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x0),
+/* PLTRST# */_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B14, 0x44000201, 0x1000),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B16, 0x84800102, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B17, 0x84800102, 0x3000),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B18, 0x84800102, 0x3000),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x0),
+/* GSPI1_CLK */_PAD_CFG_STRUCT(GPP_B20, 0x44000700, 0x1000),
+/* GSPI1_MISO */_PAD_CFG_STRUCT(GPP_B21, 0x44000700, 0x1000),
+/* GSPIO_MOSI */_PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x1000),
+/* SMBCLK */_PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0),
+/* SMBDATA */_PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000),
+/* GPIO */_PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000),
+/* SML0CLK */_PAD_CFG_STRUCT(GPP_C3, 0x44000702, 0x3000),
+/* SML0DATA */_PAD_CFG_STRUCT(GPP_C4, 0x44000702, 0x3000),
+/* GPIO */_PAD_CFG_STRUCT(GPP_C5, 0x44800100, 0x1000),
+/* RESERVED */_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00),
+/* RESERVED */_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00),
+/* UART0_RXD */_PAD_CFG_STRUCT(GPP_C8, 0x44000702, 0x3000),
+/* UART0_TXD */_PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x0),
+/* UART0_RTS# */_PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x0),
+/* UART0_CTS# */_PAD_CFG_STRUCT(GPP_C11, 0x44000702, 0x0),
+/* UART1_RXD */_PAD_CFG_STRUCT(GPP_C12, 0x44000702, 0x0),
+/* UART1_TXD */_PAD_CFG_STRUCT(GPP_C13, 0x44000700, 0x0),
+/* UART1_RTS# */_PAD_CFG_STRUCT(GPP_C14, 0x44000700, 0x0),
+/* UART1_CTS# */_PAD_CFG_STRUCT(GPP_C15, 0x44000702, 0x0),
+/* I2C0_SDA */_PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x3000),
+/* I2C0_SCL */_PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x3000),
+/* I2C1_SDA */_PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x3000),
+/* I2C1_SCL */_PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x3000),
+/* UART2_RXD */_PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x3000),
+/* UART2_TXD */_PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0),
+/* UART2_RTS# */_PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0),
+/* UART2_CTS# */_PAD_CFG_STRUCT(GPP_C23, 0x44000702, 0x0),
+/* n/a */_PAD_CFG_STRUCT(GPP_D0, 0x44000700, 0x0),
+/* n/a */_PAD_CFG_STRUCT(GPP_D1, 0x44000700, 0x0),
+/* n/a */_PAD_CFG_STRUCT(GPP_D2, 0x44000700, 0x0),
+/* n/a */_PAD_CFG_STRUCT(GPP_D3, 0x44000700, 0x0),
+/* ISH_I2C2_SDA */_PAD_CFG_STRUCT(GPP_D4, 0x44000700, 0x0),
+/* I2S_SFRM */_PAD_CFG_STRUCT(GPP_D5, 0x44000702, 0x3000),
+/* I2S_TXD */_PAD_CFG_STRUCT(GPP_D6, 0x44000702, 0x3000),
+/* I2S_RXD */_PAD_CFG_STRUCT(GPP_D7, 0x44000702, 0x3000),
+/* I2S_SCLK */_PAD_CFG_STRUCT(GPP_D8, 0x44000702, 0x3000),
+/* GPIO */_PAD_CFG_STRUCT(GPP_D9, 0x44000102, 0x3000),
+/* GPIO */_PAD_CFG_STRUCT(GPP_D10, 0x44000102, 0x3000),
+/* GPIO */_PAD_CFG_STRUCT(GPP_D11, 0x44000102, 0x3000),
+/* GPIO */_PAD_CFG_STRUCT(GPP_D12, 0x44000102, 0x3000),
+/* ISH_UART0_RXD */_PAD_CFG_STRUCT(GPP_D13, 0x44000702, 0x3000),
+/* ISH_UART0_TXD */_PAD_CFG_STRUCT(GPP_D14, 0x44000700, 0x3000),
+/* ISH_UART0_RTS# */_PAD_CFG_STRUCT(GPP_D15, 0x44000700, 0x0),
+/* ISH_UART0_CTS# */_PAD_CFG_STRUCT(GPP_D16, 0x44000702, 0x0),
+/* DMIC_CLK1 */_PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0),
+/* DMIC_DATA1 */_PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x1000),
+/* DMIC_CLK0 */_PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0),
+/* DMIC_DATA0 */_PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x1000),
+/* n/a */_PAD_CFG_STRUCT(GPP_D21, 0x44000700, 0x0),
+/* n/a */_PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0),
+/* ISH_I2C2_SCL */_PAD_CFG_STRUCT(GPP_D23, 0x44000700, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E0, 0x44000200, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E1, 0x44800102, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E3, 0x44000103, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x0),
+/* SATA_DEVSLP1 */_PAD_CFG_STRUCT(GPP_E5, 0x4000700, 0x0),
+/* SATA_DEVSLP2 */_PAD_CFG_STRUCT(GPP_E6, 0x4000700, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x0),
+/* SATA_LED# */_PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0),
+/* USB_OC0# */_PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x0),
+/* USB_OC1# */_PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x0),
+/* USB_OC2# */_PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E12, 0x44000300, 0x0),
+/* n/a */_PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0),
+/* n/a */_PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E15, 0x80880102, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E16, 0x84000102, 0x0),
+/* n/a */_PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0),
+/* n/a */_PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x3000),
+/* n/a */_PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000),
+/* n/a */_PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x3000),
+/* n/a */_PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E22, 0x44000000, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000),
+/* BATLOW# */_PAD_CFG_STRUCT(GPD0, 0x4000702, 0x3000),
+/* ACPRESENT */_PAD_CFG_STRUCT(GPD1, 0x4000702, 0x0),
+/* LAN_WAKE# */_PAD_CFG_STRUCT(GPD2, 0x4000602, 0x3c00),
+/* PWRBTN# */_PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3000),
+/* SLP_S3# */_PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0),
+/* SLP_S4# */_PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0),
+/* SLP_A# */_PAD_CFG_STRUCT(GPD6, 0x4000700, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPD7, 0x4000301, 0x0),
+/* SUSCLK */_PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0),
+/* SLP_WLAN# */_PAD_CFG_STRUCT(GPD9, 0x4000700, 0x0),
+/* SLP_S5# */_PAD_CFG_STRUCT(GPD10, 0x4000700, 0x0),
+/* LANPHYPC */_PAD_CFG_STRUCT(GPD11, 0x4000700, 0x0),
+/* SATAXPCIE3 */_PAD_CFG_STRUCT(GPP_F0, 0x44000700, 0x0),
+/* SATAXPCIE4 */_PAD_CFG_STRUCT(GPP_F1, 0x44000700, 0x0),
+/* SATAXPCIE5 */_PAD_CFG_STRUCT(GPP_F2, 0x44000700, 0x0),
+/* SATAXPCIE6 */_PAD_CFG_STRUCT(GPP_F3, 0x44000700, 0x0),
+/* SATAXPCIE7 */_PAD_CFG_STRUCT(GPP_F4, 0x44000702, 0x2003000),
+/* SATA_DEVSLP3 */_PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x2003000),
+/* SATA_DEVSLP4 */_PAD_CFG_STRUCT(GPP_F6, 0x44000702, 0x2003000),
+/* SATA_DEVSLP5 */_PAD_CFG_STRUCT(GPP_F7, 0x44000702, 0x2003000),
+/* SATA_DEVSLP6 */_PAD_CFG_STRUCT(GPP_F8, 0x44000702, 0x2003000),
+/* SATA_DEVSLP7 */_PAD_CFG_STRUCT(GPP_F9, 0x44000702, 0x2003000),
+/* n/a */_PAD_CFG_STRUCT(GPP_F10, 0x44000b02, 0x2003000),
+/* n/a */_PAD_CFG_STRUCT(GPP_F11, 0x44000b02, 0x2003000),
+/* SATA_SDATAOUT1 */_PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x0),
+/* SATA_SDATAOUT2 */_PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x0),
+/* n/a */_PAD_CFG_STRUCT(GPP_F14, 0x44000700, 0x0),
+/* USB_OC4# */_PAD_CFG_STRUCT(GPP_F15, 0x44000700, 0x0),
+/* USB_OC5# */_PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x0),
+/* USB_OC6# */_PAD_CFG_STRUCT(GPP_F17, 0x44000700, 0x0),
+/* USB_OC7# */_PAD_CFG_STRUCT(GPP_F18, 0x44000700, 0x0),
+/* eDP_VDDEN */_PAD_CFG_STRUCT(GPP_F19, 0x44000700, 0x0),
+/* eDP_BKLTEN */_PAD_CFG_STRUCT(GPP_F20, 0x44000700, 0x0),
+/* eDP_BKLTCTL */_PAD_CFG_STRUCT(GPP_F21, 0x44000700, 0x0),
+/* n/a */_PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_F23, 0x44000102, 0x0),
+/* FAN_TACH_0 */_PAD_CFG_STRUCT(GPP_G0, 0x44000700, 0x0),
+/* FAN_TACH_1 */_PAD_CFG_STRUCT(GPP_G1, 0x44000700, 0x0),
+/* FAN_TACH_2 */_PAD_CFG_STRUCT(GPP_G2, 0x44000700, 0x0),
+/* FAN_TACH_3 */_PAD_CFG_STRUCT(GPP_G3, 0x44000700, 0x0),
+/* FAN_TACH_4 */_PAD_CFG_STRUCT(GPP_G4, 0x44000700, 0x0),
+/* FAN_TACH_5 */_PAD_CFG_STRUCT(GPP_G5, 0x44000702, 0x0),
+/* FAN_TACH_6 */_PAD_CFG_STRUCT(GPP_G6, 0x44000700, 0x0),
+/* FAN_TACH_7 */_PAD_CFG_STRUCT(GPP_G7, 0x44000700, 0x1000),
+};
+
+#endif
+
+#endif
diff --git a/src/mainboard/51nb/x210/hda_verb.c b/src/mainboard/51nb/x210/hda_verb.c
new file mode 100644
index 0000000000..973024a376
--- /dev/null
+++ b/src/mainboard/51nb/x210/hda_verb.c
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x14f15069, /* Codec Vendor / Device ID: Conexant CX20585 */
+ 0x17aa2155, /* Subsystem ID */
+ 12, /* Number of jacks (NID entries) */
+
+ 0x0017ff00, /* Function Reset */
+ 0x0017ff00, /* Double Function Reset */
+ 0x0017ff00,
+ 0x0017ff00,
+
+ /* Bits 31:28 - Codec Address */
+ /* Bits 27:20 - NID */
+ /* Bits 19:8 - Verb ID */
+ /* Bits 7:0 - Payload */
+
+ /* NID 0x01, HDA Codec Subsystem ID */
+ AZALIA_SUBVENDOR(0, 0x17aa2155),
+
+ /* Pin Widget Verb Table */
+ AZALIA_PIN_CFG(0, 0x19, 0x042140f0),
+ AZALIA_PIN_CFG(0, 0x1a, 0x61a190f0),
+ AZALIA_PIN_CFG(0, 0x1b, 0x04a190f0),
+ AZALIA_PIN_CFG(0, 0x1c, 0x612140f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x601700f0),
+ AZALIA_PIN_CFG(0, 0x1e, 0x40f001f0),
+ AZALIA_PIN_CFG(0, 0x1f, 0x901701f0),
+ AZALIA_PIN_CFG(0, 0x1B, 0x40f001f0),
+ AZALIA_PIN_CFG(0, 0x22, 0x40f001f0),
+ AZALIA_PIN_CFG(0, 0x23, 0x90a601f0),
+};
+
+const u32 pc_beep_verbs[] = {
+};
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/51nb/x210/mainboard.c b/src/mainboard/51nb/x210/mainboard.c
new file mode 100644
index 0000000000..4364dd1519
--- /dev/null
+++ b/src/mainboard/51nb/x210/mainboard.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+#include <soc/ramstage.h>
+#include "gpio.h"
+
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
+{
+ /* Configure pads prior to SiliconInit() in case there's any
+ * dependencies during hardware initialization. */
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
+
+static void mainboard_enable(struct device *dev)
+{
+ /* Route 0x4e/4f to LPC */
+ lpc_enable_fixed_io_ranges(LPC_IOE_EC_4E_4F);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/51nb/x210/romstage.c b/src/mainboard/51nb/x210/romstage.c
new file mode 100644
index 0000000000..4ef10248c9
--- /dev/null
+++ b/src/mainboard/51nb/x210/romstage.c
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+#include <string.h>
+#include <assert.h>
+#include <soc/romstage.h>
+#include <spd_bin.h>
+#include <arch/io.h>
+#include <string.h>
+
+static void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
+{
+ /* Rcomp resistor */
+ const u16 RcompResistor[3] = { 121, 81, 100 };
+ memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor));
+}
+
+static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
+{
+ /* Rcomp target */
+ const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 };
+ memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
+}
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ FSP_M_CONFIG *mem_cfg;
+ struct spd_block blk = {
+ .addr_map = { 0x50, 0x52 },
+ };
+
+ mem_cfg = &mupd->FspmConfig;
+
+ get_spd_smbus(&blk);
+ dump_spd_info(&blk);
+ assert(blk.spd_array[0][0] != 0);
+
+ mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
+ mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
+
+ mem_cfg->DqPinsInterleaved = TRUE;
+ mem_cfg->MemorySpdDataLen = blk.len;
+ mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0];
+ mem_cfg->MemorySpdPtr10 = (uintptr_t) blk.spd_array[1];
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 00:46:40 +0000