diff options
Diffstat (limited to 'src/mainboard')
36 files changed, 50 insertions, 149 deletions
diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index 2929c0dc58..c95eeda358 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -26,7 +26,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { static const struct mem_controller memctrl[] = { { diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index e96de6f3fe..ad09c5c68e 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -22,7 +22,6 @@ #include <cpu/intel/romstage.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include <cpu/x86/bist.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> @@ -223,22 +222,18 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x51, 0x52, 0x53 }; - if (bist == 0) - enable_lapic(); + enable_lapic(); ich7_enable_lpc(); /* Set up the console */ console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "Soft reset detected, rebooting properly.\n"); diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index de73d016d3..7a2004f141 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -19,7 +19,6 @@ #include <device/pci_ops.h> #include <console/console.h> #include <cpu/intel/romstage.h> -#include <cpu/x86/bist.h> #include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/x4x.h> #include <southbridge/intel/common/gpio.h> @@ -82,7 +81,7 @@ static void ich7_enable_lpc(void) pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0291); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; @@ -95,7 +94,6 @@ void mainboard_romstage_entry(unsigned long bist) console_init(); - report_bist_failure(bist); enable_smbus(); x4x_early_init(); diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index 3af82f2907..91667ded57 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -39,7 +39,7 @@ static const struct rcba_config_instruction rcba_config[] = { RCBA_END_CONFIG, }; -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -94,7 +94,6 @@ void mainboard_romstage_entry(unsigned long bist) .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], - .bist = bist, }; romstage_common(&romstage_params); diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c index 91834cd5f6..a93c0ed2a9 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/romstage.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> @@ -31,11 +30,10 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); - report_bist_failure(bist); enable_smbus(); sdram_initialize(); diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c index 753f64076e..e77e3dc18d 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/romstage.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <superio/winbond/common/winbond.h> /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ @@ -32,11 +31,10 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); - report_bist_failure(bist); enable_smbus(); sdram_initialize(); diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c index 88f61f85b6..b51742907e 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/romstage.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> @@ -31,11 +30,10 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); - report_bist_failure(bist); enable_smbus(); sdram_initialize(); diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index 387cecb5dd..cc5b764b01 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <superio/winbond/common/winbond.h> /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ @@ -65,11 +64,10 @@ static void disable_spd(void) outb(0x67, PM_IO_BASE + 0x37); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); - report_bist_failure(bist); enable_smbus(); enable_pm(); diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index 4e17d34a85..c3275b5fe1 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -24,7 +24,6 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> #include <console/console.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> @@ -173,14 +172,13 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0, boot_mode = 0; u8 c_bsel = msr_get_fsb(); - if (bist == 0) - enable_lapic(); + enable_lapic(); ich7_enable_lpc(); @@ -189,9 +187,6 @@ void mainboard_romstage_entry(unsigned long bist) /* Set up the console */ console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected.\n"); boot_mode = 1; diff --git a/src/mainboard/asus/p5qc/romstage.c b/src/mainboard/asus/p5qc/romstage.c index a818b746c7..8af04e3cf9 100644 --- a/src/mainboard/asus/p5qc/romstage.c +++ b/src/mainboard/asus/p5qc/romstage.c @@ -20,7 +20,6 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <superio/winbond/w83667hg-a/w83667hg-a.h> #include <superio/winbond/common/winbond.h> @@ -66,7 +65,7 @@ static void ich10_enable_lpc(void) pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0x001c4701); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 }; u8 boot_path = 0; @@ -79,7 +78,6 @@ void mainboard_romstage_entry(unsigned long bist) console_init(); - report_bist_failure(bist); enable_smbus(); x4x_early_init(); diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index 7d028434d6..f15a187d94 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -21,7 +21,6 @@ #include <console/console.h> #include <cpu/intel/romstage.h> #include <cpu/intel/speedstep.h> -#include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/x4x.h> @@ -162,7 +161,7 @@ static void ich7_enable_lpc(void) pci_write_config32(LPC_DEV, 0x84, 0x000295); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; @@ -176,7 +175,6 @@ void mainboard_romstage_entry(unsigned long bist) console_init(); - report_bist_failure(bist); enable_smbus(); x4x_early_init(); diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c index ec4541f92e..16c3b47a30 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -17,7 +17,6 @@ */ #include <console/console.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <device/pci_ops.h> #include <northbridge/intel/x4x/iomap.h> @@ -81,7 +80,7 @@ static void ich7_enable_lpc(void) pci_write_config32(LPC_DEV, GEN1_DEC, 0x003c0a01); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { // ch0 ch1 #if CONFIG(BOARD_FOXCONN_G41S_K) @@ -101,7 +100,6 @@ void mainboard_romstage_entry(unsigned long bist) console_init(); - report_bist_failure(bist); enable_smbus(); x4x_early_init(); diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index d14b1c8719..2740aaa058 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -24,7 +24,6 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> @@ -232,12 +231,11 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0; - if (bist == 0) - enable_lapic(); + enable_lapic(); #if 0 /* Force PCIRST# */ @@ -252,9 +250,6 @@ void mainboard_romstage_entry(unsigned long bist) /* Set up the console */ console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); system_reset(); diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c index bdb0a38eab..7a2b38499b 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -21,7 +21,6 @@ #include <superio/ite/it8718f/it8718f.h> #include <superio/ite/common/ite.h> #include <console/console.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> @@ -135,12 +134,10 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0, boot_mode = 0; - - if (bist == 0) - enable_lapic(); + enable_lapic(); ich7_enable_lpc(); /* Enable SuperIO PM */ @@ -153,9 +150,6 @@ void mainboard_romstage_entry(unsigned long bist) /* Set up the console */ console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected.\n"); boot_mode = 1; diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index e20fb7a888..c13d4d6419 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -22,7 +22,6 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <superio/ite/it8718f/it8718f.h> #include <superio/ite/common/ite.h> @@ -122,7 +121,7 @@ static void ich7_enable_lpc(void) pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x007c0291); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; @@ -139,7 +138,6 @@ void mainboard_romstage_entry(unsigned long bist) console_init(); - report_bist_failure(bist); enable_smbus(); x4x_early_init(); diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index 70a8c1928a..d36971fc39 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -67,7 +67,7 @@ const struct rcba_config_instruction rcba_config[] = { RCBA_END_CONFIG, }; -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -130,7 +130,6 @@ void mainboard_romstage_entry(unsigned long bist) .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], - .bist = bist, }; /* Early SuperIO setup */ diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index ec5d5ea138..3f6d989fd4 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -18,7 +18,7 @@ #include "variant.h" -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { - variant_romstage_entry(bist); + variant_romstage_entry(); } diff --git a/src/mainboard/google/slippy/variant.h b/src/mainboard/google/slippy/variant.h index eec024ed0e..87a228c89c 100644 --- a/src/mainboard/google/slippy/variant.h +++ b/src/mainboard/google/slippy/variant.h @@ -16,6 +16,6 @@ #ifndef VARIANT_H #define VARIANT_H -void variant_romstage_entry(unsigned long bist); +void variant_romstage_entry(void); #endif diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c index 25f8d27ece..1903588816 100644 --- a/src/mainboard/google/slippy/variants/falco/romstage.c +++ b/src/mainboard/google/slippy/variants/falco/romstage.c @@ -105,7 +105,7 @@ static void copy_spd(struct pei_data *peid) } } -void variant_romstage_entry(unsigned long bist) +void variant_romstage_entry(void) { struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -167,7 +167,6 @@ void variant_romstage_entry(unsigned long bist) .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], - .bist = bist, .copy_spd = copy_spd, }; diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index b95c6e1187..3ef8eec5df 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -102,7 +102,7 @@ static void copy_spd(struct pei_data *peid) spd_file + (spd_index * spd_len), spd_len); } -void variant_romstage_entry(unsigned long bist) +void variant_romstage_entry(void) { struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -162,7 +162,6 @@ void variant_romstage_entry(unsigned long bist) .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], - .bist = bist, .copy_spd = copy_spd, }; diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index 37c7853347..71eafc2d7a 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -119,7 +119,7 @@ static void copy_spd(struct pei_data *peid) } } -void variant_romstage_entry(unsigned long bist) +void variant_romstage_entry(void) { struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -179,7 +179,6 @@ void variant_romstage_entry(unsigned long bist) .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], - .bist = bist, .copy_spd = copy_spd, }; diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index 731b35748d..7fcf085455 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -106,7 +106,7 @@ static void copy_spd(struct pei_data *peid) } } -void variant_romstage_entry(unsigned long bist) +void variant_romstage_entry(void) { struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -166,7 +166,6 @@ void variant_romstage_entry(unsigned long bist) .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], - .bist = bist, .copy_spd = copy_spd, }; diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index ab8282c8c9..847cc5f584 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -19,7 +19,6 @@ #include <device/pci_ops.h> #include <console/console.h> #include <cpu/intel/romstage.h> -#include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> #include <device/pci_def.h> #include <device/pnp_def.h> @@ -197,12 +196,11 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0; - if (bist == 0) - enable_lapic(); + enable_lapic(); ich7_enable_lpc(); early_superio_config_w83627ehg(); @@ -210,9 +208,6 @@ void mainboard_romstage_entry(unsigned long bist) /* Set up the console */ console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); system_reset(); diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index b43110bab1..3fd9aab9c7 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -63,7 +63,7 @@ const struct rcba_config_instruction rcba_config[] = { RCBA_END_CONFIG, }; -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -136,7 +136,6 @@ void mainboard_romstage_entry(unsigned long bist) .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], - .bist = bist, .copy_spd = NULL, }; diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 32b9a9feba..15acffb052 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -19,7 +19,6 @@ #include <cpu/x86/lapic.h> #include <superio/smsc/lpc47m15x/lpc47m15x.h> #include <console/console.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> @@ -117,12 +116,11 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0, boot_mode = 0; - if (bist == 0) - enable_lapic(); + enable_lapic(); ich7_enable_lpc(); /* Enable SuperIO PM */ @@ -132,9 +130,6 @@ void mainboard_romstage_entry(unsigned long bist) /* Set up the console */ console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected.\n"); boot_mode = 1; diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c index 2d6e916d5a..ec3e2bfbe6 100644 --- a/src/mainboard/intel/dg41wv/romstage.c +++ b/src/mainboard/intel/dg41wv/romstage.c @@ -19,7 +19,6 @@ #include <device/pci_ops.h> #include <console/console.h> #include <cpu/intel/romstage.h> -#include <cpu/x86/bist.h> #include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/x4x.h> #include <southbridge/intel/common/gpio.h> @@ -75,7 +74,7 @@ static void ich7_enable_lpc(void) pci_write_config32(LPC_DEV, 0x84, 0x00fc0a01); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; @@ -89,7 +88,6 @@ void mainboard_romstage_entry(unsigned long bist) console_init(); - report_bist_failure(bist); enable_smbus(); x4x_early_init(); diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c index c7ef09d8db..db896824cd 100644 --- a/src/mainboard/intel/dg43gt/romstage.c +++ b/src/mainboard/intel/dg43gt/romstage.c @@ -20,7 +20,6 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <superio/winbond/w83627dhg/w83627dhg.h> #include <superio/winbond/common/winbond.h> @@ -68,7 +67,7 @@ static void ich10_enable_lpc(void) pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 }; u8 boot_path = 0; @@ -81,7 +80,6 @@ void mainboard_romstage_entry(unsigned long bist) console_init(); - report_bist_failure(bist); enable_smbus(); x4x_early_init(); diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index c940536a03..0981fe8989 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -18,7 +18,6 @@ #include <delay.h> #include <console/console.h> #include <cpu/intel/romstage.h> -#include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> #include <device/pci_def.h> #include <device/pci_ops.h> @@ -241,12 +240,11 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0; - if (bist == 0) - enable_lapic(); + enable_lapic(); /* Force PCIRST# */ pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); @@ -259,9 +257,6 @@ void mainboard_romstage_entry(unsigned long bist) /* Set up the console */ console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); system_reset(); diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 2817023fcd..243e16112e 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -24,7 +24,6 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> @@ -157,14 +156,13 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0; int dock_err; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 }; - if (bist == 0) - enable_lapic(); + enable_lapic(); ich7_enable_lpc(); @@ -188,9 +186,6 @@ void mainboard_romstage_entry(unsigned long bist) /* Setup the console */ console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); system_reset(); diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c index e41035166c..bbb73dd57c 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c +++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c @@ -20,7 +20,6 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <device/pci_ops.h> #include <superio/smsc/smscsuperio/smscsuperio.h> @@ -60,7 +59,7 @@ static void ich7_enable_lpc(void) pci_write_config32(LPC_DEV, GEN1_DEC, 0x00fc0a01); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; @@ -74,7 +73,6 @@ void mainboard_romstage_entry(unsigned long bist) console_init(); - report_bist_failure(bist); enable_smbus(); x4x_early_init(); diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 73f5bccf92..067528b87b 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -23,7 +23,6 @@ #include <cpu/x86/lapic.h> #include <romstage_handoff.h> #include <console/console.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <ec/acpi/ec.h> #include <timestamp.h> @@ -167,14 +166,12 @@ static void set_fsb_frequency(void) smbus_block_write(0x69, 0, 5, block); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { u32 reg32; int s3resume = 0; const u8 spd_addrmap[4] = { 0x50, 0, 0x51, 0 }; - - if (bist == 0) - enable_lapic(); + enable_lapic(); nehalem_early_initialization(NEHALEM_MOBILE); @@ -197,9 +194,6 @@ void mainboard_romstage_entry(unsigned long bist) console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - /* Read PM1_CNT */ reg32 = inl(DEFAULT_PMBASE + 0x04); printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 590e7864b4..2b8a9badba 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -25,7 +25,6 @@ #include <cpu/x86/lapic.h> #include <arch/acpi.h> #include <console/console.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> @@ -157,13 +156,12 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 }; - if (bist == 0) - enable_lapic(); + enable_lapic(); /* Enable GPIOs */ pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); @@ -190,9 +188,6 @@ void mainboard_romstage_entry(unsigned long bist) else printk(BIOS_DEBUG, "Dock is not present\n"); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "Soft reset detected, rebooting properly.\n"); diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 4c487c0df5..8946179c4a 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -24,7 +24,6 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> @@ -157,14 +156,13 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0; int dock_err; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 }; - if (bist == 0) - enable_lapic(); + enable_lapic(); ich7_enable_lpc(); @@ -188,9 +186,6 @@ void mainboard_romstage_entry(unsigned long bist) /* Setup the console */ console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); system_reset(); diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index e2c5133c5c..a4d598f93f 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -23,7 +23,6 @@ #include <cpu/x86/lapic.h> #include <romstage_handoff.h> #include <console/console.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <ec/acpi/ec.h> #include <timestamp.h> @@ -159,7 +158,7 @@ static inline u16 read_acpi16(u32 addr) } #endif -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { u32 reg32; int s3resume = 0; @@ -169,8 +168,7 @@ void mainboard_romstage_entry(unsigned long bist) outb(4, 0x61); outb(0, 0x61); - if (bist == 0) - enable_lapic(); + enable_lapic(); nehalem_early_initialization(NEHALEM_MOBILE); @@ -196,9 +194,6 @@ void mainboard_romstage_entry(unsigned long bist) console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - /* Read PM1_CNT */ reg32 = inl(DEFAULT_PMBASE + 0x04); printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 02ee004250..196f0a510f 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -24,7 +24,6 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> @@ -204,12 +203,11 @@ static void init_artec_dongle(void) outb(0xf4, 0x88); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0; - if (bist == 0) - enable_lapic(); + enable_lapic(); /* Force PCIRST# */ pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); @@ -222,9 +220,6 @@ void mainboard_romstage_entry(unsigned long bist) /* Set up the console */ console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); system_reset(); diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index e43302af24..228bcb581e 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -38,7 +38,7 @@ static const struct rcba_config_instruction rcba_config[] = { RCBA_END_CONFIG, }; -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -92,7 +92,6 @@ void mainboard_romstage_entry(unsigned long bist) .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = rcba_config, - .bist = bist, }; romstage_common(&romstage_params); |