diff options
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/deltaur/dsdt.asl | 3 | ||||
| -rw-r--r-- | src/mainboard/google/drallion/dsdt.asl | 3 | ||||
| -rw-r--r-- | src/mainboard/google/hatch/dsdt.asl | 3 | ||||
| -rw-r--r-- | src/mainboard/google/sarien/dsdt.asl | 3 | ||||
| -rw-r--r-- | src/mainboard/google/volteer/dsdt.asl | 4 |
5 files changed, 0 insertions, 16 deletions
diff --git a/src/mainboard/google/deltaur/dsdt.asl b/src/mainboard/google/deltaur/dsdt.asl index 206119f380..1bca44f26f 100644 --- a/src/mainboard/google/deltaur/dsdt.asl +++ b/src/mainboard/google/deltaur/dsdt.asl @@ -35,9 +35,6 @@ DefinitionBlock( /* VPD support */ #include <vendorcode/google/chromeos/acpi/vpd.asl> - /* Low power idle table */ - #include <soc/intel/common/acpi/lpit.asl> - /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index a6abdb86ad..92fa2b8318 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -39,9 +39,6 @@ DefinitionBlock( #include <southbridge/intel/common/acpi/sleepstates.asl> - /* Low power idle table */ - #include <soc/intel/common/acpi/lpit.asl> - /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index d2170d0eca..1395c8f204 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -36,9 +36,6 @@ DefinitionBlock( #include <southbridge/intel/common/acpi/sleepstates.asl> - /* Low power idle table */ - #include <soc/intel/common/acpi/lpit.asl> - /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index 98aa54a808..664305eeef 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -39,9 +39,6 @@ DefinitionBlock( #include <southbridge/intel/common/acpi/sleepstates.asl> - /* Low power idle table */ - #include <soc/intel/common/acpi/lpit.asl> - #if CONFIG(EC_GOOGLE_WILCO) /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index cf733676e3..ba9541ee5d 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -38,10 +38,6 @@ DefinitionBlock( // Chrome OS specific #include <vendorcode/google/chromeos/acpi/chromeos.asl> - /* Include Low power idle table for a short term workaround to enable - S0ix. Once cr50 pulse width is fixed, this can be removed. */ - #include <soc/intel/common/acpi/lpit.asl> - // Chrome OS Embedded Controller Scope (\_SB.PCI0.LPCB) { |