summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/lenovo/t520/Makefile.inc1
-rw-r--r--src/mainboard/lenovo/t520/gpio.c (renamed from src/mainboard/lenovo/t520/gpio.h)2
-rw-r--r--src/mainboard/lenovo/t520/romstage.c107
-rw-r--r--src/mainboard/lenovo/t530/Makefile.inc1
-rw-r--r--src/mainboard/lenovo/t530/gpio.c (renamed from src/mainboard/lenovo/t530/gpio.h)2
-rw-r--r--src/mainboard/lenovo/t530/romstage.c116
-rw-r--r--src/mainboard/lenovo/x220/Makefile.inc1
-rw-r--r--src/mainboard/lenovo/x220/gpio.c (renamed from src/mainboard/lenovo/x220/gpio.h)2
-rw-r--r--src/mainboard/lenovo/x220/romstage.c103
-rw-r--r--src/mainboard/lenovo/x230/Makefile.inc1
-rw-r--r--src/mainboard/lenovo/x230/gpio.c (renamed from src/mainboard/lenovo/x230/gpio.h)2
-rw-r--r--src/mainboard/lenovo/x230/romstage.c103
12 files changed, 90 insertions, 351 deletions
diff --git a/src/mainboard/lenovo/t520/Makefile.inc b/src/mainboard/lenovo/t520/Makefile.inc
index d514d4b9f9..265059ae9f 100644
--- a/src/mainboard/lenovo/t520/Makefile.inc
+++ b/src/mainboard/lenovo/t520/Makefile.inc
@@ -18,3 +18,4 @@
##
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+romstage-y += gpio.c
diff --git a/src/mainboard/lenovo/t520/gpio.h b/src/mainboard/lenovo/t520/gpio.c
index 562259a255..a9b0f9e08a 100644
--- a/src/mainboard/lenovo/t520/gpio.h
+++ b/src/mainboard/lenovo/t520/gpio.c
@@ -287,7 +287,7 @@ const struct pch_gpio_set3 pch_gpio_set3_level = {
.gpio75 = GPIO_LEVEL_HIGH,
};
-const struct pch_gpio_map t520_gpio_map = {
+const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c
index 4d1684d896..83be0c7f86 100644
--- a/src/mainboard/lenovo/t520/romstage.c
+++ b/src/mainboard/lenovo/t520/romstage.c
@@ -37,12 +37,10 @@
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/bd82x6x/gpio.h>
#include <arch/cpu.h>
-#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <cbfs.h>
-#include "gpio.h"
-static void pch_enable_lpc(void)
+void pch_enable_lpc(void)
{
/* T520 EC Decode Range Port60/64, Port62/66 */
/* Enable EC, PS/2 Keyboard/Mouse */
@@ -60,7 +58,7 @@ static void pch_enable_lpc(void)
0x80010000);
}
-static void rcba_config(void)
+void rcba_config(void)
{
/*
* GFX INTA -> PIRQA (MSI)
@@ -109,85 +107,24 @@ static void rcba_config(void)
RCBA32(BUC) = 0;
}
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
-{
- int s3resume = 0;
- spd_raw_data spd[4];
-
- if (MCHBAR16(SSKPD) == 0xCAFE) {
- outb(0x6, 0xcf9);
- hlt ();
- }
-
- timestamp_init(get_initial_timestamp());
- timestamp_add_now(TS_START_ROMSTAGE);
-
- if (bist == 0)
- enable_lapic();
-
- pch_enable_lpc();
-
- /* Enable GPIOs */
- pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
- pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
-
- setup_pch_gpios(&t520_gpio_map);
-
- early_usb_init((struct southbridge_usb_port []) {
- { 1, 1, 0 }, /* P0 left dual conn, OC 0 */
- { 1, 1, 1 }, /* P1 system onboard USB port (eSATA), (EHCI debug), OC 1 */
- { 1, 2, -1 }, /* P2: wimax / WLAN */
- { 1, 1, -1 }, /* P3: WWAN, no OC */
- { 1, 1, -1 }, /* P4: smartcard, no OC */
- { 1, 1, -1 }, /* P5: ExpressCard, no OC */
- { 0, 2, -1 }, /* P6: empty */
- { 0, 2, -1 }, /* P7: to touch panel, no OC */
- { 1, 1, 4 }, /* P8: left dual conn, OC4 */
- { 1, 4, 5 }, /* P9: to system subcard back right, (EHCI debug), OC 5 */
- { 1, 1, -1 }, /* P10: fingerprint reader, no OC */
- { 1, 2, -1 }, /* P11: bluetooth, no OC. */
- { 1, 1, -1 }, /* P12: docking, no OC */
- { 1, 1, -1 }, /* P13: CAMERA (LCD), no OC */
- });
-
- /* Initialize console device(s) */
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- /* Perform some early chipset initialization required
- * before RAM initialization can work
- */
- sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
- printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
-
- s3resume = southbridge_detect_s3_resume();
-
- post_code(0x38);
- /* Enable SPD ROMs and DDR-III DRAM */
- enable_smbus();
-
- post_code(0x39);
-
- post_code(0x3a);
- timestamp_add_now(TS_BEFORE_INITRAM);
-
- memset(spd, 0, sizeof(spd));
- read_spd(&spd[0], 0x50);
- read_spd(&spd[2], 0x51);
-
- init_dram_ddr3(spd, 1, TCK_800MHZ, s3resume);
-
- timestamp_add_now(TS_AFTER_INITRAM);
- post_code(0x3c);
-
- rcba_config();
- post_code(0x3d);
-
- northbridge_romstage_finalize(s3resume);
-
- post_code(0x3f);
- timestamp_add_now(TS_END_ROMSTAGE);
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 }, /* P0 left dual conn, OC 0 */
+ { 1, 1, 1 }, /* P1 system onboard USB port (eSATA), (EHCI debug), OC 1 */
+ { 1, 2, -1 }, /* P2: wimax / WLAN */
+ { 1, 1, -1 }, /* P3: WWAN, no OC */
+ { 1, 1, -1 }, /* P4: smartcard, no OC */
+ { 1, 1, -1 }, /* P5: ExpressCard, no OC */
+ { 0, 2, -1 }, /* P6: empty */
+ { 0, 2, -1 }, /* P7: to touch panel, no OC */
+ { 1, 1, 4 }, /* P8: left dual conn, OC4 */
+ { 1, 4, 5 }, /* P9: to system subcard back right, (EHCI debug), OC 5 */
+ { 1, 1, -1 }, /* P10: fingerprint reader, no OC */
+ { 1, 2, -1 }, /* P11: bluetooth, no OC. */
+ { 1, 1, -1 }, /* P12: docking, no OC */
+ { 1, 1, -1 }, /* P13: CAMERA (LCD), no OC */
+};
+
+void mainboard_get_spd(spd_raw_data *spd) {
+ read_spd (&spd[0], 0x50);
+ read_spd (&spd[2], 0x51);
}
diff --git a/src/mainboard/lenovo/t530/Makefile.inc b/src/mainboard/lenovo/t530/Makefile.inc
index d514d4b9f9..265059ae9f 100644
--- a/src/mainboard/lenovo/t530/Makefile.inc
+++ b/src/mainboard/lenovo/t530/Makefile.inc
@@ -18,3 +18,4 @@
##
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+romstage-y += gpio.c
diff --git a/src/mainboard/lenovo/t530/gpio.h b/src/mainboard/lenovo/t530/gpio.c
index 9668b58ea0..32e0e1732a 100644
--- a/src/mainboard/lenovo/t530/gpio.h
+++ b/src/mainboard/lenovo/t530/gpio.c
@@ -324,7 +324,7 @@ const struct pch_gpio_set3 pch_gpio_set3_level = {
.gpio75 = GPIO_LEVEL_HIGH,
};
-const struct pch_gpio_map t530_gpio_map = {
+const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c
index ad2ae644d9..115f83bdbc 100644
--- a/src/mainboard/lenovo/t530/romstage.c
+++ b/src/mainboard/lenovo/t530/romstage.c
@@ -20,30 +20,14 @@
*/
#include <stdint.h>
-#include <string.h>
-#include <lib.h>
-#include <timestamp.h>
#include <arch/byteorder.h>
#include <arch/io.h>
#include <device/pci_def.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <arch/acpi.h>
-#include <cbmem.h>
#include <console/console.h>
-#include "northbridge/intel/sandybridge/sandybridge.h"
#include "northbridge/intel/sandybridge/raminit_native.h"
#include "southbridge/intel/bd82x6x/pch.h"
-#include "southbridge/intel/bd82x6x/gpio.h"
-#include <arch/cpu.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/msr.h>
-#include "gpio.h"
-#include <cbfs.h>
-#include <cpu/intel/romstage.h>
-static void pch_enable_lpc(void)
+void pch_enable_lpc(void)
{
/* X230 EC Decode Range Port60/64, Port62/66 */
/* Enable EC, PS/2 Keyboard/Mouse */
@@ -61,7 +45,7 @@ static void pch_enable_lpc(void)
0x80010000);
}
-static void rcba_config(void)
+void rcba_config(void)
{
/*
* GFX INTA -> PIRQA (MSI)
@@ -110,84 +94,24 @@ static void rcba_config(void)
RCBA32(BUC) = 0;
}
-void main(unsigned long bist)
-{
- int s3resume = 0;
- spd_raw_data spd[4];
-
- if (MCHBAR16(SSKPD) == 0xCAFE) {
- outb(0x6, 0xcf9);
- hlt ();
- }
-
- timestamp_init(get_initial_timestamp());
- timestamp_add_now(TS_START_ROMSTAGE);
-
- if (bist == 0)
- enable_lapic();
-
- pch_enable_lpc();
-
- /* Enable GPIOs */
- pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
- pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
-
- setup_pch_gpios(&t530_gpio_map);
-
- early_usb_init((struct southbridge_usb_port []) {
- { 1, 1, 0 },
- { 1, 1, 1 },
- { 1, 2, 3 },
- { 1, 1, -1 },
- { 1, 1, -1 },
- { 1, 0, -1 },
- { 0, 0, -1 },
- { 1, 2, -1 },
- { 1, 0, -1 },
- { 1, 1, 5 },
- { 1, 0, -1 },
- { 1, 0, -1 },
- { 1, 3, -1 },
- { 1, 1, -1 },
- });
-
- /* Initialize console device(s) */
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- /* Perform some early chipset initialization required
- * before RAM initialization can work
- */
- sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
- printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
-
- s3resume = southbridge_detect_s3_resume();
-
- post_code(0x38);
- /* Enable SPD ROMs and DDR-III DRAM */
- enable_smbus();
-
- post_code(0x39);
-
- post_code(0x3a);
- timestamp_add_now(TS_BEFORE_INITRAM);
-
- memset (spd, 0, sizeof (spd));
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 2, 3 },
+ { 1, 1, -1 },
+ { 1, 1, -1 },
+ { 1, 0, -1 },
+ { 0, 0, -1 },
+ { 1, 2, -1 },
+ { 1, 0, -1 },
+ { 1, 1, 5 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 3, -1 },
+ { 1, 1, -1 },
+};
+
+void mainboard_get_spd(spd_raw_data *spd) {
read_spd (&spd[0], 0x50);
read_spd (&spd[2], 0x51);
-
- init_dram_ddr3 (spd, 1, TCK_800MHZ, s3resume);
-
- timestamp_add_now(TS_AFTER_INITRAM);
- post_code(0x3c);
-
- rcba_config();
- post_code(0x3d);
-
- northbridge_romstage_finalize(s3resume);
-
- post_code(0x3f);
- timestamp_add_now(TS_END_ROMSTAGE);
}
diff --git a/src/mainboard/lenovo/x220/Makefile.inc b/src/mainboard/lenovo/x220/Makefile.inc
index d514d4b9f9..265059ae9f 100644
--- a/src/mainboard/lenovo/x220/Makefile.inc
+++ b/src/mainboard/lenovo/x220/Makefile.inc
@@ -18,3 +18,4 @@
##
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+romstage-y += gpio.c
diff --git a/src/mainboard/lenovo/x220/gpio.h b/src/mainboard/lenovo/x220/gpio.c
index 59e00c91f7..83a0db30db 100644
--- a/src/mainboard/lenovo/x220/gpio.h
+++ b/src/mainboard/lenovo/x220/gpio.c
@@ -359,7 +359,7 @@ static const struct pch_gpio_set3 pch_gpio_set3_level = {
.gpio75 = GPIO_LEVEL_HIGH,
};
-static const struct pch_gpio_map x220_gpio_map = {
+const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c
index a516ee617c..ba48fac574 100644
--- a/src/mainboard/lenovo/x220/romstage.c
+++ b/src/mainboard/lenovo/x220/romstage.c
@@ -35,11 +35,9 @@
#include "southbridge/intel/bd82x6x/pch.h"
#include "southbridge/intel/bd82x6x/gpio.h"
#include <arch/cpu.h>
-#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
-#include "gpio.h"
-static void pch_enable_lpc(void)
+void pch_enable_lpc(void)
{
/* X230 EC Decode Range Port60/64, Port62/66 */
/* Enable EC, PS/2 Keyboard/Mouse */
@@ -57,7 +55,7 @@ static void pch_enable_lpc(void)
0x80010000);
}
-static void rcba_config(void)
+void rcba_config(void)
{
/*
* GFX INTA -> PIRQA (MSI)
@@ -106,85 +104,24 @@ static void rcba_config(void)
RCBA32(BUC) = 0;
}
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
-{
- int s3resume = 0;
- spd_raw_data spd[4];
-
- if (MCHBAR16(SSKPD) == 0xCAFE) {
- outb(0x6, 0xcf9);
- hlt ();
- }
-
- timestamp_init(get_initial_timestamp());
- timestamp_add_now(TS_START_ROMSTAGE);
-
- if (bist == 0)
- enable_lapic();
-
- pch_enable_lpc();
-
- /* Enable GPIOs */
- pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
- pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
-
- setup_pch_gpios(&x220_gpio_map);
-
- early_usb_init((struct southbridge_usb_port []) {
- { 1, 0, 0 },
- { 1, 1, 1 },
- { 1, 1, 3 },
- { 1, 1, 3 },
- { 1, 1, -1 },
- { 1, 1, -1 },
- { 1, 0, 2 },
- { 1, 0, 2 },
- { 1, 1, 6 },
- { 1, 1, 5 },
- { 1, 1, 6 },
- { 1, 1, 6 },
- { 1, 1, 7 },
- { 1, 1, 6 },
- });
-
- /* Initialize console device(s) */
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- /* Perform some early chipset initialization required
- * before RAM initialization can work
- */
- sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
- printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
-
- s3resume = southbridge_detect_s3_resume();
-
- post_code(0x38);
- /* Enable SPD ROMs and DDR-III DRAM */
- enable_smbus();
-
- post_code(0x39);
-
- post_code(0x3a);
- timestamp_add_now(TS_BEFORE_INITRAM);
-
- memset (spd, 0, sizeof (spd));
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 0, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 3 },
+ { 1, 1, 3 },
+ { 1, 1, -1 },
+ { 1, 1, -1 },
+ { 1, 0, 2 },
+ { 1, 0, 2 },
+ { 1, 1, 6 },
+ { 1, 1, 5 },
+ { 1, 1, 6 },
+ { 1, 1, 6 },
+ { 1, 1, 7 },
+ { 1, 1, 6 },
+};
+
+void mainboard_get_spd(spd_raw_data *spd) {
read_spd (&spd[0], 0x50);
read_spd (&spd[2], 0x51);
-
- init_dram_ddr3 (spd, 1, TCK_800MHZ, s3resume);
-
- timestamp_add_now(TS_AFTER_INITRAM);
- post_code(0x3c);
-
- rcba_config();
- post_code(0x3d);
-
- northbridge_romstage_finalize(s3resume);
-
- post_code(0x3f);
- timestamp_add_now(TS_END_ROMSTAGE);
}
diff --git a/src/mainboard/lenovo/x230/Makefile.inc b/src/mainboard/lenovo/x230/Makefile.inc
index d514d4b9f9..265059ae9f 100644
--- a/src/mainboard/lenovo/x230/Makefile.inc
+++ b/src/mainboard/lenovo/x230/Makefile.inc
@@ -18,3 +18,4 @@
##
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+romstage-y += gpio.c
diff --git a/src/mainboard/lenovo/x230/gpio.h b/src/mainboard/lenovo/x230/gpio.c
index f0a32a8955..cacc90f5eb 100644
--- a/src/mainboard/lenovo/x230/gpio.h
+++ b/src/mainboard/lenovo/x230/gpio.c
@@ -284,7 +284,7 @@ const struct pch_gpio_set3 pch_gpio_set3_level = {
.gpio75 = GPIO_LEVEL_HIGH,
};
-const struct pch_gpio_map x230_gpio_map = {
+const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c
index c2a0ae7af7..2c39741770 100644
--- a/src/mainboard/lenovo/x230/romstage.c
+++ b/src/mainboard/lenovo/x230/romstage.c
@@ -37,12 +37,10 @@
#include "southbridge/intel/bd82x6x/pch.h"
#include "southbridge/intel/bd82x6x/gpio.h"
#include <arch/cpu.h>
-#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
-#include "gpio.h"
#include <cbfs.h>
-static void pch_enable_lpc(void)
+void pch_enable_lpc(void)
{
/* X230 EC Decode Range Port60/64, Port62/66 */
/* Enable EC, PS/2 Keyboard/Mouse */
@@ -60,7 +58,7 @@ static void pch_enable_lpc(void)
0x80010000);
}
-static void rcba_config(void)
+void rcba_config(void)
{
/*
* GFX INTA -> PIRQA (MSI)
@@ -109,85 +107,24 @@ static void rcba_config(void)
RCBA32(BUC) = 0;
}
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
-{
- int s3resume = 0;
- spd_raw_data spd[4];
-
- if (MCHBAR16(SSKPD) == 0xCAFE) {
- outb(0x6, 0xcf9);
- hlt ();
- }
-
- timestamp_init(get_initial_timestamp());
- timestamp_add_now(TS_START_ROMSTAGE);
-
- if (bist == 0)
- enable_lapic();
-
- pch_enable_lpc();
-
- /* Enable GPIOs */
- pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
- pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
-
- setup_pch_gpios(&x230_gpio_map);
-
- early_usb_init((struct southbridge_usb_port []) {
- { 1, 0, 0 }, /* P0 (left, fan side), OC 0 */
- { 1, 0, 1 }, /* P1 (left touchpad side), OC 1 */
- { 1, 1, 3 }, /* P2: dock, OC 3 */
- { 1, 1, -1 }, /* P3: wwan, no OC */
- { 1, 1, -1 }, /* P4: Wacom tablet on X230t, otherwise empty */
- { 1, 1, -1 }, /* P5: Expresscard, no OC */
- { 0, 0, -1 }, /* P6: Empty */
- { 1, 2, -1 }, /* P7: dock, no OC */
- { 1, 0, -1 },
- { 1, 2, 5 }, /* P9: Right (EHCI debug), OC 5 */
- { 1, 1, -1 }, /* P10: fingerprint reader, no OC */
- { 1, 1, -1 }, /* P11: bluetooth, no OC. */
- { 1, 1, -1 }, /* P12: wlan, no OC */
- { 1, 1, -1 }, /* P13: webcam, no OC */
- });
-
- /* Initialize console device(s) */
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- /* Perform some early chipset initialization required
- * before RAM initialization can work
- */
- sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
- printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
-
- s3resume = southbridge_detect_s3_resume();
-
- post_code(0x38);
- /* Enable SPD ROMs and DDR-III DRAM */
- enable_smbus();
-
- post_code(0x39);
-
- post_code(0x3a);
- timestamp_add_now(TS_BEFORE_INITRAM);
-
- memset (spd, 0, sizeof (spd));
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 0, 0 }, /* P0 (left, fan side), OC 0 */
+ { 1, 0, 1 }, /* P1 (left touchpad side), OC 1 */
+ { 1, 1, 3 }, /* P2: dock, OC 3 */
+ { 1, 1, -1 }, /* P3: wwan, no OC */
+ { 1, 1, -1 }, /* P4: Wacom tablet on X230t, otherwise empty */
+ { 1, 1, -1 }, /* P5: Expresscard, no OC */
+ { 0, 0, -1 }, /* P6: Empty */
+ { 1, 2, -1 }, /* P7: dock, no OC */
+ { 1, 0, -1 },
+ { 1, 2, 5 }, /* P9: Right (EHCI debug), OC 5 */
+ { 1, 1, -1 }, /* P10: fingerprint reader, no OC */
+ { 1, 1, -1 }, /* P11: bluetooth, no OC. */
+ { 1, 1, -1 }, /* P12: wlan, no OC */
+ { 1, 1, -1 }, /* P13: webcam, no OC */
+};
+
+void mainboard_get_spd(spd_raw_data *spd) {
read_spd (&spd[0], 0x50);
read_spd (&spd[2], 0x51);
-
- init_dram_ddr3 (spd, 1, TCK_800MHZ, s3resume);
-
- timestamp_add_now(TS_AFTER_INITRAM);
- post_code(0x3c);
-
- rcba_config();
- post_code(0x3d);
-
- northbridge_romstage_finalize(s3resume);
-
- post_code(0x3f);
- timestamp_add_now(TS_END_ROMSTAGE);
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 02:34:53 +0000