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-rw-r--r--src/mainboard/intel/glkrvp/smihandler.c5
-rw-r--r--src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h4
2 files changed, 9 insertions, 0 deletions
diff --git a/src/mainboard/intel/glkrvp/smihandler.c b/src/mainboard/intel/glkrvp/smihandler.c
index afaf9f977d..c08fef9e32 100644
--- a/src/mainboard/intel/glkrvp/smihandler.c
+++ b/src/mainboard/intel/glkrvp/smihandler.c
@@ -50,3 +50,8 @@ int mainboard_smi_apmc(u8 apmc)
MAINBOARD_EC_SMI_EVENTS);
return 0;
}
+
+void mainboard_smi_espi_handler(void)
+{
+ chromeec_smi_process_events();
+}
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
index 41de87c7ce..dc23abd2fc 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
@@ -22,7 +22,11 @@
* GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0
* which is North community
*/
+#if IS_ENABLED(CONFIG_SOC_ESPI)
+#define EC_SCI_GPI GPE0A_ESPI_SCI_STS
+#else
#define EC_SCI_GPI GPE0_DW1_05
+#endif
/* EC SMI */
#define EC_SMI_GPI GPIO_41