diff options
Diffstat (limited to 'src/mainboard')
-rw-r--r-- | src/mainboard/asus/mew-am/Kconfig | 1 | ||||
-rw-r--r-- | src/mainboard/asus/mew-am/romstage.c | 20 | ||||
-rw-r--r-- | src/mainboard/asus/mew-vm/Kconfig | 1 | ||||
-rw-r--r-- | src/mainboard/asus/mew-vm/romstage.c | 24 | ||||
-rw-r--r-- | src/mainboard/ecs/p6iwp-fe/Kconfig | 1 | ||||
-rw-r--r-- | src/mainboard/ecs/p6iwp-fe/romstage.c | 22 | ||||
-rw-r--r-- | src/mainboard/hp/e_vectra_p2706t/Kconfig | 1 | ||||
-rw-r--r-- | src/mainboard/hp/e_vectra_p2706t/romstage.c | 14 | ||||
-rw-r--r-- | src/mainboard/intel/d810e2cb/romstage.c | 14 | ||||
-rw-r--r-- | src/mainboard/mitac/6513wu/Kconfig | 1 | ||||
-rw-r--r-- | src/mainboard/mitac/6513wu/romstage.c | 20 | ||||
-rw-r--r-- | src/mainboard/msi/ms6178/Kconfig | 1 | ||||
-rw-r--r-- | src/mainboard/msi/ms6178/romstage.c | 10 | ||||
-rw-r--r-- | src/mainboard/nec/powermate2000/Kconfig | 1 | ||||
-rw-r--r-- | src/mainboard/nec/powermate2000/romstage.c | 13 |
15 files changed, 24 insertions, 120 deletions
diff --git a/src/mainboard/asus/mew-am/Kconfig b/src/mainboard/asus/mew-am/Kconfig index afe6a0dee3..68ac160b33 100644 --- a/src/mainboard/asus/mew-am/Kconfig +++ b/src/mainboard/asus/mew-am/Kconfig @@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_SMSC_SMSCSUPERIO - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 diff --git a/src/mainboard/asus/mew-am/romstage.c b/src/mainboard/asus/mew-am/romstage.c index 51d97a37dc..402789c0af 100644 --- a/src/mainboard/asus/mew-am/romstage.c +++ b/src/mainboard/asus/mew-am/romstage.c @@ -26,31 +26,21 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "northbridge/intel/i82810/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" - -#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) - -static inline int spd_read_byte(unsigned int device, unsigned int address) -{ - return smbus_read_byte(device, address); -} - #include "northbridge/intel/i82810/raminit.c" /* #include "northbridge/intel/i82810/debug.c" */ +#include <lib.h> -static void main(unsigned long bist) -{ - if (bist == 0) - early_mtrr_init(); +#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) +void main(unsigned long bist) +{ smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -60,6 +50,4 @@ static void main(unsigned long bist) sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } - diff --git a/src/mainboard/asus/mew-vm/Kconfig b/src/mainboard/asus/mew-vm/Kconfig index bc952dccbd..4e461923ad 100644 --- a/src/mainboard/asus/mew-vm/Kconfig +++ b/src/mainboard/asus/mew-vm/Kconfig @@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_SMSC_LPC47B272 - select ROMCC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select UDELAY_TSC diff --git a/src/mainboard/asus/mew-vm/romstage.c b/src/mainboard/asus/mew-vm/romstage.c index 30d6a87214..e4c551eb60 100644 --- a/src/mainboard/asus/mew-vm/romstage.c +++ b/src/mainboard/asus/mew-vm/romstage.c @@ -26,42 +26,28 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "superio/smsc/lpc47b272/lpc47b272_early_serial.c" #include "northbridge/intel/i82810/raminit.h" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" - -#define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1) - #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "northbridge/intel/i82810/raminit.c" #include "northbridge/intel/i82810/debug.c" +#include <lib.h> -static void main(unsigned long bist) -{ - if (bist == 0) - early_mtrr_init(); +#define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1) +void main(unsigned long bist) +{ lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); - enable_smbus(); - - /* Halt if there was a built in self test failure. */ report_bist_failure(bist); - - /* dump_spd_registers(); */ - + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - - /* Check RAM. */ - /* ram_check(0, 640 * 1024); */ } - diff --git a/src/mainboard/ecs/p6iwp-fe/Kconfig b/src/mainboard/ecs/p6iwp-fe/Kconfig index eecae4d4bd..7d377f4717 100644 --- a/src/mainboard/ecs/p6iwp-fe/Kconfig +++ b/src/mainboard/ecs/p6iwp-fe/Kconfig @@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_ITE_IT8712F - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 diff --git a/src/mainboard/ecs/p6iwp-fe/romstage.c b/src/mainboard/ecs/p6iwp-fe/romstage.c index f84ff465c9..b899d938af 100644 --- a/src/mainboard/ecs/p6iwp-fe/romstage.c +++ b/src/mainboard/ecs/p6iwp-fe/romstage.c @@ -27,37 +27,21 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "northbridge/intel/i82810/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "superio/ite/it8712f/it8712f_early_serial.c" - -static inline int spd_read_byte(unsigned int device, unsigned int address) -{ - return smbus_read_byte(device, address); -} - #include "northbridge/intel/i82810/raminit.c" #include "northbridge/intel/i82810/debug.c" +#include <lib.h> -/* Early mainboard specific GPIO setup. */ -static void mb_gpio_init(void) +void main(unsigned long bist) { -} - -static void main(unsigned long bist) -{ - if (bist == 0) - early_mtrr_init(); - it8712f_24mhz_clkin(); it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter - mb_gpio_init(); uart_init(); console_init(); report_bist_failure(bist); @@ -67,6 +51,4 @@ static void main(unsigned long bist) sdram_set_spd_registers(); sdram_enable(); dump_spd_registers(); - /* ram_check(0, 640 * 1024); */ } - diff --git a/src/mainboard/hp/e_vectra_p2706t/Kconfig b/src/mainboard/hp/e_vectra_p2706t/Kconfig index 7186dae605..5fab95a2c6 100644 --- a/src/mainboard/hp/e_vectra_p2706t/Kconfig +++ b/src/mainboard/hp/e_vectra_p2706t/Kconfig @@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_NSC_PC87360 - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 diff --git a/src/mainboard/hp/e_vectra_p2706t/romstage.c b/src/mainboard/hp/e_vectra_p2706t/romstage.c index 50f59df2ba..39cb2669c0 100644 --- a/src/mainboard/hp/e_vectra_p2706t/romstage.c +++ b/src/mainboard/hp/e_vectra_p2706t/romstage.c @@ -26,40 +26,30 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" /* TODO: It's a PC87364 actually! */ #include "superio/nsc/pc87360/pc87360_early_serial.c" /* TODO: It's i810E actually! */ #include "northbridge/intel/i82810/raminit.h" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "pc80/udelay_io.c" #include "lib/debug.c" #include "northbridge/intel/i82810/raminit.c" +#include <lib.h> /* TODO: It's a PC87364 actually! */ #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1) -static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - /* TODO: It's a PC87364 actually! */ pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - uart_init(); console_init(); - enable_smbus(); - report_bist_failure(bist); - /* dump_spd_registers(); */ sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } - diff --git a/src/mainboard/intel/d810e2cb/romstage.c b/src/mainboard/intel/d810e2cb/romstage.c index 34371f5834..94f1170534 100644 --- a/src/mainboard/intel/d810e2cb/romstage.c +++ b/src/mainboard/intel/d810e2cb/romstage.c @@ -35,21 +35,15 @@ #include "cpu/x86/bist.h" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "gpio.c" +#include "northbridge/intel/i82810/raminit.c" +/* #include "northbridge/intel/i82810/debug.c" */ #include <lib.h> #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) -static inline int spd_read_byte(unsigned int device, unsigned int address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/i82810/raminit.c" -/* #include "northbridge/intel/i82810/debug.c" */ - void main(unsigned long bist) { - /* Set southbridge and superio gpios */ + /* Set southbridge and Super I/O GPIOs. */ mb_gpio_init(); smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); @@ -62,6 +56,4 @@ void main(unsigned long bist) sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } - diff --git a/src/mainboard/mitac/6513wu/Kconfig b/src/mainboard/mitac/6513wu/Kconfig index 77ed6e9153..fac565e97d 100644 --- a/src/mainboard/mitac/6513wu/Kconfig +++ b/src/mainboard/mitac/6513wu/Kconfig @@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_SMSC_SMSCSUPERIO - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 diff --git a/src/mainboard/mitac/6513wu/romstage.c b/src/mainboard/mitac/6513wu/romstage.c index bbf87568c6..1a2d7c4f0c 100644 --- a/src/mainboard/mitac/6513wu/romstage.c +++ b/src/mainboard/mitac/6513wu/romstage.c @@ -26,31 +26,21 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "northbridge/intel/i82810/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" - -#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) - -static inline int spd_read_byte(unsigned int device, unsigned int address) -{ - return smbus_read_byte(device, address); -} - #include "northbridge/intel/i82810/raminit.c" /* #include "northbridge/intel/i82810/debug.c" */ +#include <lib.h> -static void main(unsigned long bist) -{ - if (bist == 0) - early_mtrr_init(); +#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) +void main(unsigned long bist) +{ smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -61,6 +51,4 @@ static void main(unsigned long bist) sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } - diff --git a/src/mainboard/msi/ms6178/Kconfig b/src/mainboard/msi/ms6178/Kconfig index fc8f425d29..4b6d4e46df 100644 --- a/src/mainboard/msi/ms6178/Kconfig +++ b/src/mainboard/msi/ms6178/Kconfig @@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_WINBOND_W83627HF - select ROMCC select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_512 select HAVE_MAINBOARD_RESOURCES diff --git a/src/mainboard/msi/ms6178/romstage.c b/src/mainboard/msi/ms6178/romstage.c index 6d25c4d2e7..5aab983c57 100644 --- a/src/mainboard/msi/ms6178/romstage.c +++ b/src/mainboard/msi/ms6178/romstage.c @@ -26,23 +26,19 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/intel/i82810/raminit.h" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "pc80/udelay_io.c" #include "lib/debug.c" #include "northbridge/intel/i82810/raminit.c" +#include <lib.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - /* FIXME */ outb(0x87, 0x2e); outb(0x87, 0x2e); @@ -61,6 +57,4 @@ static void main(unsigned long bist) sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } - diff --git a/src/mainboard/nec/powermate2000/Kconfig b/src/mainboard/nec/powermate2000/Kconfig index d0f29bb255..55050c0001 100644 --- a/src/mainboard/nec/powermate2000/Kconfig +++ b/src/mainboard/nec/powermate2000/Kconfig @@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_SMSC_SMSCSUPERIO - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 diff --git a/src/mainboard/nec/powermate2000/romstage.c b/src/mainboard/nec/powermate2000/romstage.c index b9a3744e3c..8f71cc9d4b 100644 --- a/src/mainboard/nec/powermate2000/romstage.c +++ b/src/mainboard/nec/powermate2000/romstage.c @@ -26,34 +26,25 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "northbridge/intel/i82810/raminit.h" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "pc80/udelay_io.c" #include "northbridge/intel/i82810/raminit.c" +#include <lib.h> #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) -static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); - enable_smbus(); - report_bist_failure(bist); - /* dump_spd_registers(); */ sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } - |