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-rw-r--r--src/mainboard/via/epia-m/Config.lb241
-rw-r--r--src/mainboard/via/epia-m/auto.c140
-rw-r--r--src/mainboard/via/epia-m/chip.h5
-rw-r--r--src/mainboard/via/epia-m/debug.c128
-rw-r--r--src/mainboard/via/epia-m/failover.c29
-rw-r--r--src/mainboard/via/epia-m/irq_tables.c32
-rw-r--r--src/mainboard/via/epia-m/mainboard.c45
-rw-r--r--src/mainboard/via/epia-m/reset.c43
8 files changed, 663 insertions, 0 deletions
diff --git a/src/mainboard/via/epia-m/Config.lb b/src/mainboard/via/epia-m/Config.lb
new file mode 100644
index 0000000000..0450b2b1b9
--- /dev/null
+++ b/src/mainboard/via/epia-m/Config.lb
@@ -0,0 +1,241 @@
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses USE_FALLBACK_IMAGE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_HARD_RESET
+uses HAVE_OPTION_TABLE
+uses USE_OPTION_TABLE
+uses CONFIG_ROM_STREAM
+uses IRQ_SLOT_COUNT
+uses MAINBOARD
+uses ARCH
+uses FALLBACK_SIZE
+uses STACK_SIZE
+uses HEAP_SIZE
+uses ROM_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses CONFIG_ROM_STREAM_START
+uses PAYLOAD_SIZE
+uses _ROMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses HAVE_MP_TABLE
+
+## ROM_SIZE is the size of boot ROM that this board will use.
+default ROM_SIZE = 256*1024
+
+###
+### Build options
+###
+
+##
+## Build code for the fallback boot
+##
+default HAVE_FALLBACK_BOOT=1
+
+##
+## no MP table
+##
+default HAVE_MP_TABLE=0
+
+##
+## Build code to reset the motherboard from linuxBIOS
+##
+default HAVE_HARD_RESET=1
+
+##
+## Build code to export a programmable irq routing table
+##
+default HAVE_PIRQ_TABLE=1
+default IRQ_SLOT_COUNT=5
+object irq_tables.o
+
+##
+## Build code to export a CMOS option table
+##
+default HAVE_OPTION_TABLE=1
+
+###
+### LinuxBIOS layout values
+###
+
+## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+default ROM_IMAGE_SIZE = 65536
+
+##
+## Use a small 8K stack
+##
+default STACK_SIZE=0x2000
+
+##
+## Use a small 16K heap
+##
+default HEAP_SIZE=0x4000
+
+##
+## Only use the option table in a normal image
+##
+#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default USE_OPTION_TABLE = 0
+
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+ default ROM_SECTION_SIZE = FALLBACK_SIZE
+ default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+ default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
+ default ROM_SECTION_OFFSET = 0
+end
+
+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default CONFIG_ROM_STREAM = 1
+
+##
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+
+##
+## Set all of the defaults for an x86 architecture
+##
+
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+
+driver mainboard.o
+#object reset.o
+
+##
+## Romcc output
+##
+makerule ./failover.E
+ depends "$(MAINBOARD)/failover.c"
+ action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
+end
+
+makerule ./failover.inc
+ depends "./failover.E ./romcc"
+ action "./romcc -O -mcpu=c3 -o failover.inc --label-prefix=failover ./failover.E"
+end
+
+makerule ./auto.E
+ depends "$(MAINBOARD)/auto.c"
+ action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+end
+makerule ./auto.inc
+ depends "./auto.E ./romcc"
+ action "./romcc -O -mcpu=c3 ./auto.E "
+end
+
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+mainboardinit cpu/i386/entry16.inc
+mainboardinit cpu/i386/entry32.inc
+ldscript /cpu/i386/entry16.lds
+ldscript /cpu/i386/entry32.lds
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
+if USE_FALLBACK_IMAGE
+ mainboardinit cpu/i386/reset16.inc
+ ldscript /cpu/i386/reset16.lds
+else
+ mainboardinit cpu/i386/reset32.inc
+ ldscript /cpu/i386/reset32.lds
+end
+
+### Should this be in the northbridge code?
+mainboardinit arch/i386/lib/cpu_reset.inc
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+##
+## Setup our mtrrs
+##
+# mainboardinit cpu/p6/earlymtrr.inc
+
+###
+### This is the early phase of linuxBIOS startup
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if USE_FALLBACK_IMAGE
+ ldscript /arch/i386/lib/failover.lds
+ mainboardinit ./failover.inc
+end
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+##
+## Setup RAM
+##
+mainboardinit ./auto.inc
+
+##
+## Include the secondary Configuration files
+##
+dir /pc80
+config chip.h
+
+northbridge via/vt8601 "vt8601"
+# pci 0:0.0
+# pci 0:1.0
+ southbridge via/vt8231 "vt8231"
+# pci 0:11.0
+# pci 0:11.1
+# pci 0:11.2
+# pci 0:11.3
+# pci 0:11.4
+# pci 0:11.5
+# pci 0:11.6
+# pci 0:12.0
+ register "enable_usb" = "0"
+ register "enable_native_ide" = "0"
+ register "enable_com_ports" = "1"
+ register "enable_keyboard" = "0"
+ register "enable_nvram" = "1"
+ end
+end
+
+cpu p6 "cpu0"
+
+end
+
+##
+## Include the old serial code for those few places that still need it.
+##
+mainboardinit pc80/serial.inc
+mainboardinit arch/i386/lib/console.inc
diff --git a/src/mainboard/via/epia-m/auto.c b/src/mainboard/via/epia-m/auto.c
new file mode 100644
index 0000000000..3e40d04e8a
--- /dev/null
+++ b/src/mainboard/via/epia-m/auto.c
@@ -0,0 +1,140 @@
+#define ASSEMBLY 1
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <cpu/p6/apic.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/hlt.h>
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "ram/ramtest.c"
+#include "northbridge/via/vt8601/raminit.h"
+#include "cpu/p6/earlymtrr.c"
+
+/*
+ */
+void udelay(int usecs)
+{
+ int i;
+ for(i = 0; i < usecs; i++)
+ outb(i&0xff, 0x80);
+}
+
+#include "lib/delay.c"
+#include "cpu/p6/boot_cpu.c"
+#include "debug.c"
+
+#include "southbridge/via/vt8231/vt8231_early_smbus.c"
+
+
+#include "southbridge/via/vt8231/vt8231_early_serial.c"
+static void memreset_setup(void)
+{
+}
+
+/*
+ static void memreset(int controllers, const struct mem_controller *ctrl)
+ {
+ }
+*/
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+ unsigned char c;
+ c = smbus_read_byte(device, address);
+ return c;
+}
+
+
+
+#include "northbridge/via/vt8601/raminit.c"
+/*
+ #include "sdram/generic_sdram.c"
+*/
+
+static void enable_mainboard_devices(void)
+{
+ device_t dev;
+ /* dev 0 for southbridge */
+
+ dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
+
+ if (dev == PCI_DEV_INVALID) {
+ die("Southbridge not found!!!\n");
+ }
+ pci_write_config8(dev, 0x50, 7);
+ pci_write_config8(dev, 0x51, 0xff);
+#if 0
+ // This early setup switches IDE into compatibility mode before PCI gets
+ // // a chance to assign I/Os
+ // movl $CONFIG_ADDR(0, 0x89, 0x42), %eax
+ // // movb $0x09, %dl
+ // movb $0x00, %dl
+ // PCI_WRITE_CONFIG_BYTE
+ //
+#endif
+ /* we do this here as in V2, we can not yet do raw operations
+ * to pci!
+ */
+ dev += 0x100; /* ICKY */
+
+ pci_write_config8(dev, 0x42, 0);
+}
+
+static void enable_shadow_ram(void)
+{
+ device_t dev = 0; /* no need to look up 0:0.0 */
+ unsigned char shadowreg;
+ /* dev 0 for southbridge */
+ shadowreg = pci_read_config8(dev, 0x63);
+ /* 0xf0000-0xfffff */
+ shadowreg |= 0x30;
+ pci_write_config8(dev, 0x63, shadowreg);
+}
+
+static void main(void)
+{
+ unsigned long x;
+ /* init_timer();*/
+ outb(5, 0x80);
+
+ enable_vt8231_serial();
+
+ uart_init();
+ console_init();
+
+ enable_mainboard_devices();
+ enable_smbus();
+ enable_shadow_ram();
+ /*
+ memreset_setup();
+ this is way more generic than we need.
+ sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+ */
+ sdram_set_registers((const struct mem_controller *) 0);
+ sdram_set_spd_registers((const struct mem_controller *) 0);
+ sdram_enable(0, (const struct mem_controller *) 0);
+
+ /* Check all of memory */
+#if 0
+ ram_check(0x00000000, msr.lo);
+#endif
+#if 0
+ static const struct {
+ unsigned long lo, hi;
+ } check_addrs[] = {
+ /* Check 16MB of memory @ 0*/
+ { 0x00000000, 0x01000000 },
+#if TOTAL_CPUS > 1
+ /* Check 16MB of memory @ 2GB */
+ { 0x80000000, 0x81000000 },
+#endif
+ };
+ int i;
+ for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
+ ram_check(check_addrs[i].lo, check_addrs[i].hi);
+ }
+#endif
+ early_mtrr_init();
+}
diff --git a/src/mainboard/via/epia-m/chip.h b/src/mainboard/via/epia-m/chip.h
new file mode 100644
index 0000000000..94b632b5a8
--- /dev/null
+++ b/src/mainboard/via/epia-m/chip.h
@@ -0,0 +1,5 @@
+struct chip_control mainboard_via_epia_control;
+
+struct mainboard_via_epia_config {
+ int nothing;
+};
diff --git a/src/mainboard/via/epia-m/debug.c b/src/mainboard/via/epia-m/debug.c
new file mode 100644
index 0000000000..714fcc5783
--- /dev/null
+++ b/src/mainboard/via/epia-m/debug.c
@@ -0,0 +1,128 @@
+
+static void print_debug_pci_dev(unsigned dev)
+{
+ print_debug("PCI: ");
+ print_debug_hex8((dev >> 16) & 0xff);
+ print_debug_char(':');
+ print_debug_hex8((dev >> 11) & 0x1f);
+ print_debug_char('.');
+ print_debug_hex8((dev >> 8) & 7);
+}
+
+static void print_pci_devices(void)
+{
+ device_t dev;
+ for(dev = PCI_DEV(0, 0, 0);
+ dev <= PCI_DEV(0, 0x1f, 0x7);
+ dev += PCI_DEV(0,0,1)) {
+ uint32_t id;
+ id = pci_read_config32(dev, PCI_VENDOR_ID);
+ if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
+ (((id >> 16) & 0xffff) == 0xffff) ||
+ (((id >> 16) & 0xffff) == 0x0000)) {
+ continue;
+ }
+ print_debug_pci_dev(dev);
+ print_debug("\r\n");
+ }
+}
+
+static void dump_pci_device(unsigned dev)
+{
+ int i;
+ print_debug_pci_dev(dev);
+ print_debug("\r\n");
+
+ for(i = 0; i <= 255; i++) {
+ unsigned char val;
+ if ((i & 0x0f) == 0) {
+ print_debug_hex8(i);
+ print_debug_char(':');
+ }
+ val = pci_read_config8(dev, i);
+ print_debug_char(' ');
+ print_debug_hex8(val);
+ if ((i & 0x0f) == 0x0f) {
+ print_debug("\r\n");
+ }
+ }
+}
+
+static void dump_pci_devices(void)
+{
+ device_t dev;
+ for(dev = PCI_DEV(0, 0, 0);
+ dev <= PCI_DEV(0, 0x1f, 0x7);
+ dev += PCI_DEV(0,0,1)) {
+ uint32_t id;
+ id = pci_read_config32(dev, PCI_VENDOR_ID);
+ if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
+ (((id >> 16) & 0xffff) == 0xffff) ||
+ (((id >> 16) & 0xffff) == 0x0000)) {
+ continue;
+ }
+ dump_pci_device(dev);
+ }
+}
+#if 0
+static void dump_spd_registers(const struct mem_controller *ctrl)
+{
+ int i;
+ print_debug("\r\n");
+ for(i = 0; i < 4; i++) {
+ unsigned device;
+ device = ctrl->channel0[i];
+ if (device) {
+ int j;
+ print_debug("dimm: ");
+ print_debug_hex8(i);
+ print_debug(".0: ");
+ print_debug_hex8(device);
+ for(j = 0; j < 256; j++) {
+ int status;
+ unsigned char byte;
+ if ((j & 0xf) == 0) {
+ print_debug("\r\n");
+ print_debug_hex8(j);
+ print_debug(": ");
+ }
+ status = smbus_read_byte(device, j);
+ if (status < 0) {
+ print_debug("bad device\r\n");
+ break;
+ }
+ byte = status & 0xff;
+ print_debug_hex8(byte);
+ print_debug_char(' ');
+ }
+ print_debug("\r\n");
+ }
+ device = ctrl->channel1[i];
+ if (device) {
+ int j;
+ print_debug("dimm: ");
+ print_debug_hex8(i);
+ print_debug(".1: ");
+ print_debug_hex8(device);
+ for(j = 0; j < 256; j++) {
+ int status;
+ unsigned char byte;
+ if ((j & 0xf) == 0) {
+ print_debug("\r\n");
+ print_debug_hex8(j);
+ print_debug(": ");
+ }
+ status = smbus_read_byte(device, j);
+ if (status < 0) {
+ print_debug("bad device\r\n");
+ break;
+ }
+ byte = status & 0xff;
+ print_debug_hex8(byte);
+ print_debug_char(' ');
+ }
+ print_debug("\r\n");
+ }
+ }
+}
+#endif
diff --git a/src/mainboard/via/epia-m/failover.c b/src/mainboard/via/epia-m/failover.c
new file mode 100644
index 0000000000..bd0df4e89d
--- /dev/null
+++ b/src/mainboard/via/epia-m/failover.c
@@ -0,0 +1,29 @@
+#define ASSEMBLY 1
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include "arch/romcc_io.h"
+#include "pc80/mc146818rtc_early.c"
+#include "cpu/p6/boot_cpu.c"
+
+static void main(void)
+{
+ /* for now, just always assume failure */
+
+#if 0
+ /* Is this a cpu reset? */
+ if (cpu_init_detected()) {
+ if (last_boot_normal()) {
+ asm("jmp __normal_image");
+ } else {
+ asm("jmp __cpu_reset");
+ }
+ }
+
+ /* This is the primary cpu how should I boot? */
+ else if (do_normal_boot()) {
+ asm("jmp __normal_image");
+ }
+#endif
+}
diff --git a/src/mainboard/via/epia-m/irq_tables.c b/src/mainboard/via/epia-m/irq_tables.c
new file mode 100644
index 0000000000..894c27dec5
--- /dev/null
+++ b/src/mainboard/via/epia-m/irq_tables.c
@@ -0,0 +1,32 @@
+/* This file was generated by getpir.c, do not modify!
+ (but if you do, please run checkpir on it to verify)
+ Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
+
+ Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
+*/
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32+16*5, /* there can be total 5 devices on the bus */
+ 0, /* Where the interrupt router lies (bus) */
+ 0x88, /* Where the interrupt router lies (dev) */
+ 0x1c20, /* IRQs devoted exclusively to PCI usage */
+ 0x1106, /* Vendor */
+ 0x8231, /* Device */
+ 0, /* Crap (miniport) */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0x5e, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+ {
+ /* 8231 ethernet */
+ {0,0x90, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x1, 0},
+ /* 8231 internal */
+ {0,0x88, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x2, 0},
+ /* PCI slot */
+ {0,0xa0, {{0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}}, 0, 0},
+ {0,0x50, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x3, 0},
+ {0,0x98, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
+ }
+};
diff --git a/src/mainboard/via/epia-m/mainboard.c b/src/mainboard/via/epia-m/mainboard.c
new file mode 100644
index 0000000000..df52081ac7
--- /dev/null
+++ b/src/mainboard/via/epia-m/mainboard.c
@@ -0,0 +1,45 @@
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+
+#include <arch/io.h>
+#include <device/chip.h>
+#include "chip.h"
+
+static int
+mainboard_scan_bus(device_t root, int maxbus)
+{
+ int retval;
+ printk_spew("%s: root %p maxbus %d\n", __FUNCTION__, root, maxbus);
+ retval = pci_scan_bus(root->bus, 0, 0xff, maxbus);
+ printk_spew("DONE %s: return %d\n", __FUNCTION__, maxbus);
+ return maxbus;
+}
+
+static struct device_operations mainboard_operations = {
+ .read_resources = root_dev_read_resources,
+ .set_resources = root_dev_set_resources,
+ .enable_resources = enable_childrens_resources,
+ .init = 0,
+ .scan_bus = mainboard_scan_bus,
+ .enable = 0,
+};
+
+static void enumerate(struct chip *chip)
+{
+ struct chip *child;
+ dev_root.ops = &mainboard_operations;
+ chip->dev = &dev_root;
+ chip->bus = 0;
+ for(child = chip->children; child; child = child->next) {
+ child->bus = &dev_root.link[0];
+ }
+}
+struct chip_control mainboard_via_epia_control = {
+ .enumerate = enumerate,
+ .name = "VIA EPIA mainboard ",
+};
+
diff --git a/src/mainboard/via/epia-m/reset.c b/src/mainboard/via/epia-m/reset.c
new file mode 100644
index 0000000000..5796e17dc8
--- /dev/null
+++ b/src/mainboard/via/epia-m/reset.c
@@ -0,0 +1,43 @@
+#if 0
+//#include "arch/romcc_io.h"
+#include <arch/io.h>
+
+typedef unsigned device_t;
+
+#define PCI_DEV(BUS, DEV, FN) ( \
+ (((BUS) & 0xFF) << 16) | \
+ (((DEV) & 0x1f) << 11) | \
+ (((FN) & 0x7) << 8))
+
+static void pci_write_config8(device_t dev, unsigned where, unsigned char value)
+{
+ unsigned addr;
+ addr = dev | where;
+ outl(0x80000000 | (addr & ~3), 0xCF8);
+ outb(value, 0xCFC + (addr & 3));
+}
+
+static void pci_write_config32(device_t dev, unsigned where, unsigned value)
+{
+ unsigned addr;
+ addr = dev | where;
+ outl(0x80000000 | (addr & ~3), 0xCF8);
+ outl(value, 0xCFC);
+}
+
+static unsigned pci_read_config32(device_t dev, unsigned where)
+{
+ unsigned addr;
+ addr = dev | where;
+ outl(0x80000000 | (addr & ~3), 0xCF8);
+ return inl(0xCFC);
+}
+
+#include "../../../northbridge/amd/amdk8/reset_test.c"
+
+void hard_reset(void)
+{
+ set_bios_reset();
+ pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1);
+}
+#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 07:53:22 +0000