diff options
Diffstat (limited to 'src/mainboard')
52 files changed, 614 insertions, 539 deletions
diff --git a/src/mainboard/advansus/a785e-i/Kconfig b/src/mainboard/advansus/a785e-i/Kconfig index 309475986b..2becdf07d1 100644 --- a/src/mainboard/advansus/a785e-i/Kconfig +++ b/src/mainboard/advansus/a785e-i/Kconfig @@ -7,10 +7,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_AMD_RS780 - select SOUTHBRIDGE_AMD_CIMX_SB800 + select SOUTHBRIDGE_AMD_SB800 select SUPERIO_WINBOND_W83627HF #COM1, COM2 #select SUPERIO_FINTEK_F81216AD #COM3, COM4 - select SB_SUPERIO_HWM select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY diff --git a/src/mainboard/advansus/a785e-i/Makefile.inc b/src/mainboard/advansus/a785e-i/Makefile.inc deleted file mode 100644 index 7b6a8e6ce5..0000000000 --- a/src/mainboard/advansus/a785e-i/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ - -#SB800 CIMx share AGESA V5 lib code -ifneq ($(CONFIG_CPU_AMD_AGESA),y) - AGESA_ROOT ?= src/vendorcode/amd/agesa/f14 - romstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c - ramstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c - - AGESA_INC := -I$(AGESA_ROOT)/ \ - -I$(AGESA_ROOT)/../common \ - -I$(AGESA_ROOT)/Include \ - -I$(AGESA_ROOT)/Proc/IDS/ \ - -I$(AGESA_ROOT)/Proc/CPU/ \ - -I$(AGESA_ROOT)/Proc/CPU/Family - - CFLAGS_common += $(AGESA_INC) -endif diff --git a/src/mainboard/advansus/a785e-i/mainboard.c b/src/mainboard/advansus/a785e-i/mainboard.c index be37d2d7c4..14f9ec0548 100644 --- a/src/mainboard/advansus/a785e-i/mainboard.c +++ b/src/mainboard/advansus/a785e-i/mainboard.c @@ -20,8 +20,6 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include "SBPLATFORM.h" - u8 is_dev3_present(void); void set_pcie_dereset(void); @@ -34,14 +32,14 @@ void enable_int_gfx(void) volatile u8 *gpio_reg; /* make sure the Acpi MMIO(fed80000) is accessible */ - RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0); + // XXX Redo this RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0); - gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0xD00; /* IoMux Register */ + gpio_reg = (volatile u8 *)0xFED80000 + 0xD00; /* IoMux Register */ *(gpio_reg + 0x6) = 0x1; /* Int_vga_en */ *(gpio_reg + 170) = 0x1; /* gpio_gate */ - gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0x100; /* GPIO Registers */ + gpio_reg = (volatile u8 *)0xFED80000 + 0x100; /* GPIO Registers */ *(gpio_reg + 0x6) = 0x8; *(gpio_reg + 170) = 0x0; diff --git a/src/mainboard/advansus/a785e-i/mptable.c b/src/mainboard/advansus/a785e-i/mptable.c index 7def45339a..a423c39698 100644 --- a/src/mainboard/advansus/a785e-i/mptable.c +++ b/src/mainboard/advansus/a785e-i/mptable.c @@ -20,7 +20,6 @@ #include <string.h> #include <stdint.h> #include <cpu/amd/amdfam10_sysconf.h> -#include <SBPLATFORM.h> extern int bus_isa; extern u8 bus_rs780[11]; @@ -42,7 +41,7 @@ u8 intr_data[] = { static void *smp_write_config_table(void *v) { struct mp_config_table *mc; - u32 dword; + u32 dword = 0; u8 byte; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); @@ -56,7 +55,7 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ - ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); + // XXX Redo this: ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); dword &= 0xFFFFFFF0; smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword); diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index c067664562..f145c25707 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -15,7 +15,6 @@ #define SYSTEM_TYPE 1 /* SERVER=0, DESKTOP=1, MOBILE=2 */ -/* used by incoherent_ht */ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -30,43 +29,43 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/amd/mtrr.h> -#include "northbridge/amd/amdfam10/setup_resource_map.c" +#include <cpu/amd/car.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <southbridge/amd/sb800/smbus.h> +#include <southbridge/amd/sb800/sb800.h> #include "southbridge/amd/rs780/early_setup.c" -#include <sb_cimx.h> -#include <SBPLATFORM.h> /* SB OEM constants */ -#include <southbridge/amd/cimx/sb800/smbus.h> -#include "northbridge/amd/amdfam10/debug.c" +#include "southbridge/amd/sb800/early_setup.c" +#include <arch/early_variables.h> +#include <cbmem.h> + +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" +#include "spd.h" +#include <reset.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -static void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } -static int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" -#include "spd.h" -#include <reset.h> - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; @@ -85,7 +84,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enumerate_ht_chain(); /* enable port80 decoding and southbridge poweron init */ - sb_Poweron_Init(); + sb800_lpc_init(); + sb800_pci_port80(); } post_code(0x30); @@ -156,12 +156,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* run _early_setup before soft-reset. */ rs780_early_setup(); + sb800_early_setup(); #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); post_code(0x39); + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + if (!warm_reset_detect(0)) { /* BSP is node 0 */ init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { @@ -203,6 +206,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) amdmct_cbmem_store_info(sysinfo); rs780_before_pci_init(); + sb800_before_pci_init(); post_code(0x42); post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */ diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 6b094fac35..cdb12e3244 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -29,39 +29,38 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <cpu/amd/mtrr.h> -#include "northbridge/amd/amdfam10/setup_resource_map.c" +#include <cpu/amd/car.h> +#include <southbridge/amd/sb800/smbus.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> #include "southbridge/amd/rs780/early_setup.c" #include "southbridge/amd/sb800/early_setup.c" -#include "northbridge/amd/amdfam10/debug.c" #include <spd.h> -static void activate_spd_rom(const struct mem_controller *ctrl) +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" + +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } -static int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { - return smbus_read_byte(device, address); + return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index 1e0000e877..bbbe869e35 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -31,11 +31,12 @@ #include <superio/ite/it8718f/it8718f.h> #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/rs780/early_setup.c" #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> #include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */ +unsigned get_sbdn(unsigned bus); + #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -46,6 +47,7 @@ static inline int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } +#include "southbridge/amd/rs780/early_setup.c" #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 1ee6698d70..efb2885963 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -31,41 +31,40 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> -#include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/rs780/early_setup.c" +#include <cpu/amd/car.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> -#include "northbridge/amd/amdfam10/debug.c" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> +#include "southbridge/amd/rs780/early_setup.c" #include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) -static void activate_spd_rom(const struct mem_controller *ctrl) { } +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" -static int spd_read_byte(u32 device, u32 address) +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } + +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index 51794484ed..ae89b05015 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -31,10 +31,11 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/amd8111/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +unsigned get_sbdn(unsigned bus); + static void memreset_setup(void) { /* GPIO on amd8111 to enable MEMRST ???? */ @@ -63,6 +64,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } +#include "southbridge/amd/amd8111/early_ctrl.c" #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index fa92219069..831e050648 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -29,23 +29,31 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include "southbridge/amd/amd8111/early_smbus.c" -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <spd.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdfam10/debug.c" +#include <cpu/amd/car.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "northbridge/amd/amdfam10/setup_resource_map.c" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> +#include "southbridge/amd/amd8111/early_smbus.c" #include "southbridge/amd/amd8111/early_ctrl.c" +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" + #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + static void memreset_setup(void) { /* GPIO on amd8111 to enable MEMRST ???? */ @@ -53,7 +61,7 @@ static void memreset_setup(void) outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17); } -static void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_HUB 0x18 int ret,i; @@ -69,21 +77,11 @@ static void activate_spd_rom(const struct mem_controller *ctrl) smbus_write_byte(SMBUS_HUB, 0x03, 0); } -static int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return smbus_read_byte(device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" - static const u8 spd_addr[] = { /* first node */ RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index c68fcccced..022e91de19 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -29,41 +29,40 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> -#include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/rs780/early_setup.c" +#include <cpu/amd/car.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> -#include "northbridge/amd/amdfam10/debug.c" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> +#include <spd.h> +#include "southbridge/amd/rs780/early_setup.c" + +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } -static int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" -#include <spd.h> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index cbe320b62f..3645c9f242 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -32,7 +32,6 @@ #include <superio/winbond/w83627dhg/w83627dhg.h> #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/rs780/early_setup.c" #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> #include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */ @@ -40,6 +39,8 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) +unsigned get_sbdn(unsigned bus); + static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -48,6 +49,7 @@ static inline int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } +#include "southbridge/amd/rs780/early_setup.c" #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index 256cf7e479..c31d98a20b 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -30,43 +30,37 @@ #include <lib.h> #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83667hg-a/w83667hg-a.h> #include <cpu/x86/bist.h> #include <smp/spinlock.h> -// #include "northbridge/amd/amdk8/incoherent_ht.c" +#include <cpu/amd/car.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> #include <southbridge/amd/sr5650/sr5650.h> -#include "northbridge/amd/amdfam10/debug.c" -#include "northbridge/amd/amdfam10/setup_resource_map.c" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> + +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" #define SERIAL_0_DEV PNP_DEV(0x2e, W83667HG_A_SP1) #define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2) -static void activate_spd_rom(const struct mem_controller *ctrl); +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; -static inline int spd_read_byte(unsigned device, unsigned address) +inline int spd_read_byte(unsigned device, unsigned address) { return do_smbus_read_byte(SMBUS_AUX_IO_BASE, device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" - -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" - /* * ASUS KCMA-D8 specific SPD enable/disable magic. * @@ -108,7 +102,7 @@ static const uint8_t spd_addr_fam10[] = { RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, }; -static void activate_spd_rom(const struct mem_controller *ctrl) { +void activate_spd_rom(const struct mem_controller *ctrl) { printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); if (ctrl->node_id == 0) { printk(BIOS_DEBUG, "enable_spd_node0()\n"); diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index c7fa429698..53ec731242 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -20,8 +20,6 @@ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 1 -unsigned int get_sbdn(unsigned bus); - #include <stdint.h> #include <string.h> #include <reset.h> @@ -34,47 +32,41 @@ unsigned int get_sbdn(unsigned bus); #include <timestamp.h> #include <lib.h> #include <spd.h> +#include <cbmem.h> #include <cpu/amd/model_10xxx_rev.h> -#include "southbridge/nvidia/ck804/early_smbus.h" -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> +#include <cpu/amd/car.h> +#include <southbridge/nvidia/ck804/early_smbus.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627thg/w83627thg.h> #include <cpu/x86/bist.h> -// #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdfam10/debug.c" -#include "northbridge/amd/amdfam10/setup_resource_map.c" - -#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) - -static void activate_spd_rom(const struct mem_controller *ctrl); - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" +#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) + #define CK804_MB_SETUP \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+33, ~(0x0f),(0x04 | 0x01), /* -ENOINFO Proprietary BIOS sets this register; "When in Rome..."*/ #include <southbridge/nvidia/ck804/early_setup_ss.h> #include "southbridge/nvidia/ck804/early_setup_car.c" -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" #define GPIO3_DEV PNP_DEV(0x2e, W83627THG_GPIO3) +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + /** * @brief Get SouthBridge device number * @param[in] bus target bus number @@ -182,7 +174,7 @@ static const uint8_t spd_addr[] = { RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, }; -static void activate_spd_rom(const struct mem_controller *ctrl) { +void activate_spd_rom(const struct mem_controller *ctrl) { printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); if (ctrl->node_id == 0) { printk(BIOS_DEBUG, "enable_spd_node0()\n"); diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 80d1c45387..72581a0d88 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -30,43 +30,37 @@ #include <lib.h> #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83667hg-a/w83667hg-a.h> #include <cpu/x86/bist.h> +#include <cpu/amd/car.h> #include <smp/spinlock.h> -// #include "northbridge/amd/amdk8/incoherent_ht.c" #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> #include <southbridge/amd/sr5650/sr5650.h> -#include "northbridge/amd/amdfam10/debug.c" -#include "northbridge/amd/amdfam10/setup_resource_map.c" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> + +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" #define SERIAL_0_DEV PNP_DEV(0x2e, W83667HG_A_SP1) #define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2) -static void activate_spd_rom(const struct mem_controller *ctrl); +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return do_smbus_read_byte(SMBUS_AUX_IO_BASE, device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" - -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" - /* * ASUS KGPE-D16 specific SPD enable/disable magic. * @@ -116,9 +110,8 @@ static const uint8_t spd_addr_fam10[] = { RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, }; -static void activate_spd_rom(const struct mem_controller *ctrl) { +void activate_spd_rom(const struct mem_controller *ctrl) { struct sys_info *sysinfo = &sysinfo_car; - printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); if (ctrl->node_id == 0) { printk(BIOS_DEBUG, "enable_spd_node0()\n"); diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index 3bf54db3fa..7e98cdc73a 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -38,11 +38,23 @@ #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) #define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) +unsigned get_sbdn(unsigned bus); + +unsigned get_sbdn(unsigned bus) +{ + pci_devfn_t dev; + + /* Find the device. */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); + + return (dev >> 15) & 0x1f; +} + static void memreset(int controllers, const struct mem_controller *ctrl) {} static inline void activate_spd_rom(const struct mem_controller *ctrl) {} @@ -51,6 +63,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } +#include "southbridge/nvidia/mcp55/early_ctrl.c" #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 6c081d4a61..1076bf601c 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -17,7 +17,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -//used by incoherent_ht #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -31,43 +30,41 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include <cpu/amd/mtrr.h> -#include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/rs780/early_setup.c" +#include <cpu/amd/car.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> -#include "northbridge/amd/amdfam10/debug.c" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> +#include <spd.h> +#include "southbridge/amd/rs780/early_setup.c" + +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } -static int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" -#include <spd.h> - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 2393e38472..40334d66b3 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -31,43 +31,41 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include <cpu/amd/mtrr.h> -#include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/rs780/early_setup.c" +#include <cpu/amd/car.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> -#include "northbridge/amd/amdfam10/debug.c" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> +#include <spd.h> +#include "southbridge/amd/rs780/early_setup.c" + +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } -static int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" -#include <spd.h> - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; diff --git a/src/mainboard/asus/m5a88-v/Kconfig b/src/mainboard/asus/m5a88-v/Kconfig index 8f2ede13ee..9bb89656a4 100644 --- a/src/mainboard/asus/m5a88-v/Kconfig +++ b/src/mainboard/asus/m5a88-v/Kconfig @@ -7,7 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_AMD_RS780 - select SOUTHBRIDGE_AMD_CIMX_SB800 + select SOUTHBRIDGE_AMD_SB800 select SUPERIO_ITE_IT8721F select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/asus/m5a88-v/Makefile.inc b/src/mainboard/asus/m5a88-v/Makefile.inc deleted file mode 100644 index 7b6a8e6ce5..0000000000 --- a/src/mainboard/asus/m5a88-v/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ - -#SB800 CIMx share AGESA V5 lib code -ifneq ($(CONFIG_CPU_AMD_AGESA),y) - AGESA_ROOT ?= src/vendorcode/amd/agesa/f14 - romstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c - ramstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c - - AGESA_INC := -I$(AGESA_ROOT)/ \ - -I$(AGESA_ROOT)/../common \ - -I$(AGESA_ROOT)/Include \ - -I$(AGESA_ROOT)/Proc/IDS/ \ - -I$(AGESA_ROOT)/Proc/CPU/ \ - -I$(AGESA_ROOT)/Proc/CPU/Family - - CFLAGS_common += $(AGESA_INC) -endif diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c index 941ba26afe..3e20044e68 100644 --- a/src/mainboard/asus/m5a88-v/mainboard.c +++ b/src/mainboard/asus/m5a88-v/mainboard.c @@ -20,8 +20,6 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include "SBPLATFORM.h" - u8 is_dev3_present(void); void set_pcie_dereset(void); @@ -34,14 +32,14 @@ void enable_int_gfx(void) volatile u8 *gpio_reg; /* make sure the MMIO(fed80000) is accessible */ - RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0); + // FIXME: RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0); - gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0xD00; /* IoMux Register */ + gpio_reg = (volatile u8 *)0xFED80000 + 0xD00; /* IoMux Register */ *(gpio_reg + 0x6) = 0x1; /* Int_vga_en */ *(gpio_reg + 170) = 0x1; /* gpio_gate */ - gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0x100; /* GPIO Registers */ + gpio_reg = (volatile u8 *)0xFED80000 + 0x100; /* GPIO Registers */ *(gpio_reg + 0x6) = 0x8; *(gpio_reg + 170) = 0x0; diff --git a/src/mainboard/asus/m5a88-v/mptable.c b/src/mainboard/asus/m5a88-v/mptable.c index 5216783a31..7df8be3e32 100644 --- a/src/mainboard/asus/m5a88-v/mptable.c +++ b/src/mainboard/asus/m5a88-v/mptable.c @@ -20,7 +20,6 @@ #include <string.h> #include <stdint.h> #include <cpu/amd/amdfam10_sysconf.h> -#include <SBPLATFORM.h> extern int bus_isa; extern u8 bus_rs780[11]; @@ -42,7 +41,7 @@ u8 intr_data[] = { static void *smp_write_config_table(void *v) { struct mp_config_table *mc; - u32 dword; + u32 dword = 0; u8 byte; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); @@ -56,7 +55,7 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ - ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); + // FIXME: ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); dword &= 0xFFFFFFF0; smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword); diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 28867ee12f..d11f98a039 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -17,7 +17,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -//used by incoherent_ht #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -32,42 +31,43 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8721f/it8721f.h> #include <cpu/amd/mtrr.h> -#include "northbridge/amd/amdfam10/setup_resource_map.c" +#include <cpu/amd/car.h> +#include <southbridge/amd/sb800/smbus.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> #include "southbridge/amd/rs780/early_setup.c" -#include <sb_cimx.h> -#include <SBPLATFORM.h> /* SB OEM constants */ -#include <southbridge/amd/cimx/sb800/smbus.h> -#include "northbridge/amd/amdfam10/debug.c" +#include "southbridge/amd/sb800/early_setup.c" +#include "spd.h" +#include <reset.h> + +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" + +#define SERIAL_DEV PNP_DEV(0x4e, IT8721F_SP1) + +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; -static void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl) { } -static int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" -#include "spd.h" -#include <reset.h> -#define SERIAL_DEV PNP_DEV(0x4e, IT8721F_SP1) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; @@ -86,7 +86,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enumerate_ht_chain(); //enable port80 decoding and southbridge poweron init - sb_Poweron_Init(); + sb800_lpc_init(); + sb800_pci_port80(); } post_code(0x30); @@ -157,12 +158,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* run _early_setup before soft-reset. */ rs780_early_setup(); + sb800_early_setup(); #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); post_code(0x39); + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + if (!warm_reset_detect(0)) { // BSP is node 0 init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { @@ -218,6 +222,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // die("After MCT init before CAR disabled."); rs780_before_pci_init(); + sb800_before_pci_init(); post_code(0x42); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. diff --git a/src/mainboard/avalue/eax-785e/Kconfig b/src/mainboard/avalue/eax-785e/Kconfig index 09a1d2de8c..3e835dae61 100644 --- a/src/mainboard/avalue/eax-785e/Kconfig +++ b/src/mainboard/avalue/eax-785e/Kconfig @@ -7,10 +7,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_AMD_RS780 - select SOUTHBRIDGE_AMD_CIMX_SB800 + select SOUTHBRIDGE_AMD_SB800 select SUPERIO_WINBOND_W83627HF #COM1, COM2 #select SUPERIO_FINTEK_F81216AD #COM3, COM4 - select SB_SUPERIO_HWM select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY diff --git a/src/mainboard/avalue/eax-785e/Makefile.inc b/src/mainboard/avalue/eax-785e/Makefile.inc deleted file mode 100644 index 7b6a8e6ce5..0000000000 --- a/src/mainboard/avalue/eax-785e/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ - -#SB800 CIMx share AGESA V5 lib code -ifneq ($(CONFIG_CPU_AMD_AGESA),y) - AGESA_ROOT ?= src/vendorcode/amd/agesa/f14 - romstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c - ramstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c - - AGESA_INC := -I$(AGESA_ROOT)/ \ - -I$(AGESA_ROOT)/../common \ - -I$(AGESA_ROOT)/Include \ - -I$(AGESA_ROOT)/Proc/IDS/ \ - -I$(AGESA_ROOT)/Proc/CPU/ \ - -I$(AGESA_ROOT)/Proc/CPU/Family - - CFLAGS_common += $(AGESA_INC) -endif diff --git a/src/mainboard/avalue/eax-785e/mainboard.c b/src/mainboard/avalue/eax-785e/mainboard.c index 1ff96b5715..dc1a1431d3 100644 --- a/src/mainboard/avalue/eax-785e/mainboard.c +++ b/src/mainboard/avalue/eax-785e/mainboard.c @@ -20,8 +20,6 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include "SBPLATFORM.h" - u8 is_dev3_present(void); void set_pcie_dereset(void); @@ -34,14 +32,14 @@ void enable_int_gfx(void) volatile u8 *gpio_reg; /* make sure the Acpi MMIO(fed80000) is accessible */ - RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0); + // FIXME: RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0); - gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0xD00; /* IoMux Register */ + gpio_reg = (volatile u8 *)0xFED80000 + 0xD00; /* IoMux Register */ *(gpio_reg + 0x6) = 0x1; /* Int_vga_en */ *(gpio_reg + 170) = 0x1; /* gpio_gate */ - gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0x100; /* GPIO Registers */ + gpio_reg = (volatile u8 *)0xFED80000 + 0x100; /* GPIO Registers */ *(gpio_reg + 0x6) = 0x8; *(gpio_reg + 170) = 0x0; diff --git a/src/mainboard/avalue/eax-785e/mptable.c b/src/mainboard/avalue/eax-785e/mptable.c index 0b8a91b352..fb6de475b5 100644 --- a/src/mainboard/avalue/eax-785e/mptable.c +++ b/src/mainboard/avalue/eax-785e/mptable.c @@ -19,7 +19,6 @@ #include <arch/io.h> #include <string.h> #include <stdint.h> -#include <SBPLATFORM.h> #include <cpu/amd/amdfam10_sysconf.h> extern int bus_isa; @@ -42,7 +41,7 @@ u8 intr_data[] = { static void *smp_write_config_table(void *v) { struct mp_config_table *mc; - u32 dword; + u32 dword = 0; u8 byte; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); @@ -56,7 +55,7 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ - ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); + // FIXME: ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); dword &= 0xFFFFFFF0; smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword); diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 821eaa70a2..464831066d 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -15,7 +15,6 @@ #define SYSTEM_TYPE 1 /* SERVER=0, DESKTOP=1, MOBILE=2 */ -/* used by incoherent_ht */ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -30,44 +29,43 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/amd/mtrr.h> -#include "northbridge/amd/amdfam10/setup_resource_map.c" +#include <cpu/amd/car.h> +#include <southbridge/amd/sb800/smbus.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> +#include "spd.h" +#include <reset.h> #include "southbridge/amd/rs780/early_setup.c" -#include <sb_cimx.h> -#include <SBPLATFORM.h> /* SB OEM constants */ -#include <southbridge/amd/cimx/sb800/smbus.h> -#include "northbridge/amd/amdfam10/debug.c" +#include "southbridge/amd/sb800/early_setup.c" + +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define CLK_DEV PNP_DEV(0x2e, W83627HF_SP1) -static void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } -static int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" -#include "spd.h" -#include <reset.h> - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; @@ -86,7 +84,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enumerate_ht_chain(); /*enable port80 decoding and southbridge poweron init */ - sb_Poweron_Init(); + sb800_lpc_init(); + sb800_pci_port80(); } post_code(0x30); @@ -157,12 +156,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* run _early_setup before soft-reset. */ rs780_early_setup(); + sb800_early_setup(); #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); post_code(0x39); + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + if (!warm_reset_detect(0)) { /* BSP is node 0 */ init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { @@ -204,6 +206,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) amdmct_cbmem_store_info(sysinfo); rs780_before_pci_init(); + sb800_before_pci_init(); post_code(0x42); post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */ diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index 33d939a71a..158e612519 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -17,11 +17,11 @@ #include <superio/nsc/pc87417/pc87417.h> #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/broadcom/bcm5785/early_setup.c" #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1) #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC) +unsigned get_sbdn(unsigned bus); static void memreset_setup(void) { } static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -37,6 +37,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } +#include "southbridge/broadcom/bcm5785/early_setup.c" #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index b12b12ca0c..d42ccc7570 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -36,11 +36,23 @@ #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) #define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) +unsigned get_sbdn(unsigned bus); + +unsigned get_sbdn(unsigned bus) +{ + pci_devfn_t dev; + + /* Find the device. */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); + + return (dev >> 15) & 0x1f; +} + static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -57,6 +69,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ +#include "southbridge/nvidia/mcp55/early_ctrl.c" #include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" #include <northbridge/amd/amdk8/f.h> diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 06eaa8cefc..2e22556b17 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -27,43 +27,41 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> -#include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/rs780/early_setup.c" +#include <cpu/amd/car.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> -#include "northbridge/amd/amdfam10/debug.c" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> +#include <spd.h> +#include "southbridge/amd/rs780/early_setup.c" + +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } -static int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" -#include <spd.h> - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 860b1f1070..bf51e38238 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -27,43 +27,41 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> -#include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/rs780/early_setup.c" +#include <cpu/amd/car.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> -#include "northbridge/amd/amdfam10/debug.c" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> +#include <spd.h> +#include "southbridge/amd/rs780/early_setup.c" + +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } -static int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" -#include <spd.h> - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index 9efda6f547..1405507a7f 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -17,7 +17,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -//used by incoherent_ht #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -31,43 +30,41 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> -#include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/rs780/early_setup.c" +#include <cpu/amd/car.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> -#include "northbridge/amd/amdfam10/debug.c" +#include <spd.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> +#include "southbridge/amd/rs780/early_setup.c" + +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } -static int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" -#include <spd.h> - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index ea0b60c525..4ec6a8718c 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -20,10 +20,11 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/x86/bist.h> -#include "southbridge/amd/amd8111/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +unsigned get_sbdn(unsigned bus); + static void memreset_setup(void) { if (is_cpu_pre_c0()) { @@ -79,6 +80,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } +#include "southbridge/amd/amd8111/early_ctrl.c" #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" #include "resourcemap.c" diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 1d1195a82c..e7a3b2f36e 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -41,11 +41,12 @@ #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/broadcom/bcm5785/early_setup.c" #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) +unsigned get_sbdn(unsigned bus); + static void memreset(int controllers, const struct mem_controller *ctrl) { } static inline void activate_spd_rom(const struct mem_controller *ctrl) @@ -62,6 +63,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } +#include "southbridge/broadcom/bcm5785/early_setup.c" #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 39cd0e339d..d282e34d0e 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -35,24 +35,32 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include "southbridge/broadcom/bcm5785/early_smbus.c" -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <spd.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <superio/serverengines/pilot/pilot.h> #include <superio/nsc/pc87417/pc87417.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdfam10/debug.c" +#include <cpu/amd/car.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> +#include "southbridge/broadcom/bcm5785/early_smbus.c" #include "southbridge/broadcom/bcm5785/early_setup.c" +#include "cpu/amd/quadcore/quadcore.c" + #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) -static inline void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +inline void activate_spd_rom(const struct mem_controller *ctrl) { u8 val; outb(0x3d, 0x0cd6); @@ -63,20 +71,11 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) outb((val & ~3) | ctrl->spd_switch_addr, 0xcd7); } -static inline int spd_read_byte(unsigned device, unsigned address) +inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" - static const u8 spd_addr[] = { // switch addr, 1A addr, 2A addr, 3A addr, 4A addr, 1B addr, 2B addr, 3B addr 4B addr //first node diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 09e4ec7e2a..1731ef4c26 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -17,7 +17,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -//used by incoherent_ht #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -31,42 +30,40 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f71859/f71859.h> #include <cpu/amd/mtrr.h> -#include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/rs780/early_setup.c" +#include <cpu/amd/car.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> -#include "northbridge/amd/amdfam10/debug.c" +#include <spd.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> +#include "southbridge/amd/rs780/early_setup.c" + +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" #define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1) -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } -static int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" -#include <spd.h> - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index c1c141e822..9fbc80839c 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -16,10 +16,11 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/amd8111/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +unsigned get_sbdn(unsigned bus); + /* * GPIO28 of 8111 will control H0_MEMRESET_L * GPIO29 of 8111 will control H1_MEMRESET_L @@ -54,6 +55,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } +#include "southbridge/amd/amd8111/early_ctrl.c" #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 43e88d1795..f540a73bde 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -18,7 +18,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -//used by incoherent_ht #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -32,21 +31,26 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f71863fg/f71863fg.h> #include <cpu/amd/mtrr.h> -#include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/rs780/early_setup.c" +#include <cpu/amd/car.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> -#include "northbridge/amd/amdfam10/debug.c" +#include <spd.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> +#include "southbridge/amd/rs780/early_setup.c" + +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" #if CONFIG_TTYS0_BASE == 0x2f8 #define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP2) @@ -54,24 +58,17 @@ #define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP1) #endif -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } -static int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" -#include <spd.h> - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index b3f9d4ef62..5b036d6631 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -38,10 +38,22 @@ #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1) +unsigned get_sbdn(unsigned bus); + +unsigned get_sbdn(unsigned bus) +{ + pci_devfn_t dev; + + /* Find the device. */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); + + return (dev >> 15) & 0x1f; +} + static void memreset(int controllers, const struct mem_controller *ctrl) {} static inline void activate_spd_rom(const struct mem_controller *ctrl) {} @@ -50,6 +62,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } +#include "southbridge/nvidia/mcp55/early_ctrl.c" #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index 6f5ff3202c..db5242926a 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -39,11 +39,12 @@ #include <superio/nsc/pc87417/pc87417.h> #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/broadcom/bcm5785/early_setup.c" #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1) #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC) +unsigned get_sbdn(unsigned bus); + static void memreset(int controllers, const struct mem_controller *ctrl) { } static inline void activate_spd_rom(const struct mem_controller *ctrl) @@ -60,6 +61,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } +#include "southbridge/broadcom/bcm5785/early_setup.c" #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 7d360e3790..2dd1283bc7 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -39,10 +39,22 @@ #include <spd.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include <device/pci_ids.h> -#include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) +unsigned get_sbdn(unsigned bus); + +unsigned get_sbdn(unsigned bus) +{ + pci_devfn_t dev; + + /* Find the device. */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); + + return (dev >> 15) & 0x1f; +} + static void memreset(int controllers, const struct mem_controller *ctrl) { } static inline void activate_spd_rom(const struct mem_controller *ctrl) @@ -59,6 +71,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } +#include "southbridge/nvidia/mcp55/early_ctrl.c" #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index e22ec11b94..7e987a01b9 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -30,33 +30,46 @@ #include <lib.h> #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> -#include "southbridge/nvidia/mcp55/early_smbus.c" -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" +#include <cpu/amd/car.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdfam10/debug.c" -#include "northbridge/amd/amdfam10/setup_resource_map.c" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> +#include "southbridge/nvidia/mcp55/early_smbus.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" + #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" +unsigned get_sbdn(unsigned bus) +{ + pci_devfn_t dev; + + /* Find the device. */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); + + return (dev >> 15) & 0x1f; +} #define MCP55_MB_SETUP \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \ @@ -68,10 +81,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" static void sio_setup(void) { diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index d0966ee4fe..7228c3e185 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -37,10 +37,22 @@ #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) +unsigned get_sbdn(unsigned bus); + +unsigned get_sbdn(unsigned bus) +{ + pci_devfn_t dev; + + /* Find the device. */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); + + return (dev >> 15) & 0x1f; +} + static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -49,6 +61,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } +#include "southbridge/nvidia/mcp55/early_ctrl.c" #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c index a7489daa6b..51f5a85138 100644 --- a/src/mainboard/sunw/ultra40m2/romstage.c +++ b/src/mainboard/sunw/ultra40m2/romstage.c @@ -36,10 +36,22 @@ #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, DME1737_SP1) +unsigned get_sbdn(unsigned bus); + +unsigned get_sbdn(unsigned bus) +{ + pci_devfn_t dev; + + /* Find the device. */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); + + return (dev >> 15) & 0x1f; +} + static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -48,6 +60,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } +#include "southbridge/nvidia/mcp55/early_ctrl.c" #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index d85ae5ba68..7d3470f9cc 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -34,11 +34,23 @@ #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) +unsigned get_sbdn(unsigned bus); + +unsigned get_sbdn(unsigned bus) +{ + pci_devfn_t dev; + + /* Find the device. */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); + + return (dev >> 15) & 0x1f; +} + static void memreset(int controllers, const struct mem_controller *ctrl) { } static inline void activate_spd_rom(const struct mem_controller *ctrl) @@ -58,6 +70,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } +#include "southbridge/nvidia/mcp55/early_ctrl.c" #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index a7e69bd9b3..7986d50d68 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -37,11 +37,23 @@ #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) +unsigned get_sbdn(unsigned bus); + +unsigned get_sbdn(unsigned bus) +{ + pci_devfn_t dev; + + /* Find the device. */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); + + return (dev >> 15) & 0x1f; +} + static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -50,6 +62,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } +#include "southbridge/nvidia/mcp55/early_ctrl.c" #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 7766f3a5bf..26fba1406a 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -30,40 +30,50 @@ #include <lib.h> #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> -#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdfam10/debug.c" -#include "northbridge/amd/amdfam10/setup_resource_map.c" +#include <cpu/amd/car.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> + +#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN #include "southbridge/nvidia/mcp55/early_ctrl.c" +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" +#include <southbridge/nvidia/mcp55/early_setup_ss.h> +#include "southbridge/nvidia/mcp55/early_setup_car.c" + #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <southbridge/nvidia/mcp55/early_setup_ss.h> -#include "southbridge/nvidia/mcp55/early_setup_car.c" -#include <cpu/amd/microcode.h> +unsigned get_sbdn(unsigned bus) +{ + pci_devfn_t dev; -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" + /* Find the device. */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); + + return (dev >> 15) & 0x1f; +} static void sio_setup(void) { diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 25cf7d7d80..eedc9d08c8 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -30,47 +30,56 @@ #include <lib.h> #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> -#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdfam10/debug.c" -#include "northbridge/amd/amdfam10/setup_resource_map.c" +#include <cpu/amd/car.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> +#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN #include "southbridge/nvidia/mcp55/early_ctrl.c" +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" +#include <southbridge/nvidia/mcp55/early_setup_ss.h> +#include "southbridge/nvidia/mcp55/early_setup_car.c" + #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) #define SMBUS_SWITCH1 0x70 #define SMBUS_SWITCH2 0x72 -static inline void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +inline void activate_spd_rom(const struct mem_controller *ctrl) { smbus_send_byte(SMBUS_SWITCH1, 5 & 0x0f); smbus_send_byte(SMBUS_SWITCH2, (5 >> 4) & 0x0f); } -static inline int spd_read_byte(unsigned device, unsigned address) +inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <southbridge/nvidia/mcp55/early_setup_ss.h> -#include "southbridge/nvidia/mcp55/early_setup_car.c" -#include <cpu/amd/microcode.h> +unsigned get_sbdn(unsigned bus) +{ + pci_devfn_t dev; -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" + /* Find the device. */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); + + return (dev >> 15) & 0x1f; +} static void sio_setup(void) { diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index f2c79b4db1..091514d91a 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -17,7 +17,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -//used by incoherent_ht #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -31,40 +30,39 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <cpu/amd/mtrr.h> -#include "northbridge/amd/amdfam10/setup_resource_map.c" +#include <cpu/amd/car.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> #include <southbridge/amd/sr5650/sr5650.h> #include <superio/nuvoton/wpcm450/wpcm450.h> -#include "northbridge/amd/amdfam10/debug.c" +#include <spd.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> + +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" -static void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } -static int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" -#include <spd.h> - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index 8c012727fb..64caabeb37 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -37,10 +37,22 @@ #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +unsigned get_sbdn(unsigned bus); + +unsigned get_sbdn(unsigned bus) +{ + pci_devfn_t dev; + + /* Find the device. */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); + + return (dev >> 15) & 0x1f; +} + static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -49,6 +61,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } +#include "southbridge/nvidia/mcp55/early_ctrl.c" #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index e095b7960e..4491df56ca 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -30,34 +30,36 @@ #include <lib.h> #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> -#include "southbridge/nvidia/mcp55/early_smbus.c" -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" +#include <cpu/amd/car.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdfam10/debug.c" -#include "northbridge/amd/amdfam10/setup_resource_map.c" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> +#include "southbridge/nvidia/mcp55/early_smbus.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" + #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" - #define MCP55_MB_SETUP \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \ @@ -68,10 +70,17 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" -#include <cpu/amd/microcode.h> -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" +unsigned get_sbdn(unsigned bus) +{ + pci_devfn_t dev; + + /* Find the device. */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); + + return (dev >> 15) & 0x1f; +} static void sio_setup(void) { |