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-rw-r--r--src/mainboard/amd/persimmon/romstage.c15
-rw-r--r--src/mainboard/asrock/e350m1/romstage.c15
2 files changed, 0 insertions, 30 deletions
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index 5ef5557a5b..dfc2b6ae4b 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -55,21 +55,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
__writemsr (0xc0010062, 0);
- if (boot_cpu())
- {
- u8 reg8;
- // SB800: program AcpiMmioEn to enable MMIO access to MiscCntrl register
- outb(0x24, 0xCD6);
- reg8 = inb(0xCD7);
- reg8 |= 1;
- reg8 &= ~(1 << 1);
- outb(reg8, 0xCD7);
-
- // program SB800 MiscCntrl
- *(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
- *(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */
- }
-
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
sb_poweron_init();
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 29df530279..38790cd517 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -55,21 +55,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
__writemsr(0xc0010062, 0);
- if (boot_cpu()) {
- u8 reg8;
- // SB800: Program AcpiMmioEn to enable MMIO access to MiscCntrl register
- outb(0x24, 0xCD6);
- reg8 = inb(0xCD7);
- reg8 |= 1;
- reg8 &= ~(1 << 1);
- outb(0x24, 0xCD6);
- outb(reg8, 0xCD7);
-
- // Program SB800 MiscCntrl
- *(volatile u32 *)(0xFED80000 + 0xE00 + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
- *(volatile u32 *)(0xFED80000 + 0xE00 + 0x40) |= 1 << 1; /* 48Mhz */
- }
-
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
sb_poweron_init();