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-rw-r--r--src/mainboard/via/vt8454c/Config.lb198
-rw-r--r--src/mainboard/via/vt8454c/Options.lb246
-rw-r--r--src/mainboard/via/vt8454c/acpi_tables.c205
-rw-r--r--src/mainboard/via/vt8454c/auto.c127
-rw-r--r--src/mainboard/via/vt8454c/chip.h26
-rw-r--r--src/mainboard/via/vt8454c/cmos.layout67
-rw-r--r--src/mainboard/via/vt8454c/debug.c108
-rw-r--r--src/mainboard/via/vt8454c/dmi.h31
-rw-r--r--src/mainboard/via/vt8454c/dsdt.dsl341
-rw-r--r--src/mainboard/via/vt8454c/fadt.c156
-rw-r--r--src/mainboard/via/vt8454c/irq-p2p-bridge.dsl88
-rw-r--r--src/mainboard/via/vt8454c/irq.dsl143
-rw-r--r--src/mainboard/via/vt8454c/irq_tables.c61
-rw-r--r--src/mainboard/via/vt8454c/mainboard.c28
-rw-r--r--src/mainboard/via/vt8454c/mptable.c104
-rw-r--r--src/mainboard/via/vt8454c/reset.c28
16 files changed, 1957 insertions, 0 deletions
diff --git a/src/mainboard/via/vt8454c/Config.lb b/src/mainboard/via/vt8454c/Config.lb
new file mode 100644
index 0000000000..5cda9d228e
--- /dev/null
+++ b/src/mainboard/via/vt8454c/Config.lb
@@ -0,0 +1,198 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2009 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+##
+## Compute the location and size of where this firmware image
+## (coreboot plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+ default ROM_SECTION_SIZE = FALLBACK_SIZE
+ default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+ default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
+ default ROM_SECTION_OFFSET = 0
+end
+
+##
+## Compute the start location and size size of
+## The coreboot bootloader.
+##
+default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+
+##
+## Compute where this copy of coreboot will start in the boot rom
+##
+default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up coreboot,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+
+##
+## Set all of the defaults for an x86 architecture
+##
+
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+
+if HAVE_MP_TABLE
+ object mptable.o
+end
+
+if HAVE_PIRQ_TABLE
+ object irq_tables.o
+end
+
+if HAVE_ACPI_TABLES
+ object fadt.o
+ object acpi_tables.o
+ makerule dsdt.c
+ depends "$(MAINBOARD)/dsdt.dsl"
+ action "iasl -p dsdt -tc $(MAINBOARD)/dsdt.dsl"
+ action "mv dsdt.hex dsdt.c"
+ end
+ object ./dsdt.o
+end
+
+##
+## Romcc output
+##
+makerule ./auto.inc
+ depends "$(MAINBOARD)/auto.c option_table.h"
+ action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c -S $(MAINBOARD)/auto.c -o $@"
+ action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
+ action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
+end
+
+##
+## Build our 16 bit and 32 bit coreboot entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+
+##
+## Build our reset vector (This is where coreboot is entered)
+##
+if USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+else
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
+end
+
+mainboardinit cpu/via/car/cache_as_ram.inc
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+##
+## Setup RAM
+##
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit ./auto.inc
+
+##
+## Include the secondary Configuration files
+##
+dir /pc80
+config chip.h
+
+chip northbridge/via/cx700
+ device apic_cluster 0 on
+ chip cpu/via/model_c7
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ device pci 0.0 on end # AGP Bridge
+ device pci 0.1 on end # Error Reporting
+ device pci 0.2 on end # Host Bus Control
+ device pci 0.3 on end # Memory Controller
+ device pci 0.4 on end # Power Management
+ device pci 0.7 on end # V-Link Controller
+ device pci 1.0 on # PCI Bridge
+ chip drivers/pci/onboard
+ device pci 0.0 on end
+ #register "rom_address" = "0xfffc0000" #256k image
+ register "rom_address" = "0xfff80000" #512k image
+ #register "rom_address" = "0xfff00000" #1024k image
+ end # Onboard Video
+ end # PCI Bridge
+ device pci f.0 on end # IDE/SATA
+ #device pci f.1 on end # IDE
+ device pci 10.0 on end # USB 1.1
+ device pci 10.1 on end # USB 1.1
+ device pci 10.2 on end # USB 1.1
+ device pci 10.4 on end # USB 2.0
+ device pci 11.0 on # Southbridge LPC
+ chip superio/via/vt1211
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 2e.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.b on # HWM
+ io 0x60 = 0xec00
+ end
+ end # superio
+ end # pci 11.0
+ # 1-4 non existant
+ #device pci 11.5 on end # AC97 Audio
+ #device pci 11.6 off end # AC97 Modem
+ #device pci 12.0 on end # Ethernet
+ end # pci domain 0
+end # cx700
+
diff --git a/src/mainboard/via/vt8454c/Options.lb b/src/mainboard/via/vt8454c/Options.lb
new file mode 100644
index 0000000000..4a319725f1
--- /dev/null
+++ b/src/mainboard/via/vt8454c/Options.lb
@@ -0,0 +1,246 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2009 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses IRQ_SLOT_COUNT
+uses HAVE_ACPI_TABLES
+uses HAVE_OPTION_TABLE
+uses USE_OPTION_TABLE
+
+uses USE_FALLBACK_IMAGE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_HARD_RESET
+uses MAINBOARD
+uses MAINBOARD_VENDOR
+uses MAINBOARD_PART_NUMBER
+uses COREBOOT_EXTRA_VERSION
+uses ARCH
+uses FALLBACK_SIZE
+uses STACK_SIZE
+uses HEAP_SIZE
+uses ROM_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+
+uses CONFIG_COMPRESS
+uses CONFIG_ROM_PAYLOAD
+uses CONFIG_ROM_PAYLOAD_START
+uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
+uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses PAYLOAD_SIZE
+
+uses _ROMBASE
+uses _RAMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses CONFIG_CBFS
+
+# compiler specifics
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
+
+# Console specifics
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_CONSOLE_SERIAL8250
+uses TTYS0_BAUD
+uses TTYS0_BASE
+uses TTYS0_LCS
+
+uses CONFIG_UDELAY_TSC
+uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+uses CONFIG_PCI_ROM_RUN
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_MAX_PCI_BUSES
+uses CONFIG_SMP
+uses CONFIG_IOAPIC
+
+uses CONFIG_GDB_STUB
+
+uses USE_DCACHE_RAM
+uses DCACHE_RAM_BASE
+uses DCACHE_RAM_SIZE
+uses CONFIG_USE_PRINTK_IN_CAR
+
+## ROM_SIZE is the size of boot ROM that this board will use.
+default ROM_SIZE = 256*1024
+
+default USE_DCACHE_RAM=1
+default DCACHE_RAM_BASE=0xffef0000
+#default DCACHE_RAM_BASE=0xffbf0000
+#default DCACHE_RAM_BASE=0xfec00000
+default DCACHE_RAM_SIZE=0x8000
+default CONFIG_USE_PRINTK_IN_CAR=1
+
+###
+### Leave this to 0; VGA is handled by seperate code.
+###
+default CONFIG_PCI_ROM_RUN=0
+default CONFIG_CONSOLE_VGA=0
+
+##
+## Build code for the fallback boot
+##
+default HAVE_FALLBACK_BOOT=1
+
+##
+## Use TSC for udelay.
+##
+default CONFIG_UDELAY_TSC=1
+default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
+
+##
+## Build code to reset the motherboard from linuxBIOS
+##
+default HAVE_HARD_RESET=1
+
+##
+## Build code to export a programmable irq routing table
+##
+default HAVE_PIRQ_TABLE=1
+default IRQ_SLOT_COUNT=15
+
+##
+## Build code to export an x86 MP table
+## Useful for specifying IRQ routing values
+##
+default HAVE_MP_TABLE=1
+
+##
+## Build code to load acpi tables
+##
+default HAVE_ACPI_TABLES=1
+
+##
+## Build code to export a CMOS option table
+##
+default HAVE_OPTION_TABLE=1
+
+
+##
+## Build code to setup a generic IOAPIC
+##
+default CONFIG_SMP=1
+default CONFIG_IOAPIC=1
+
+###
+### LinuxBIOS layout values
+###
+
+## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+default ROM_IMAGE_SIZE = 65536
+default FALLBACK_SIZE = 131072
+
+##
+## Use a small 8K stack
+##
+default STACK_SIZE=0x2000
+
+##
+## Use a small 16K heap
+##
+default HEAP_SIZE=0x4000
+
+##
+## Only use the option table in a normal image
+##
+#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default USE_OPTION_TABLE = 0
+
+default _RAMBASE = 0x00004000
+
+default CONFIG_ROM_PAYLOAD = 1
+
+##
+## The default compiler
+##
+default CROSS_COMPILE=""
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
+
+##
+## Set this to the max PCI bus number you
+## would ever use for PCI config IO.
+## Setting this number very high will make
+## pci_locate_device take a long time when
+## it can't find a device.
+##
+default CONFIG_MAX_PCI_BUSES = 0x80
+
+##
+## Disable the gdb stub by default
+##
+default CONFIG_GDB_STUB=0
+
+##
+## The Serial Console
+##
+
+# To Enable the Serial Console
+default CONFIG_CONSOLE_SERIAL8250=1
+
+## Select the serial console baud rate
+default TTYS0_BAUD=115200
+#default TTYS0_BAUD=57600
+#default TTYS0_BAUD=38400
+#default TTYS0_BAUD=19200
+#default TTYS0_BAUD=9600
+#default TTYS0_BAUD=4800
+#default TTYS0_BAUD=2400
+#default TTYS0_BAUD=1200
+
+# Select the serial console base port
+default TTYS0_BASE=0x3f8
+
+# Select the serial protocol
+# This defaults to 8 data bits, 1 stop bit, and no parity
+default TTYS0_LCS=0x3
+
+##
+## Select the coreboot loglevel
+##
+## EMERG 1 system is unusable
+## ALERT 2 action must be taken immediately
+## CRIT 3 critical conditions
+## ERR 4 error conditions
+## WARNING 5 warning conditions
+## NOTICE 6 normal but significant condition
+## INFO 7 informational
+## DEBUG 8 debug-level messages
+## SPEW 9 Way too many details
+
+## Request this level of debugging output
+default DEFAULT_CONSOLE_LOGLEVEL=5
+## At a maximum only compile in this level of debugging
+default MAXIMUM_CONSOLE_LOGLEVEL=5
+
+#
+# CBFS
+#
+default CONFIG_CBFS=0
+
+end
+
diff --git a/src/mainboard/via/vt8454c/acpi_tables.c b/src/mainboard/via/vt8454c/acpi_tables.c
new file mode 100644
index 0000000000..edf8d7e207
--- /dev/null
+++ b/src/mainboard/via/vt8454c/acpi_tables.c
@@ -0,0 +1,205 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "dmi.h"
+
+extern unsigned char AmlCode[];
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+ device_t dev;
+ u64 mmcfg;
+
+ dev = dev_find_device(0x1106, 0x324b, 0); // 0:0x13.0
+ if (!dev)
+ return current;
+
+ // MMCFG not supported or not enabled.
+ if ((pci_read_config8(dev, 0x40) & 0xC0) != 0xC0)
+ return current;
+
+ mmcfg = ((u64) pci_read_config8(dev, 0x41)) << 28;
+ if (!mmcfg)
+ return current;
+
+ current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, mmcfg, 0x0, 0x0, 0xff);
+
+ return current;
+}
+
+
+void acpi_create_via_hpet(acpi_hpet_t * hpet)
+{
+#define HPET_ADDR 0xfe800000ULL
+ acpi_header_t *header = &(hpet->header);
+ acpi_addr_t *addr = &(hpet->addr);
+
+ memset((void *) hpet, 0, sizeof(acpi_hpet_t));
+
+ /* fill out header fields */
+ memcpy(header->signature, HPET_NAME, 4);
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, "COREBOOT", 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+
+ header->length = sizeof(acpi_hpet_t);
+ header->revision = 1;
+
+ /* fill out HPET address */
+ // XXX factory bios just puts an address here -- who's right?
+ addr->space_id = 0; /* Memory */
+ addr->bit_width = 64;
+ addr->bit_offset = 0;
+ addr->addrl = HPET_ADDR & 0xffffffff;
+ addr->addrh = HPET_ADDR >> 32;
+
+ hpet->id = 0x11068201; /* VIA */
+ hpet->number = 0x00;
+ hpet->min_tick = 0x0090;
+
+ header->checksum =
+ acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
+}
+
+
+
+#define IO_APIC_ADDR 0xfec00000UL
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local Apic */
+ current += acpi_create_madt_lapic((acpi_madt_lapic_t *) current, 0, 0);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0);
+
+ /* INT_SRC_OVR */
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, 0x000f); // low/level
+
+ /* LAPIC_NMI */
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) current, 0, 0x0005, 1); // high/edge
+
+ return current;
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+ // Not implemented
+ return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ /* No NUMA, no SRAT */
+ return current;
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ acpi_rsdp_t *rsdp;
+ acpi_rsdt_t *rsdt;
+ acpi_hpet_t *hpet;
+ acpi_madt_t *madt;
+ acpi_mcfg_t *mcfg;
+ acpi_fadt_t *fadt;
+ acpi_facs_t *facs;
+ acpi_header_t *dsdt;
+
+ /* Align ACPI tables to 16byte */
+ start = (start + 0x0f) & -0x10;
+ current = start;
+
+ printk_info("ACPI: Writing ACPI tables at %lx.\n", start);
+
+ /* We need at least an RSDP and an RSDT Table */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+
+ /* clear all table memory */
+ memset((void *) start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt);
+ acpi_write_rsdt(rsdt);
+
+ /*
+ * We explicitly add these tables later on:
+ */
+
+ printk_debug("ACPI: * HPET\n");
+
+ hpet = (acpi_hpet_t *) current;
+ current += sizeof(acpi_hpet_t);
+ acpi_create_via_hpet(hpet);
+ acpi_add_table(rsdt, hpet);
+
+ /* If we want to use HPET Timers Linux wants an MADT */
+ printk_debug("ACPI: * MADT\n");
+
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current += madt->header.length;
+ acpi_add_table(rsdt, madt);
+
+ printk_debug("ACPI: * MCFG\n");
+ mcfg = (acpi_mcfg_t *) current;
+ acpi_create_mcfg(mcfg);
+ current += mcfg->header.length;
+ acpi_add_table(rsdt, mcfg);
+
+ printk_debug("ACPI: * FACS\n");
+ facs = (acpi_facs_t *) current;
+ current += sizeof(acpi_facs_t);
+ acpi_create_facs(facs);
+
+ dsdt = (acpi_header_t *) current;
+ current += ((acpi_header_t *) AmlCode)->length;
+ memcpy((void *) dsdt, (void *) AmlCode,
+ ((acpi_header_t *) AmlCode)->length);
+#if DONT_TRUST_IASL
+ dsdt->checksum = 0; // don't trust intel iasl compiler to get this right
+ dsdt->checksum = acpi_checksum(dsdt, dsdt->length);
+#endif
+ printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt,
+ dsdt->length);
+ printk_debug("ACPI: * FADT\n");
+
+ fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+
+ acpi_create_fadt(fadt, facs, dsdt);
+ acpi_add_table(rsdt, fadt);
+
+ printk_debug("ACPI: * DMI (Linux workaround)\n");
+ memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE);
+
+ printk_info("ACPI: done.\n");
+ return current;
+}
diff --git a/src/mainboard/via/vt8454c/auto.c b/src/mainboard/via/vt8454c/auto.c
new file mode 100644
index 0000000000..1812fca139
--- /dev/null
+++ b/src/mainboard/via/vt8454c/auto.c
@@ -0,0 +1,127 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/hlt.h>
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "ram/ramtest.c"
+#include "northbridge/via/cx700/raminit.h"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "cpu/x86/bist.h"
+
+#define CONFIG_DEACTIVATE_CAR 1
+#define CONFIG_DEACTIVATE_CAR_FILE "cpu/via/car/cache_as_ram_post.c"
+#include "cpu/x86/car/copy_and_run.c"
+#include "pc80/udelay_io.c"
+#include "lib/delay.c"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/via/cx700/cx700_early_smbus.c"
+#include "debug.c"
+
+#include "northbridge/via/cx700/cx700_early_serial.c"
+#include "northbridge/via/cx700/raminit.c"
+
+static void enable_mainboard_devices(void)
+{
+ device_t dev;
+
+ dev = pci_locate_device(PCI_ID(0x1106, 0x8324), 0);
+ if (dev == PCI_DEV_INVALID) {
+ die("LPC bridge not found!!!\n");
+ }
+ // Disable GP3
+ pci_write_config8(dev, 0x98, 0x00);
+
+ // Disable mc97
+ pci_write_config8(dev, 0x50, 0x80);
+
+ // Disable internal KBC Configuration
+ pci_write_config8(dev, 0x51, 0x2d);
+ pci_write_config8(dev, 0x58, 0x42);
+ pci_write_config8(dev, 0x59, 0x80);
+ pci_write_config8(dev, 0x5b, 0x01);
+
+ // Enable P2P Bridge Header for External PCI BUS.
+ dev = pci_locate_device(PCI_ID(0x1106, 0x324e), 0);
+ if (dev == PCI_DEV_INVALID) {
+ die("P2P bridge not found!!!\n");
+ }
+ pci_write_config8(dev, 0x4f, 0x41);
+
+ // Switch SATA to non-RAID mode
+ dev = pci_locate_device(PCI_ID(0x1106, 0x0581), 0);
+ if (dev != PCI_DEV_INVALID) {
+ pci_write_config16(dev, 0xBA, 0x5324);
+ }
+}
+
+static void enable_shadow_ram(const struct mem_controller *ctrl)
+{
+ u8 shadowreg;
+
+ pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0x2a);
+
+ /* 0xf0000-0xfffff - ACPI tables */
+ shadowreg = pci_read_config8(PCI_DEV(0, 0, 3), 0x83);
+ shadowreg |= 0x30;
+ pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg);
+}
+
+static void main(unsigned long bist)
+{
+ /* Set statically so it should work with cx700 as well */
+ static const struct mem_controller cx700[] = {
+ {
+ .channel0 = {0x50, 0x51},
+ },
+ };
+
+ enable_smbus();
+
+ enable_cx700_serial();
+ uart_init();
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ enable_mainboard_devices();
+
+ /* Allows access to all northbridge devices */
+ pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01);
+
+ sdram_set_registers(cx700);
+ enable_shadow_ram(cx700);
+ sdram_enable(cx700);
+ copy_and_run(0);
+}
+
+void amd64_main(unsigned long bist) {
+ main(bist);
+}
diff --git a/src/mainboard/via/vt8454c/chip.h b/src/mainboard/via/vt8454c/chip.h
new file mode 100644
index 0000000000..ac8c5eb62d
--- /dev/null
+++ b/src/mainboard/via/vt8454c/chip.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {
+ int nothing;
+};
diff --git a/src/mainboard/via/vt8454c/cmos.layout b/src/mainboard/via/vt8454c/cmos.layout
new file mode 100644
index 0000000000..e80bb94d9d
--- /dev/null
+++ b/src/mainboard/via/vt8454c/cmos.layout
@@ -0,0 +1,67 @@
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2009 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+entries
+
+#start-bit length config config-ID name
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+1008 16 h 0 check_sum
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+
+checksums
+
+checksum 392 1007 1008
+
+
diff --git a/src/mainboard/via/vt8454c/debug.c b/src/mainboard/via/vt8454c/debug.c
new file mode 100644
index 0000000000..54d8cf34e5
--- /dev/null
+++ b/src/mainboard/via/vt8454c/debug.c
@@ -0,0 +1,108 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+static void print_debug_pci_dev(unsigned dev)
+{
+ print_debug("PCI: ");
+ print_debug_hex8((dev >> 16) & 0xff);
+ print_debug_char(':');
+ print_debug_hex8((dev >> 11) & 0x1f);
+ print_debug_char('.');
+ print_debug_hex8((dev >> 8) & 7);
+}
+
+static void print_pci_devices(void)
+{
+ device_t dev;
+ for (dev = PCI_DEV(0, 0, 0);
+ dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) {
+ u32 id;
+ id = pci_read_config32(dev, PCI_VENDOR_ID);
+ if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff)
+ || (((id >> 16) & 0xffff) == 0xffff)
+ || (((id >> 16) & 0xffff) == 0x0000)) {
+ continue;
+ }
+ print_debug_pci_dev(dev);
+ print_debug("\r\n");
+ }
+}
+
+static void dump_pci_device(unsigned dev)
+{
+ int i;
+ print_debug_pci_dev(dev);
+ print_debug("\r\n");
+
+ for (i = 0; i <= 255; i++) {
+ unsigned char val;
+ if ((i & 0x0f) == 0) {
+ print_debug_hex8(i);
+ print_debug_char(':');
+ }
+ val = pci_read_config8(dev, i);
+ print_debug_char(' ');
+ print_debug_hex8(val);
+ if ((i & 0x0f) == 0x0f) {
+ print_debug("\r\n");
+ }
+ }
+}
+
+static void dump_pci_devices(void)
+{
+ device_t dev;
+ for (dev = PCI_DEV(0, 0, 0);
+ dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) {
+ u32 id;
+ id = pci_read_config32(dev, PCI_VENDOR_ID);
+ if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff)
+ || (((id >> 16) & 0xffff) == 0xffff)
+ || (((id >> 16) & 0xffff) == 0x0000)) {
+ continue;
+ }
+ dump_pci_device(dev);
+ }
+}
+
+
+static void dump_io_resources(unsigned port)
+{
+
+ int i;
+ udelay(2000);
+ print_debug_hex16(port);
+ print_debug(":\r\n");
+ for (i = 0; i < 256; i++) {
+ u8 val;
+ if ((i & 0x0f) == 0) {
+ print_debug_hex8(i);
+ print_debug_char(':');
+ }
+ val = inb(port);
+ print_debug_char(' ');
+ print_debug_hex8(val);
+ if ((i & 0x0f) == 0x0f) {
+ print_debug("\r\n");
+ }
+ port++;
+ }
+}
diff --git a/src/mainboard/via/vt8454c/dmi.h b/src/mainboard/via/vt8454c/dmi.h
new file mode 100644
index 0000000000..17563f24c8
--- /dev/null
+++ b/src/mainboard/via/vt8454c/dmi.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#define DMI_TABLE_SIZE 0x55
+
+static u8 dmi_table[DMI_TABLE_SIZE] = {
+ 0x5f, 0x53, 0x4d, 0x5f, 0x2d, 0x1f, 0x02, 0x03, 0x51, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0xeb, 0xa8, 0x03, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00,
+ 0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00,
+ 0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20,
+ 0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32,
+ 0x30, 0x30, 0x38, 0x00, 0x00
+};
diff --git a/src/mainboard/via/vt8454c/dsdt.dsl b/src/mainboard/via/vt8454c/dsdt.dsl
new file mode 100644
index 0000000000..150fbcf5f9
--- /dev/null
+++ b/src/mainboard/via/vt8454c/dsdt.dsl
@@ -0,0 +1,341 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001)
+{
+ /*
+ * Define the main processor
+ */
+ Scope (\_PR)
+ {
+ Processor (\_PR.CPU0, 0x00, 0x00000410, 0x06) {}
+ }
+
+ /* For now only define 2 power states:
+ * - S0 which is fully on
+ * - S5 which is soft off
+ * any others would involve declaring the wake up methods
+ */
+ Name (\_S0, Package () {0x00, 0x00, 0x00, 0x00 })
+ Name (\_S5, Package () {0x02, 0x02, 0x00, 0x00 })
+
+ Scope (\) {
+ Name (PICF , 0) // Global flag indicating whether to use PIC or APIC mode
+ Method ( _PIC,1) // The OS is calling this
+ {
+ Store( Arg0 , PICF)
+ }
+ } // end of \ scope
+
+ /* Root of the bus hierarchy */
+ Scope (\_SB)
+ {
+ /* Define how interrupt Link A is plumbed in */
+ Device (LNKA)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x01)
+
+ /* Status - always return ready */
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0B)
+ }
+
+ /* Current Resources - return irq set up in BIOS */
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (CRSP, ResourceTemplate () {
+ IRQ (Level, ActiveLow, Shared) {11}
+ })
+ Name (CRSA, ResourceTemplate () {
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {16}
+ })
+
+ If (LNot (PICF)) {
+ Return (CRSP)
+ } Else {
+ Return (CRSA)
+ }
+ }
+ /* Possible Resources - return the range of irqs
+ * we are using for PCI - only here to keep Linux ACPI
+ * happy
+ */
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (PRSP, ResourceTemplate () {
+ IRQ (Level, ActiveLow, Shared) {3,4,6,7,10,11,12}
+ })
+ Name (PRSA, ResourceTemplate () {
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {16,17,18,19,20,21,22,23}
+ })
+
+ If (LNot (PICF)) {
+ Return (PRSP)
+ } Else {
+ Return (PRSA)
+ }
+
+ }
+ /* Set Resources - dummy function to keep Linux ACPI happy
+ * Linux is more than happy not to tinker with irq
+ * assignments as long as the CRS and STA functions
+ * return good values
+ */
+ Method (_SRS, 1, NotSerialized ) {}
+ /* Disable - dummy function to keep Linux ACPI happy */
+ Method (_DIS, 0, NotSerialized ) {}
+
+ } // End of LNKA
+
+ /* Define how interrupt Link B is plumbed in */
+ Device (LNKB)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x02)
+
+ /* Status - always return ready */
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0B)
+ }
+
+ /* Current Resources - return irq set up in BIOS */
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (CRSP, ResourceTemplate () {
+ IRQ (Level, ActiveLow, Shared) {11}
+ })
+ Name (CRSA, ResourceTemplate () {
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {17}
+ })
+
+ If (LNot (PICF)) {
+ Return (CRSP)
+ } Else {
+ Return (CRSA)
+ }
+ }
+ /* Possible Resources - return the range of irqs
+ * we are using for PCI - only here to keep Linux ACPI
+ * happy
+ */
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (PRSP, ResourceTemplate () {
+ IRQ (Level, ActiveLow, Shared) {3,4,6,7,10,11,12}
+ })
+ Name (PRSA, ResourceTemplate () {
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {16,17,18,19,20,21,22,23}
+ })
+
+ If (LNot (PICF)) {
+ Return (PRSP)
+ } Else {
+ Return (PRSA)
+ }
+
+ }
+
+ /* Set Resources - dummy function to keep Linux ACPI happy
+ * Linux is more than happy not to tinker with irq
+ * assignments as long as the CRS and STA functions
+ * return good values
+ */
+ Method (_SRS, 1, NotSerialized ) {}
+ /* Disable - dummy function to keep Linux ACPI happy */
+ Method (_DIS, 0, NotSerialized ) {}
+
+ } // End of LNKB
+
+ /* Define how interrupt Link C is plumbed in */
+ Device (LNKC)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x03)
+
+ /* Status - always return ready */
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0B)
+ }
+
+ /* Current Resources - return irq set up in BIOS */
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (CRSP, ResourceTemplate () {
+ IRQ (Level, ActiveLow, Shared) {10}
+ })
+ Name (CRSA, ResourceTemplate () {
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {18}
+ })
+
+ If (LNot (PICF)) {
+ Return (CRSP)
+ } Else {
+ Return (CRSA)
+ }
+ }
+ /* Possible Resources - return the range of irqs
+ * we are using for PCI - only here to keep Linux ACPI
+ * happy
+ */
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (PRSP, ResourceTemplate () {
+ IRQ (Level, ActiveLow, Shared) {3,4,6,7,10,11,12}
+ })
+ Name (PRSA, ResourceTemplate () {
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {16,17,18,19,20,21,22,23}
+ })
+
+ If (LNot (PICF)) {
+ Return (PRSP)
+ } Else {
+ Return (PRSA)
+ }
+
+ }
+
+ /* Set Resources - dummy function to keep Linux ACPI happy
+ * Linux is more than happy not to tinker with irq
+ * assignments as long as the CRS and STA functions
+ * return good values
+ */
+ Method (_SRS, 1, NotSerialized ) {}
+ /* Disable - dummy function to keep Linux ACPI happy */
+ Method (_DIS, 0, NotSerialized ) {}
+
+ } // End of LNKC
+
+ /* Define how interrupt Link D is plumbed in */
+ Device (LNKD)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x04)
+
+ /* Status - always return ready */
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0B)
+ }
+
+ /* Current Resources - return irq set up in BIOS */
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (CRSP, ResourceTemplate () {
+ IRQ (Level, ActiveLow, Shared) {10}
+ })
+ Name (CRSA, ResourceTemplate () {
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {19}
+ })
+
+ If (LNot (PICF)) {
+ Return (CRSP)
+ } Else {
+ Return (CRSA)
+ }
+ }
+ /* Possible Resources - return the range of irqs
+ * we are using for PCI - only here to keep Linux ACPI
+ * happy
+ */
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (PRSP, ResourceTemplate () {
+ IRQ (Level, ActiveLow, Shared) {3,4,6,7,10,11,12}
+ })
+ Name (PRSA, ResourceTemplate () {
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {16,17,18,19,20,21,22,23}
+ })
+
+ If (LNot (PICF)) {
+ Return (PRSP)
+ } Else {
+ Return (PRSA)
+ }
+
+ }
+
+ /* Set Resources - dummy function to keep Linux ACPI happy
+ * Linux is more than happy not to tinker with irq
+ * assignments as long as the CRS and STA functions
+ * return good values
+ */
+ Method (_SRS, 1, NotSerialized ) {}
+ /* Disable - dummy function to keep Linux ACPI happy */
+ Method (_DIS, 0, NotSerialized ) {}
+
+ } // End of LNKD
+
+ /* PCI Root Bridge */
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A08"))
+ Name (_CID, EisaId ("PNP0A03"))
+ Name (_ADR, 0x00)
+ Name (_UID, 0x00)
+ Name (_BBN, 0x00)
+
+ // Mainboard specific IRQ routing
+ Include ("irq.dsl")
+
+ /* PCI Routing Table */
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LNot (PICF))
+ {
+ Return (PICM)
+ }
+ Else
+ {
+ Return (APIC)
+ }
+ }
+
+ Device (P2PB) /* PCI to PCI bridge */
+ {
+ Name (_ADR, 0x00130001)
+
+ Include ("irq-p2p-bridge.dsl")
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LNot (PICF))
+ {
+ Return (PICM)
+ }
+ Else
+ {
+ Return (APIC)
+ }
+ }
+ /* Status - always return ready */
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+ }
+ } // End of PCI0
+ } // End of _SB
+} // End of Definition Block
+
diff --git a/src/mainboard/via/vt8454c/fadt.c b/src/mainboard/via/vt8454c/fadt.c
new file mode 100644
index 0000000000..3954974075
--- /dev/null
+++ b/src/mainboard/via/vt8454c/fadt.c
@@ -0,0 +1,156 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <arch/acpi.h>
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+
+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = 244;
+ header->revision = 1;
+ memcpy(header->oem_id, "CX700 ", 6);
+ memcpy(header->oem_table_id, "COREBOOT", 8);
+ memcpy(header->asl_compiler_id, "CORE", 4);
+ header->asl_compiler_revision = 0;
+
+ fadt->firmware_ctrl = (unsigned long) facs;
+ fadt->dsdt = (unsigned long) dsdt;
+ fadt->preferred_pm_profile = 0;
+ fadt->sci_int = 0x9;
+ fadt->smi_cmd = 0x0;
+ fadt->acpi_enable = 0xA1;
+ fadt->acpi_disable = 0xA0;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = 0x0;
+
+ fadt->pm1a_evt_blk = 0x400;
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = 0x404;
+ fadt->pm1b_cnt_blk = 0x0;
+ fadt->pm2_cnt_blk = 0x22;
+ fadt->pm_tmr_blk = 0x408;
+ fadt->gpe0_blk = 0x420;
+ fadt->gpe1_blk = 0x450;
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm2_cnt_len = 1;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 4;
+ fadt->gpe1_blk_len = 4;
+ fadt->gpe1_base = 0x10;
+ fadt->cst_cnt = 0;
+ fadt->p_lvl2_lat = 101;
+ fadt->p_lvl3_lat = 1001;
+ fadt->flush_size = 0;
+ fadt->flush_stride = 0;
+ fadt->duty_offset = 0;
+ fadt->duty_width = 1;
+ fadt->day_alrm = 0x7d;
+ fadt->mon_alrm = 0x7e;
+ fadt->century = 0x32;
+ fadt->iapc_boot_arch = 0x0;
+ fadt->flags = 0x44a5;
+
+ fadt->reset_reg.space_id = 0;
+ fadt->reset_reg.bit_width = 0;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.resv = 0;
+ fadt->reset_reg.addrl = 0x0;
+ fadt->reset_reg.addrh = 0x0;
+
+ fadt->reset_value = 0;
+ fadt->x_firmware_ctl_l = (unsigned long) facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (unsigned long) dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = 4;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.resv = 0;
+ fadt->x_pm1a_evt_blk.addrl = 0x400;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+
+ fadt->x_pm1b_evt_blk.space_id = 1;
+ fadt->x_pm1b_evt_blk.bit_width = 4;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.resv = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = 2;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.resv = 0;
+ fadt->x_pm1a_cnt_blk.addrl = 0x404;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+
+ fadt->x_pm1b_cnt_blk.space_id = 1;
+ fadt->x_pm1b_cnt_blk.bit_width = 2;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.resv = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = 0;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.resv = 0;
+ fadt->x_pm2_cnt_blk.addrl = 0x0;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = 4;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.resv = 0;
+ fadt->x_pm_tmr_blk.addrl = 0x408;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+
+ fadt->x_gpe0_blk.space_id = 1;
+ fadt->x_gpe0_blk.bit_width = 0;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.resv = 0;
+ fadt->x_gpe0_blk.addrl = 0x420;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+
+ fadt->x_gpe1_blk.space_id = 1;
+ fadt->x_gpe1_blk.bit_width = 0;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.resv = 0;
+ fadt->x_gpe1_blk.addrl = 0x0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum =
+ acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
+
+}
diff --git a/src/mainboard/via/vt8454c/irq-p2p-bridge.dsl b/src/mainboard/via/vt8454c/irq-p2p-bridge.dsl
new file mode 100644
index 0000000000..4a294bcbaa
--- /dev/null
+++ b/src/mainboard/via/vt8454c/irq-p2p-bridge.dsl
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Name (PICM, Package () {
+ // _ADR PIN SRC IDX
+
+ Package () { 0x0003FFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x0003FFFF, 0x01, LNKB, 0x00 },
+ Package () { 0x0003FFFF, 0x02, LNKC, 0x00 },
+ Package () { 0x0003FFFF, 0x03, LNKD, 0x00 },
+
+ Package () { 0x0004FFFF, 0x00, LNKB, 0x00 },
+ Package () { 0x0004FFFF, 0x01, LNKC, 0x00 },
+ Package () { 0x0004FFFF, 0x02, LNKD, 0x00 },
+ Package () { 0x0004FFFF, 0x03, LNKA, 0x00 },
+
+ Package () { 0x0005FFFF, 0x00, LNKC, 0x00 },
+ Package () { 0x0005FFFF, 0x01, LNKD, 0x00 },
+ Package () { 0x0005FFFF, 0x02, LNKA, 0x00 },
+ Package () { 0x0005FFFF, 0x03, LNKB, 0x00 },
+
+ Package () { 0x0006FFFF, 0x00, LNKD, 0x00 },
+ Package () { 0x0006FFFF, 0x01, LNKA, 0x00 },
+ Package () { 0x0006FFFF, 0x02, LNKB, 0x00 },
+ Package () { 0x0006FFFF, 0x03, LNKC, 0x00 },
+
+ Package () { 0x0007FFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x0007FFFF, 0x01, LNKB, 0x00 },
+ Package () { 0x0007FFFF, 0x02, LNKC, 0x00 },
+ Package () { 0x0007FFFF, 0x03, LNKD, 0x00 },
+
+ Package () { 0x0008FFFF, 0x00, LNKB, 0x00 },
+ Package () { 0x0008FFFF, 0x01, LNKC, 0x00 },
+ Package () { 0x0008FFFF, 0x02, LNKD, 0x00 },
+ Package () { 0x0008FFFF, 0x03, LNKA, 0x00 },
+})
+
+Name (APIC, Package () {
+ Package () { 0x0003FFFF, 0x00, 0x00, 0x10 },
+ Package () { 0x0003FFFF, 0x01, 0x00, 0x11 },
+ Package () { 0x0003FFFF, 0x02, 0x00, 0x12 },
+ Package () { 0x0003FFFF, 0x03, 0x00, 0x13 },
+
+ Package () { 0x0004FFFF, 0x00, 0x00, 0x11 },
+ Package () { 0x0004FFFF, 0x01, 0x00, 0x12 },
+ Package () { 0x0004FFFF, 0x02, 0x00, 0x13 },
+ Package () { 0x0004FFFF, 0x03, 0x00, 0x10 },
+
+ Package () { 0x0005FFFF, 0x00, 0x00, 0x12 },
+ Package () { 0x0005FFFF, 0x01, 0x00, 0x13 },
+ Package () { 0x0005FFFF, 0x02, 0x00, 0x10 },
+ Package () { 0x0005FFFF, 0x03, 0x00, 0x11 },
+
+ Package () { 0x0006FFFF, 0x00, 0x00, 0x13 },
+ Package () { 0x0006FFFF, 0x01, 0x00, 0x10 },
+ Package () { 0x0006FFFF, 0x02, 0x00, 0x11 },
+ Package () { 0x0006FFFF, 0x03, 0x00, 0x12 },
+
+ Package () { 0x0007FFFF, 0x00, 0x00, 0x10 },
+ Package () { 0x0007FFFF, 0x01, 0x00, 0x11 },
+ Package () { 0x0007FFFF, 0x02, 0x00, 0x12 },
+ Package () { 0x0007FFFF, 0x03, 0x00, 0x13 },
+
+ Package () { 0x0008FFFF, 0x00, 0x00, 0x11 },
+ Package () { 0x0008FFFF, 0x01, 0x00, 0x12 },
+ Package () { 0x0008FFFF, 0x02, 0x00, 0x13 },
+ Package () { 0x0008FFFF, 0x03, 0x00, 0x10 },
+})
+
+
diff --git a/src/mainboard/via/vt8454c/irq.dsl b/src/mainboard/via/vt8454c/irq.dsl
new file mode 100644
index 0000000000..63e64e61c0
--- /dev/null
+++ b/src/mainboard/via/vt8454c/irq.dsl
@@ -0,0 +1,143 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Name (PICM, Package () {
+ // _ADR PIN SRC IDX
+
+ Package () { 0x0001FFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x0001FFFF, 0x01, LNKB, 0x00 },
+ Package () { 0x0001FFFF, 0x02, LNKC, 0x00 },
+ Package () { 0x0001FFFF, 0x03, LNKD, 0x00 },
+
+ Package () { 0x0008FFFF, 0x00, LNKB, 0x00 },
+ Package () { 0x0008FFFF, 0x01, LNKC, 0x00 },
+ Package () { 0x0008FFFF, 0x02, LNKD, 0x00 },
+ Package () { 0x0008FFFF, 0x03, LNKA, 0x00 },
+
+ Package () { 0x0009FFFF, 0x00, LNKC, 0x00 },
+ Package () { 0x0009FFFF, 0x01, LNKD, 0x00 },
+ Package () { 0x0009FFFF, 0x02, LNKA, 0x00 },
+ Package () { 0x0009FFFF, 0x03, LNKB, 0x00 },
+
+ Package () { 0x000AFFFF, 0x00, LNKD, 0x00 },
+ Package () { 0x000AFFFF, 0x01, LNKA, 0x00 },
+ Package () { 0x000AFFFF, 0x02, LNKB, 0x00 },
+ Package () { 0x000AFFFF, 0x03, LNKC, 0x00 },
+
+ Package () { 0x000BFFFF, 0x00, LNKD, 0x00 },
+ Package () { 0x000BFFFF, 0x01, LNKA, 0x00 },
+ Package () { 0x000BFFFF, 0x02, LNKB, 0x00 },
+ Package () { 0x000BFFFF, 0x03, LNKC, 0x00 },
+
+ Package () { 0x000CFFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x000CFFFF, 0x01, LNKB, 0x00 },
+ Package () { 0x000CFFFF, 0x02, LNKC, 0x00 },
+ Package () { 0x000CFFFF, 0x03, LNKD, 0x00 },
+
+ Package () { 0x000DFFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x000DFFFF, 0x01, LNKB, 0x00 },
+ Package () { 0x000DFFFF, 0x02, LNKC, 0x00 },
+ Package () { 0x000DFFFF, 0x03, LNKD, 0x00 },
+
+ Package () { 0x000FFFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x000FFFFF, 0x01, LNKB, 0x00 },
+ Package () { 0x000FFFFF, 0x02, LNKC, 0x00 },
+ Package () { 0x000FFFFF, 0x03, LNKD, 0x00 },
+
+ /* USB controller */
+ Package () { 0x0010FFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x0010FFFF, 0x01, LNKB, 0x00 },
+ Package () { 0x0010FFFF, 0x02, LNKC, 0x00 },
+ Package () { 0x0010FFFF, 0x03, LNKD, 0x00 },
+
+ Package () { 0x0011FFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x0011FFFF, 0x01, LNKB, 0x00 },
+ Package () { 0x0011FFFF, 0x02, LNKC, 0x00 },
+ Package () { 0x0011FFFF, 0x03, LNKD, 0x00 },
+
+ Package () { 0x0012FFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x0012FFFF, 0x01, LNKB, 0x00 },
+ Package () { 0x0012FFFF, 0x02, LNKC, 0x00 },
+ Package () { 0x0012FFFF, 0x03, LNKD, 0x00 }
+})
+
+Name (APIC, Package () {
+ Package () { 0x0001FFFF, 0x00, 0x00, 0x10 },
+ Package () { 0x0001FFFF, 0x01, 0x00, 0x11 },
+ Package () { 0x0001FFFF, 0x02, 0x00, 0x12 },
+ Package () { 0x0001FFFF, 0x03, 0x00, 0x13 },
+
+ Package () { 0x0008FFFF, 0x00, 0x00, 0x11 },
+ Package () { 0x0008FFFF, 0x01, 0x00, 0x12 },
+ Package () { 0x0008FFFF, 0x02, 0x00, 0x13 },
+ Package () { 0x0008FFFF, 0x03, 0x00, 0x10 },
+
+ Package () { 0x0009FFFF, 0x00, 0x00, 0x12 },
+ Package () { 0x0009FFFF, 0x01, 0x00, 0x13 },
+ Package () { 0x0009FFFF, 0x02, 0x00, 0x10 },
+ Package () { 0x0009FFFF, 0x03, 0x00, 0x11 },
+
+ Package () { 0x000AFFFF, 0x00, 0x00, 0x13 },
+ Package () { 0x000AFFFF, 0x01, 0x00, 0x10 },
+ Package () { 0x000AFFFF, 0x02, 0x00, 0x11 },
+ Package () { 0x000AFFFF, 0x03, 0x00, 0x12 },
+
+ Package () { 0x000BFFFF, 0x00, 0x00, 0x13 },
+ Package () { 0x000BFFFF, 0x01, 0x00, 0x10 },
+ Package () { 0x000BFFFF, 0x02, 0x00, 0x11 },
+ Package () { 0x000BFFFF, 0x03, 0x00, 0x12 },
+
+ Package () { 0x000CFFFF, 0x00, 0x00, 0x10 },
+ Package () { 0x000CFFFF, 0x01, 0x00, 0x11 },
+ Package () { 0x000CFFFF, 0x02, 0x00, 0x12 },
+ Package () { 0x000CFFFF, 0x03, 0x00, 0x13 },
+
+ Package () { 0x000DFFFF, 0x00, 0x00, 0x10 },
+ Package () { 0x000DFFFF, 0x01, 0x00, 0x11 },
+ Package () { 0x000DFFFF, 0x02, 0x00, 0x12 },
+ Package () { 0x000DFFFF, 0x03, 0x00, 0x13 },
+
+ Package () { 0x000FFFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x000FFFFF, 0x01, LNKA, 0x00 },
+ Package () { 0x000FFFFF, 0x02, LNKA, 0x00 },
+ Package () { 0x000FFFFF, 0x03, LNKA, 0x00 },
+
+ /* USB controller. Hardwired in internal
+ APIC mode, see PM pg. 137,
+ "miscellaneous controls", footnote to
+ "IDE interrupt select" */
+ Package () { 0x0010FFFF, 0x00, 0x00, 0x14 },
+ Package () { 0x0010FFFF, 0x01, 0x00, 0x16 },
+ Package () { 0x0010FFFF, 0x02, 0x00, 0x15 },
+ Package () { 0x0010FFFF, 0x03, 0x00, 0x17 },
+
+ Package () { 0x0011FFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x0011FFFF, 0x01, LNKB, 0x00 },
+ Package () { 0x0011FFFF, 0x02, LNKC, 0x00 },
+ Package () { 0x0011FFFF, 0x03, LNKD, 0x00 },
+
+ Package () { 0x0012FFFF, 0x00, LNKD, 0x00 },
+ Package () { 0x0012FFFF, 0x01, LNKD, 0x00 },
+ Package () { 0x0012FFFF, 0x02, LNKD, 0x00 },
+ Package () { 0x0012FFFF, 0x03, LNKD, 0x00 },
+})
+
+
diff --git a/src/mainboard/via/vt8454c/irq_tables.c b/src/mainboard/via/vt8454c/irq_tables.c
new file mode 100644
index 0000000000..40d1ebb691
--- /dev/null
+++ b/src/mainboard/via/vt8454c/irq_tables.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32 + 16 * IRQ_SLOT_COUNT, /* There can be total 15 devices on the bus */
+ 0x00, /* Where the interrupt router lies (bus) */
+ (0x11 << 3) | 0x0, /* Where the interrupt router lies (dev) */
+ 0xc20, /* IRQs devoted exclusively to PCI usage */
+ 0x1106, /* Vendor */
+ 0x596, /* Device */
+ 0, /* Crap (miniport) */
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
+ 0x84, /* u8 checksum. This has to be set to some
+ value that would give 0 after the sum of all
+ bytes for this structure (including checksum) */
+ {
+ /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00, (0x08 << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x1, 0x0},
+ {0x00, (0x09 << 3) | 0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0x0deb8}}, 0x2, 0x0},
+ {0x00, (0x0a << 3) | 0x0, {{0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x3, 0x0},
+ {0x02, (0x03 << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x4, 0x0},
+ {0x02, (0x04 << 3) | 0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0x0deb8}}, 0x5, 0x0},
+ {0x02, (0x05 << 3) | 0x0, {{0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x6, 0x0},
+ {0x02, (0x06 << 3) | 0x0, {{0x05, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0x0deb8}}, 0x7, 0x0},
+ {0x02, (0x07 << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x8, 0x0},
+ {0x02, (0x08 << 3) | 0x0, {{0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x9, 0x0},
+ {0x00, (0x01 << 3) | 0x0, {{0x02, 0xdeb8}, {0x02, 0xdeb8}, {0x02, 0xdeb8}, {0x02, 0x0deb8}}, 0x0, 0x0},
+ {0x80, (0x01 << 3) | 0x0, {{0x02, 0xdeb8}, {0x02, 0xdeb8}, {0x02, 0xdeb8}, {0x02, 0x0deb8}}, 0x0, 0x0},
+ {0x00, (0x11 << 3) | 0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0},
+ {0x00, (0x0f << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0},
+ {0x00, (0x01 << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0},
+ {0x00, (0x10 << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0}
+ }
+};
+
+inline unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr);
+}
diff --git a/src/mainboard/via/vt8454c/mainboard.c b/src/mainboard/via/vt8454c/mainboard.c
new file mode 100644
index 0000000000..e931ccdafb
--- /dev/null
+++ b/src/mainboard/via/vt8454c/mainboard.c
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("VIA VT8454c Mainboard")
+};
+
diff --git a/src/mainboard/via/vt8454c/mptable.c b/src/mainboard/via/vt8454c/mptable.c
new file mode 100644
index 0000000000..e060d67ddd
--- /dev/null
+++ b/src/mainboard/via/vt8454c/mptable.c
@@ -0,0 +1,104 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/smp/mpspec.h>
+#include <cpu/x86/lapic.h>
+#include <console/console.h>
+#include <string.h>
+#include <stdint.h>
+
+void *smp_write_config_table(void *v)
+{
+ static const char sig[4] = MPC_SIGNATURE;
+ static const char oem[8] = "COREBOOT";
+ static const char productid[12] = "VIA VT8454C ";
+ struct mp_config_table *mc;
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+ memset(mc, 0, sizeof(*mc));
+
+ memcpy(mc->mpc_signature, sig, sizeof(sig));
+ mc->mpc_length = sizeof(*mc); /* initially just the header */
+ mc->mpc_spec = 0x04;
+ mc->mpc_checksum = 0; /* not yet computed */
+ memcpy(mc->mpc_oem, oem, sizeof(oem));
+ memcpy(mc->mpc_productid, productid, sizeof(productid));
+ mc->mpc_oemptr = 0;
+ mc->mpc_oemsize = 0;
+ mc->mpc_entry_count = 0; /* No entries yet... */
+ mc->mpc_lapic = LAPIC_ADDR;
+ mc->mpe_length = 0;
+ mc->mpe_checksum = 0;
+ mc->reserved = 0;
+
+ smp_write_processors(mc);
+
+ /*Bus: Bus ID Type */
+ smp_write_bus(mc, 0, "PCI ");
+ smp_write_bus(mc, 1, "PCI ");
+ smp_write_bus(mc, 2, "PCI ");
+ smp_write_bus(mc, 128, "PCI ");
+ smp_write_bus(mc, 129, "ISA ");
+
+ /* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, 2, 17, 0xfec00000);
+
+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x40, 0x2, 0x14);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x41, 0x2, 0x16);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x42, 0x2, 0x15);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x43, 0x2, 0x17);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x80, 0x4, 0x2, 0x11);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x11);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x2, 0x10, 0x2, 0x11);
+ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x81, 0x0, 0x2, 0x0);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x81, 0x1, 0x2, 0x1);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x81, 0x0, 0x2, 0x2);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x81, 0x3, 0x2, 0x3);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x81, 0x4, 0x2, 0x4);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x81, 0x6, 0x2, 0x6);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x81, 0x7, 0x2, 0x7);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x81, 0x8, 0x2, 0x8);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x81, 0x9, 0x2, 0x9);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x81, 0xc, 0x2, 0xc);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x81, 0xd, 0x2, 0xd);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x81, 0xe, 0x2, 0xe);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x81, 0xf, 0x2, 0xf);
+
+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0);
+ smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1);
+
+ /* Compute the checksums */
+ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+ mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+ printk_debug("Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
+ return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr);
+ return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/via/vt8454c/reset.c b/src/mainboard/via/vt8454c/reset.c
new file mode 100644
index 0000000000..e1d879fa5a
--- /dev/null
+++ b/src/mainboard/via/vt8454c/reset.c
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include "arch/romcc_io.h"
+
+void hard_reset(void)
+{
+ set_bios_reset();
+ outb(0x06, 0x0cf9);
+}
generated by cgit v1.2.3 (git 2.39.1) at 2024-08-21 16:21:33 +0000