summaryrefslogtreecommitdiff
path: root/src/mainboard/tyan
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard/tyan')
-rw-r--r--src/mainboard/tyan/s2912_fam10/romstage.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index 976f691531..d809ff26f7 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -77,7 +77,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/mcp55/early_setup_car.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
+
+#if CONFIG_UPDATE_CPU_MICROCODE
#include "cpu/amd/model_10xxx/update_microcode.c"
+#endif
+
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
@@ -153,7 +157,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
+#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
+#endif
post_code(0x33);
cpuSetAMDMSR();