diff options
Diffstat (limited to 'src/mainboard/tyan')
28 files changed, 184 insertions, 184 deletions
diff --git a/src/mainboard/tyan/s1846/Options.lb b/src/mainboard/tyan/s1846/Options.lb index 340325f42d..b0fa5250d2 100644 --- a/src/mainboard/tyan/s1846/Options.lb +++ b/src/mainboard/tyan/s1846/Options.lb @@ -30,7 +30,7 @@ uses IRQ_SLOT_COUNT uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE diff --git a/src/mainboard/tyan/s2735/Config.lb b/src/mainboard/tyan/s2735/Config.lb index 46f1b3821f..2506906222 100644 --- a/src/mainboard/tyan/s2735/Config.lb +++ b/src/mainboard/tyan/s2735/Config.lb @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,19 +12,19 @@ end ## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default CONFIG_ROM_PAYLOAD = 1 ## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) ## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -90,7 +90,7 @@ end end ## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -107,7 +107,7 @@ end ## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -137,7 +137,7 @@ mainboardinit cpu/x86/car/cache_as_ram.inc end ### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ### diff --git a/src/mainboard/tyan/s2735/Options.lb b/src/mainboard/tyan/s2735/Options.lb index e151c7ed92..447b5513ea 100644 --- a/src/mainboard/tyan/s2735/Options.lb +++ b/src/mainboard/tyan/s2735/Options.lb @@ -36,7 +36,7 @@ uses MAINBOARD_VENDOR uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses CONFIG_GDB_STUB uses CROSS_COMPILE @@ -87,7 +87,7 @@ default FALLBACK_SIZE=131072 default HAVE_FALLBACK_BOOT=1 ## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1 @@ -114,7 +114,7 @@ default HAVE_MP_TABLE=1 default HAVE_OPTION_TABLE=1 ## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -162,10 +162,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2735 ### -### LinuxBIOS layout values +### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 ## @@ -184,7 +184,7 @@ default HEAP_SIZE=0x4000 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE ## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000 @@ -233,7 +233,7 @@ default TTYS0_BASE=0x3f8 default TTYS0_LCS=0x3 ## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately diff --git a/src/mainboard/tyan/s2735/cache_as_ram_auto.c b/src/mainboard/tyan/s2735/cache_as_ram_auto.c index 80af842f4f..797ff62b80 100644 --- a/src/mainboard/tyan/s2735/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2735/cache_as_ram_auto.c @@ -259,7 +259,7 @@ cpu_reset_x: print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n"); #endif - /*copy and execute linuxbios_ram */ + /*copy and execute coreboot_ram */ copy_and_run(new_cpu_reset); /* We will not return */ } diff --git a/src/mainboard/tyan/s2850/Config.lb b/src/mainboard/tyan/s2850/Config.lb index e6ca2c304b..3c0c7d2d96 100644 --- a/src/mainboard/tyan/s2850/Config.lb +++ b/src/mainboard/tyan/s2850/Config.lb @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@ end ## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) ## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) ## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -90,7 +90,7 @@ end end ## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -110,7 +110,7 @@ if USE_DCACHE_RAM end ## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -140,7 +140,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc end ### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ### diff --git a/src/mainboard/tyan/s2850/Options.lb b/src/mainboard/tyan/s2850/Options.lb index d3f95014f3..cf1298e9c8 100644 --- a/src/mainboard/tyan/s2850/Options.lb +++ b/src/mainboard/tyan/s2850/Options.lb @@ -35,7 +35,7 @@ uses MAINBOARD_VENDOR uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -83,7 +83,7 @@ default FALLBACK_SIZE=0x40000 default HAVE_FALLBACK_BOOT=1 ## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1 @@ -105,7 +105,7 @@ default HAVE_MP_TABLE=1 default HAVE_OPTION_TABLE=1 ## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -153,10 +153,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2850 ### -### LinuxBIOS layout values +### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 ## @@ -175,7 +175,7 @@ default HEAP_SIZE=0x4000 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE ## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000 @@ -224,7 +224,7 @@ default TTYS0_BASE=0x3f8 default TTYS0_LCS=0x3 ## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately diff --git a/src/mainboard/tyan/s2875/Config.lb b/src/mainboard/tyan/s2875/Config.lb index 4f1c6e4658..74a71f15a1 100644 --- a/src/mainboard/tyan/s2875/Config.lb +++ b/src/mainboard/tyan/s2875/Config.lb @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@ end ## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) ## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) ## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -90,7 +90,7 @@ end end ## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -110,7 +110,7 @@ if USE_DCACHE_RAM end ## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -140,7 +140,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc end ### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ### diff --git a/src/mainboard/tyan/s2875/Options.lb b/src/mainboard/tyan/s2875/Options.lb index 189ca08b7d..b90d4184e2 100644 --- a/src/mainboard/tyan/s2875/Options.lb +++ b/src/mainboard/tyan/s2875/Options.lb @@ -35,7 +35,7 @@ uses MAINBOARD_VENDOR uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -84,7 +84,7 @@ default FALLBACK_SIZE=0x40000 default HAVE_FALLBACK_BOOT=1 ## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1 @@ -106,7 +106,7 @@ default HAVE_MP_TABLE=1 default HAVE_OPTION_TABLE=1 ## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -154,10 +154,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2875 ### -### LinuxBIOS layout values +### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 ## @@ -176,7 +176,7 @@ default HEAP_SIZE=0x4000 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE ## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000 @@ -225,7 +225,7 @@ default TTYS0_BASE=0x3f8 default TTYS0_LCS=0x3 ## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately diff --git a/src/mainboard/tyan/s2880/Config.lb b/src/mainboard/tyan/s2880/Config.lb index bd4289ff56..1bc7726788 100644 --- a/src/mainboard/tyan/s2880/Config.lb +++ b/src/mainboard/tyan/s2880/Config.lb @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@ end ## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) ## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) ## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -90,7 +90,7 @@ end end ## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -110,7 +110,7 @@ if USE_DCACHE_RAM end ## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -140,7 +140,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc end ### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ### diff --git a/src/mainboard/tyan/s2880/Options.lb b/src/mainboard/tyan/s2880/Options.lb index d0efa27fa4..72c40d9466 100644 --- a/src/mainboard/tyan/s2880/Options.lb +++ b/src/mainboard/tyan/s2880/Options.lb @@ -35,7 +35,7 @@ uses MAINBOARD_VENDOR uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -83,7 +83,7 @@ default FALLBACK_SIZE=0x40000 default HAVE_FALLBACK_BOOT=1 ## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1 @@ -105,7 +105,7 @@ default HAVE_MP_TABLE=1 default HAVE_OPTION_TABLE=1 ## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -153,10 +153,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2880 ### -### LinuxBIOS layout values +### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 ## @@ -175,7 +175,7 @@ default HEAP_SIZE=0x4000 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE ## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000 @@ -224,7 +224,7 @@ default TTYS0_BASE=0x3f8 default TTYS0_LCS=0x3 ## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately diff --git a/src/mainboard/tyan/s2881/Config.lb b/src/mainboard/tyan/s2881/Config.lb index 05ff5c7234..e1c42de929 100644 --- a/src/mainboard/tyan/s2881/Config.lb +++ b/src/mainboard/tyan/s2881/Config.lb @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@ end ## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) ## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) ## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -90,7 +90,7 @@ end end ## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -110,7 +110,7 @@ if USE_DCACHE_RAM end ## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -140,7 +140,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc end ### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ### diff --git a/src/mainboard/tyan/s2881/Options.lb b/src/mainboard/tyan/s2881/Options.lb index 49599aeeef..edefbbe95e 100644 --- a/src/mainboard/tyan/s2881/Options.lb +++ b/src/mainboard/tyan/s2881/Options.lb @@ -35,7 +35,7 @@ uses MAINBOARD_VENDOR uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -88,7 +88,7 @@ default FALLBACK_SIZE=0x40000 default HAVE_FALLBACK_BOOT=1 ## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1 @@ -110,7 +110,7 @@ default HAVE_MP_TABLE=1 default HAVE_OPTION_TABLE=1 ## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -170,10 +170,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2881 ### -### LinuxBIOS layout values +### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 ## @@ -192,7 +192,7 @@ default HEAP_SIZE=0x4000 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE ## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000 @@ -241,7 +241,7 @@ default TTYS0_BASE=0x3f8 default TTYS0_LCS=0x3 ## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately diff --git a/src/mainboard/tyan/s2882/Config.lb b/src/mainboard/tyan/s2882/Config.lb index 10363604ae..d883177fcc 100644 --- a/src/mainboard/tyan/s2882/Config.lb +++ b/src/mainboard/tyan/s2882/Config.lb @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@ end ## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) ## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) ## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -90,7 +90,7 @@ end end ## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -110,7 +110,7 @@ if USE_DCACHE_RAM end ## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -140,7 +140,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc end ### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ### diff --git a/src/mainboard/tyan/s2882/Options.lb b/src/mainboard/tyan/s2882/Options.lb index 1fb5694559..23b2658ed6 100644 --- a/src/mainboard/tyan/s2882/Options.lb +++ b/src/mainboard/tyan/s2882/Options.lb @@ -35,7 +35,7 @@ uses MAINBOARD_VENDOR uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -83,7 +83,7 @@ default FALLBACK_SIZE=0x40000 default HAVE_FALLBACK_BOOT=1 ## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1 @@ -105,7 +105,7 @@ default HAVE_MP_TABLE=1 default HAVE_OPTION_TABLE=1 ## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -153,10 +153,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2882 ### -### LinuxBIOS layout values +### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 ## @@ -175,7 +175,7 @@ default HEAP_SIZE=0x4000 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE ## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000 @@ -224,7 +224,7 @@ default TTYS0_BASE=0x3f8 default TTYS0_LCS=0x3 ## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately diff --git a/src/mainboard/tyan/s2885/Config.lb b/src/mainboard/tyan/s2885/Config.lb index 795485df6d..a6c0449290 100644 --- a/src/mainboard/tyan/s2885/Config.lb +++ b/src/mainboard/tyan/s2885/Config.lb @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@ end ## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) ## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) ## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -90,7 +90,7 @@ end end ## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -110,7 +110,7 @@ if USE_DCACHE_RAM end ## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -140,7 +140,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc end ### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ### diff --git a/src/mainboard/tyan/s2885/Options.lb b/src/mainboard/tyan/s2885/Options.lb index 4d339d7e93..254483d3ad 100644 --- a/src/mainboard/tyan/s2885/Options.lb +++ b/src/mainboard/tyan/s2885/Options.lb @@ -35,7 +35,7 @@ uses MAINBOARD_VENDOR uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -94,7 +94,7 @@ default FALLBACK_SIZE=0x40000 default HAVE_FALLBACK_BOOT=1 ## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1 @@ -116,7 +116,7 @@ default HAVE_MP_TABLE=1 default HAVE_OPTION_TABLE=1 ## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -180,10 +180,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2885 ### -### LinuxBIOS layout values +### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 ## @@ -202,7 +202,7 @@ default HEAP_SIZE=0x4000 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE ## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000 @@ -251,7 +251,7 @@ default TTYS0_BASE=0x3f8 default TTYS0_LCS=0x3 ## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately diff --git a/src/mainboard/tyan/s2891/Config.lb b/src/mainboard/tyan/s2891/Config.lb index 9c14f7d3ad..840d2703a6 100644 --- a/src/mainboard/tyan/s2891/Config.lb +++ b/src/mainboard/tyan/s2891/Config.lb @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,19 +12,19 @@ end ## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default CONFIG_ROM_PAYLOAD = 1 ## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) ## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -98,7 +98,7 @@ else end ## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -119,7 +119,7 @@ if USE_DCACHE_RAM end ## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -157,7 +157,7 @@ if USE_DCACHE_RAM end ### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ### diff --git a/src/mainboard/tyan/s2891/Options.lb b/src/mainboard/tyan/s2891/Options.lb index 484c84ecbe..8513e049fb 100644 --- a/src/mainboard/tyan/s2891/Options.lb +++ b/src/mainboard/tyan/s2891/Options.lb @@ -35,7 +35,7 @@ uses MAINBOARD_VENDOR uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses CONFIG_GDB_STUB uses CROSS_COMPILE @@ -101,7 +101,7 @@ default FALLBACK_SIZE=0x40000 default HAVE_FALLBACK_BOOT=1 ## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1 @@ -123,7 +123,7 @@ default HAVE_MP_TABLE=1 default HAVE_OPTION_TABLE=1 ## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -189,10 +189,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2891 ### -### LinuxBIOS layout values +### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 ## @@ -211,7 +211,7 @@ default HEAP_SIZE=0x4000 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE ## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000 @@ -260,7 +260,7 @@ default TTYS0_BASE=0x3f8 default TTYS0_LCS=0x3 ## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately diff --git a/src/mainboard/tyan/s2892/Config.lb b/src/mainboard/tyan/s2892/Config.lb index 0c3e2ae8a4..14b320075d 100644 --- a/src/mainboard/tyan/s2892/Config.lb +++ b/src/mainboard/tyan/s2892/Config.lb @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,19 +12,19 @@ end ## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default CONFIG_ROM_PAYLOAD = 1 ## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) ## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -98,7 +98,7 @@ end end ## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -118,7 +118,7 @@ if USE_DCACHE_RAM end ## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -156,7 +156,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc end ### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ### diff --git a/src/mainboard/tyan/s2892/Options.lb b/src/mainboard/tyan/s2892/Options.lb index 8646e0a04b..9dbaf9dd31 100644 --- a/src/mainboard/tyan/s2892/Options.lb +++ b/src/mainboard/tyan/s2892/Options.lb @@ -35,7 +35,7 @@ uses MAINBOARD_VENDOR uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses CONFIG_GDB_STUB uses CROSS_COMPILE @@ -94,7 +94,7 @@ default FALLBACK_SIZE=0x40000 default HAVE_FALLBACK_BOOT=1 ## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1 @@ -116,7 +116,7 @@ default HAVE_MP_TABLE=1 default HAVE_OPTION_TABLE=1 ## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -176,10 +176,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2892 ### -### LinuxBIOS layout values +### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 ## @@ -198,7 +198,7 @@ default HEAP_SIZE=0x4000 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE ## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000 @@ -247,7 +247,7 @@ default TTYS0_BASE=0x3f8 default TTYS0_LCS=0x3 ## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately diff --git a/src/mainboard/tyan/s2895/Config.lb b/src/mainboard/tyan/s2895/Config.lb index f24b07d5cb..f43ad82c4b 100644 --- a/src/mainboard/tyan/s2895/Config.lb +++ b/src/mainboard/tyan/s2895/Config.lb @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FAILOVER_IMAGE default ROM_SECTION_SIZE = FAILOVER_SIZE @@ -17,18 +17,18 @@ end ## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) ## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) ## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -102,7 +102,7 @@ else end ## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE @@ -130,7 +130,7 @@ end ## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE @@ -185,7 +185,7 @@ if USE_DCACHE_RAM end ### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ### diff --git a/src/mainboard/tyan/s2895/Options.lb b/src/mainboard/tyan/s2895/Options.lb index c27999a383..84922a399a 100644 --- a/src/mainboard/tyan/s2895/Options.lb +++ b/src/mainboard/tyan/s2895/Options.lb @@ -38,7 +38,7 @@ uses MAINBOARD_PART_NUMBER uses MAINBOARD_VENDOR uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses CONFIG_GDB_STUB uses CROSS_COMPILE @@ -106,7 +106,7 @@ default HAVE_FALLBACK_BOOT=1 default HAVE_FAILOVER_BOOT=1 ## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1 @@ -128,7 +128,7 @@ default HAVE_MP_TABLE=1 default HAVE_OPTION_TABLE=1 ## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -197,10 +197,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2895 ### -### LinuxBIOS layout values +### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 ## @@ -219,7 +219,7 @@ default HEAP_SIZE=0x4000 default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) ## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00100000 @@ -268,7 +268,7 @@ default TTYS0_BASE=0x3f8 default TTYS0_LCS=0x3 ## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately diff --git a/src/mainboard/tyan/s2912/Config.lb b/src/mainboard/tyan/s2912/Config.lb index 6cb3491c0b..a92478a805 100644 --- a/src/mainboard/tyan/s2912/Config.lb +++ b/src/mainboard/tyan/s2912/Config.lb @@ -21,7 +21,7 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FAILOVER_IMAGE default ROM_SECTION_SIZE = FAILOVER_SIZE @@ -38,18 +38,18 @@ end ## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) ## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) ## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -112,7 +112,7 @@ end ## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE @@ -140,7 +140,7 @@ end ## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE @@ -189,7 +189,7 @@ if USE_DCACHE_RAM end ### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ### diff --git a/src/mainboard/tyan/s2912/Options.lb b/src/mainboard/tyan/s2912/Options.lb index 09b647e00b..3326cdb15b 100644 --- a/src/mainboard/tyan/s2912/Options.lb +++ b/src/mainboard/tyan/s2912/Options.lb @@ -62,7 +62,7 @@ uses MAINBOARD_VENDOR uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -146,7 +146,7 @@ default HAVE_FALLBACK_BOOT=1 default HAVE_FAILOVER_BOOT=1 ## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1 @@ -173,7 +173,7 @@ default ACPI_SSDTX_NUM=3 default HAVE_OPTION_TABLE=1 ## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -259,10 +259,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2912 ### -### LinuxBIOS layout values +### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 ## @@ -281,7 +281,7 @@ default HEAP_SIZE=0x8000 default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) ## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00100000 @@ -333,7 +333,7 @@ default TTYS0_BASE=0x3f8 default TTYS0_LCS=0x3 ## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately diff --git a/src/mainboard/tyan/s4880/Config.lb b/src/mainboard/tyan/s4880/Config.lb index df44242896..c529a8a3c3 100644 --- a/src/mainboard/tyan/s4880/Config.lb +++ b/src/mainboard/tyan/s4880/Config.lb @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,19 +12,19 @@ end ## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default CONFIG_ROM_PAYLOAD = 1 ## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) ## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -100,7 +100,7 @@ else end ## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -121,7 +121,7 @@ end ## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -152,7 +152,7 @@ if USE_DCACHE_RAM end ### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ### diff --git a/src/mainboard/tyan/s4880/Options.lb b/src/mainboard/tyan/s4880/Options.lb index 7afffb2c59..7024d629f4 100644 --- a/src/mainboard/tyan/s4880/Options.lb +++ b/src/mainboard/tyan/s4880/Options.lb @@ -35,7 +35,7 @@ uses MAINBOARD_PART_NUMBER uses MAINBOARD_VENDOR uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -87,7 +87,7 @@ default FALLBACK_SIZE=0x40000 default HAVE_FALLBACK_BOOT=1 ## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1 @@ -109,7 +109,7 @@ default HAVE_MP_TABLE=1 default HAVE_OPTION_TABLE=1 ## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -162,10 +162,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4880 ### -### LinuxBIOS layout values +### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 ## @@ -184,7 +184,7 @@ default HEAP_SIZE=0x4000 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE ## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000 @@ -233,7 +233,7 @@ default TTYS0_BASE=0x3f8 default TTYS0_LCS=0x3 ## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately diff --git a/src/mainboard/tyan/s4882/Config.lb b/src/mainboard/tyan/s4882/Config.lb index d128842c28..041dbb9748 100644 --- a/src/mainboard/tyan/s4882/Config.lb +++ b/src/mainboard/tyan/s4882/Config.lb @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,19 +12,19 @@ end ## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default CONFIG_ROM_PAYLOAD = 1 ## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) ## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -100,7 +100,7 @@ else end ## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -121,7 +121,7 @@ end ## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -152,7 +152,7 @@ if USE_DCACHE_RAM end ### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ### diff --git a/src/mainboard/tyan/s4882/Options.lb b/src/mainboard/tyan/s4882/Options.lb index 08444d46b7..d95b1e3e35 100644 --- a/src/mainboard/tyan/s4882/Options.lb +++ b/src/mainboard/tyan/s4882/Options.lb @@ -35,7 +35,7 @@ uses MAINBOARD_PART_NUMBER uses MAINBOARD_VENDOR uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -87,7 +87,7 @@ default FALLBACK_SIZE=0x40000 default HAVE_FALLBACK_BOOT=1 ## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1 @@ -109,7 +109,7 @@ default HAVE_MP_TABLE=1 default HAVE_OPTION_TABLE=1 ## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -161,10 +161,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4882 ### -### LinuxBIOS layout values +### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 ## @@ -183,7 +183,7 @@ default HEAP_SIZE=0x4000 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE ## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00002000 @@ -232,7 +232,7 @@ default TTYS0_BASE=0x3f8 default TTYS0_LCS=0x3 ## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately |