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-rw-r--r--src/mainboard/tyan/s2850/romstage.c2
-rw-r--r--src/mainboard/tyan/s2875/romstage.c2
-rw-r--r--src/mainboard/tyan/s2880/romstage.c2
-rw-r--r--src/mainboard/tyan/s2881/romstage.c2
-rw-r--r--src/mainboard/tyan/s2882/romstage.c2
-rw-r--r--src/mainboard/tyan/s2885/romstage.c2
-rw-r--r--src/mainboard/tyan/s2912/romstage.c8
-rw-r--r--src/mainboard/tyan/s2912_fam10/romstage.c2
-rw-r--r--src/mainboard/tyan/s4880/romstage.c2
-rw-r--r--src/mainboard/tyan/s4882/romstage.c2
-rw-r--r--src/mainboard/tyan/s8226/romstage.c8
11 files changed, 17 insertions, 17 deletions
diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c
index 7f291ae13f..bb91a2a42d 100644
--- a/src/mainboard/tyan/s2850/romstage.c
+++ b/src/mainboard/tyan/s2850/romstage.c
@@ -93,7 +93,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c
index fa3bcf5254..e63734ef60 100644
--- a/src/mainboard/tyan/s2875/romstage.c
+++ b/src/mainboard/tyan/s2875/romstage.c
@@ -102,7 +102,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c
index 49ff6bc657..dba58f226b 100644
--- a/src/mainboard/tyan/s2880/romstage.c
+++ b/src/mainboard/tyan/s2880/romstage.c
@@ -103,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c
index 78cccc29da..b97ba18192 100644
--- a/src/mainboard/tyan/s2881/romstage.c
+++ b/src/mainboard/tyan/s2881/romstage.c
@@ -98,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c
index 49ff6bc657..dba58f226b 100644
--- a/src/mainboard/tyan/s2882/romstage.c
+++ b/src/mainboard/tyan/s2882/romstage.c
@@ -103,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c
index 138d1c034b..fdf9606c47 100644
--- a/src/mainboard/tyan/s2885/romstage.c
+++ b/src/mainboard/tyan/s2885/romstage.c
@@ -98,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index f62e5166f1..80430cbf67 100644
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -129,7 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
+ printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
setup_coherent_ht_domain(); // routing table and start other core0
@@ -152,7 +152,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+ printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
@@ -161,7 +161,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+ printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
#endif
@@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index 77173adb0a..2a9c2a491f 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -205,7 +205,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c
index 71646c23b2..5c0b1281ec 100644
--- a/src/mainboard/tyan/s4880/romstage.c
+++ b/src/mainboard/tyan/s4880/romstage.c
@@ -138,7 +138,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c
index a3ae994fd2..ed84ab627e 100644
--- a/src/mainboard/tyan/s4882/romstage.c
+++ b/src/mainboard/tyan/s4882/romstage.c
@@ -116,7 +116,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c
index e14292e061..d57d27d8dc 100644
--- a/src/mainboard/tyan/s8226/romstage.c
+++ b/src/mainboard/tyan/s8226/romstage.c
@@ -96,7 +96,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3D);
/* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
distinguish_cpu_resets(0);
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
@@ -110,14 +110,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x42);
post_code(0x50);
- print_debug("Disabling cache as ram ");
+ printk(BIOS_DEBUG, "Disabling cache as ram ");
disable_cache_as_ram();
- print_debug("done\n");
+ printk(BIOS_DEBUG, "done\n");
post_code(0x51);
copy_and_run();
/* We will not return, Should never see this message and post code. */
- print_debug("should not be here -\n");
+ printk(BIOS_DEBUG, "should not be here -\n");
post_code(0x54);
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-17 21:22:10 +0000