diff options
Diffstat (limited to 'src/mainboard/tyan')
| -rw-r--r-- | src/mainboard/tyan/s2912/romstage.c | 6 | ||||
| -rw-r--r-- | src/mainboard/tyan/s2912_fam10/romstage.c | 6 |
2 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index 85b5321ac8..ed078397f9 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -30,9 +30,9 @@ #endif //used by init_cpus and fidvid -#define K8_SET_FIDVID 0 +#define SET_FIDVID 0 //if we want to wait for core1 done before DQS training, set it to 0 -#define K8_SET_FIDVID_CORE0_ONLY 1 +#define SET_FIDVID_CORE0_ONLY 1 #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 @@ -232,7 +232,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if K8_SET_FIDVID == 1 +#if SET_FIDVID == 1 { msr_t msr; diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 5c72639d5e..54fb96ecbf 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -30,8 +30,8 @@ #define SET_NB_CFG_54 1 #endif -#define FAM10_SET_FIDVID 1 -#define FAM10_SET_FIDVID_CORE_RANGE 0 +#define SET_FIDVID 1 +#define SET_FIDVID_CORE_RANGE 0 #define DBGP_DEFAULT 7 @@ -243,7 +243,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x38); -#if FAM10_SET_FIDVID == 1 +#if SET_FIDVID == 1 msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); |