diff options
Diffstat (limited to 'src/mainboard/tyan')
62 files changed, 1519 insertions, 815 deletions
diff --git a/src/mainboard/tyan/s2735/Config.lb b/src/mainboard/tyan/s2735/Config.lb index 568bc9b211..3977db16b9 100644 --- a/src/mainboard/tyan/s2735/Config.lb +++ b/src/mainboard/tyan/s2735/Config.lb @@ -43,7 +43,7 @@ arch i386 end driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -#object reset.o +object reset.o if USE_DCACHE_RAM if CONFIG_USE_INIT diff --git a/src/mainboard/tyan/s2735/Options.lb b/src/mainboard/tyan/s2735/Options.lb index 16b23a66bd..ada1beb593 100644 --- a/src/mainboard/tyan/s2735/Options.lb +++ b/src/mainboard/tyan/s2735/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -92,21 +89,16 @@ default HAVE_FALLBACK_BOOT=1 ## default HAVE_HARD_RESET=1 -default HARD_RESET_BUS=1 -default HARD_RESET_DEVICE=4 -default HARD_RESET_FUNCTION=0 - ## Delay timer options ## default CONFIG_UDELAY_TSC=1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 - ## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default IRQ_SLOT_COUNT=15 ## ## Build code to export an x86 MP table @@ -148,8 +140,8 @@ default SERIAL_CPU_INIT=0 ## enable CACHE_AS_RAM specifics ## default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xF2000000 -#default DCACHE_RAM_BASE=0xcf000 +#default DCACHE_RAM_BASE=0xF2000000 +default DCACHE_RAM_BASE=0xcf000 default DCACHE_RAM_SIZE=0x1000 #default CONFIG_USE_INIT=1 diff --git a/src/mainboard/tyan/s2735/reset.c b/src/mainboard/tyan/s2735/reset.c new file mode 100644 index 0000000000..3cc3d54988 --- /dev/null +++ b/src/mainboard/tyan/s2735/reset.c @@ -0,0 +1,5 @@ + +void hard_reset(void) +{ + i82801er_hard_reset(); +} diff --git a/src/mainboard/tyan/s2850/Config.lb b/src/mainboard/tyan/s2850/Config.lb index 89de7dba33..df8788233b 100644 --- a/src/mainboard/tyan/s2850/Config.lb +++ b/src/mainboard/tyan/s2850/Config.lb @@ -39,9 +39,33 @@ arch i386 end ## driver mainboard.o + +#dir /drivers/si/3114 + if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -#object reset.o +object reset.o + +if USE_DCACHE_RAM + +if CONFIG_USE_INIT + +makerule ./auto.o + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" +end + +else + +makerule ./auto.inc + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" + action "perl -e 's/.rodata/.rom.data/g' -pi $@" + action "perl -e 's/.text/.section .rom.text/g' -pi $@" +end + +end +else ## ## Romcc output @@ -65,13 +89,22 @@ makerule ./auto.inc action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" end +end ## ## Build our 16 bit and 32 bit linuxBIOS entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds +if USE_DCACHE_RAM + if CONFIG_USE_INIT + ldscript /cpu/x86/32bit/entry32.lds + end + + if CONFIG_USE_INIT + ldscript /cpu/amd/car/cache_as_ram.lds + end +end ## ## Build our reset vector (This is where linuxBIOS is entered) @@ -84,8 +117,11 @@ else ldscript /cpu/x86/32bit/reset32.lds end +if USE_DCACHE_RAM +else ### Should this be in the northbridge code? mainboardinit arch/i386/lib/cpu_reset.inc +end ## ## Include an id string (For safe flashing) @@ -93,14 +129,25 @@ mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds +if USE_DCACHE_RAM +## +## Setup Cache-As-Ram +## +mainboardinit cpu/amd/car/cache_as_ram.inc +end + ### ### This is the early phase of linuxBIOS startup ### Things are delicate and we test to see if we should ### failover to another image. ### if USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc +if USE_DCACHE_RAM + ldscript /arch/i386/lib/failover.lds +else + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end end ### @@ -110,6 +157,19 @@ end ## ## Setup RAM ## +if USE_DCACHE_RAM + +if CONFIG_USE_INIT +initobject auto.o +else +mainboardinit ./auto.inc +end + +else + +## +## Setup RAM +## mainboardinit cpu/x86/fpu/enable_fpu.inc mainboardinit cpu/x86/mmx/enable_mmx.inc mainboardinit cpu/x86/sse/enable_sse.inc @@ -117,11 +177,13 @@ mainboardinit ./auto.inc mainboardinit cpu/x86/sse/disable_sse.inc mainboardinit cpu/x86/mmx/disable_mmx.inc +end + ## ## Include the secondary Configuration files ## if CONFIG_CHIP_NAME - config chip.h + config chip.h end # sample config for tyan/s2850 diff --git a/src/mainboard/tyan/s2850/Options.lb b/src/mainboard/tyan/s2850/Options.lb index c9b56b2811..646293e20e 100644 --- a/src/mainboard/tyan/s2850/Options.lb +++ b/src/mainboard/tyan/s2850/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -45,9 +42,9 @@ uses DEFAULT_CONSOLE_LOGLEVEL uses MAXIMUM_CONSOLE_LOGLEVEL uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_CONSOLE_BTEXT uses HAVE_INIT_TIMER uses CONFIG_GDB_STUB +uses CONFIG_GDB_STUB uses CROSS_COMPILE uses CC uses HOSTCC @@ -57,6 +54,9 @@ uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses K8_E0_MEM_HOLE_SIZEK +uses USE_DCACHE_RAM +uses DCACHE_RAM_BASE +uses DCACHE_RAM_SIZE uses CONFIG_USE_INIT ### @@ -84,13 +84,6 @@ default HAVE_FALLBACK_BOOT=1 default HAVE_HARD_RESET=1 ## -## Funky hard reset implementation -## -default HARD_RESET_BUS=1 -default HARD_RESET_DEVICE=2 -default HARD_RESET_FUNCTION=0 - -## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 @@ -119,20 +112,29 @@ default LB_CKS_LOC=123 ## Only worry about 2 micro processors ## default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=1 +default CONFIG_MAX_CPUS=2 default CONFIG_MAX_PHYSICAL_CPUS=1 -default CONFIG_LOGICAL_CPUS=0 +default CONFIG_LOGICAL_CPUS=1 + +#CHIP_NAME ? +default CONFIG_CHIP_NAME=1 #1G memory hole default K8_E0_MEM_HOLE_SIZEK=0x100000 -#BTEXT CONSOLE -#default CONFIG_CONSOLE_BTEXT=1 - -#VGA +#VGA Console default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=1 + +## +## enable CACHE_AS_RAM specifics +## +default USE_DCACHE_RAM=1 +default DCACHE_RAM_BASE=0xcf000 +default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_INIT=1 + ## ## Build code to setup a generic IOAPIC ## @@ -141,7 +143,7 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="s2850" +default MAINBOARD_PART_NUMBER="S2850" default MAINBOARD_VENDOR="Tyan" default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2850 @@ -231,9 +233,9 @@ default TTYS0_LCS=0x3 ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=7 +default DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=7 +default MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting diff --git a/src/mainboard/tyan/s2850/auto.c b/src/mainboard/tyan/s2850/auto.c index 9220738d87..0b9012aca8 100644 --- a/src/mainboard/tyan/s2850/auto.c +++ b/src/mainboard/tyan/s2850/auto.c @@ -25,21 +25,52 @@ #include "cpu/x86/bist.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +/* Look up a which bus a given node/link combination is on. + * return 0 when we can't find the answer. + */ +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + unsigned reg; + + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + unsigned config_map; + config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + if ((config_map & 3) != 3) { + continue; + } + if ((((config_map >> 4) & 7) == node) && + (((config_map >> 8) & 3) == link)) + { + return (config_map >> 16) & 0xff; + } + } + return 0; +} static void hard_reset(void) { - set_bios_reset(); + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3); + + set_bios_reset(); - /* enable cf9 */ - pci_write_config8(PCI_DEV(0, 0x02, 3), 0x41, 0xf1); - /* reset */ - outb(0x0e, 0x0cf9); + /* enable cf9 */ + pci_write_config8(dev, 0x41, 0xf1); + /* reset */ + outb(0x0e, 0x0cf9); } static void soft_reset(void) { - set_bios_reset(); - pci_write_config8(PCI_DEV(0, 0x02, 0), 0x47, 1); + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0); + + set_bios_reset(); + pci_write_config8(dev, 0x47, 1); } #define REV_B_RESET 0 diff --git a/src/mainboard/tyan/s2850/mptable.c b/src/mainboard/tyan/s2850/mptable.c index 6a28ecbe79..fe175795e2 100644 --- a/src/mainboard/tyan/s2850/mptable.c +++ b/src/mainboard/tyan/s2850/mptable.c @@ -7,6 +7,42 @@ #include <cpu/amd/dualcore.h> #endif + +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + device_t dev; + unsigned reg; + + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + if (!dev) { + return 0; + } + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + uint32_t config_map; + unsigned dst_node; + unsigned dst_link; + unsigned bus_base; + config_map = pci_read_config32(dev, reg); + if ((config_map & 3) != 3) { + continue; + } + dst_node = (config_map >> 4) & 7; + dst_link = (config_map >> 8) & 3; + bus_base = (config_map >> 16) & 0xff; +#if 0 + printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", + dst_node, dst_link, bus_base, + reg, config_map); +#endif + if ((dst_node == node) && (dst_link == link)) + { + return bus_base; + } + } + return 0; +} + + void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; @@ -16,6 +52,7 @@ void *smp_write_config_table(void *v) unsigned char bus_num; unsigned char bus_isa; + unsigned char bus_chain_0; unsigned char bus_8111_1; unsigned apicid_base; unsigned apicid_8111; @@ -41,8 +78,14 @@ void *smp_write_config_table(void *v) { device_t dev; + /* HT chain 0 */ + bus_chain_0 = node_link_to_bus(0, 0); + if (bus_chain_0 == 0) { + printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n"); + bus_chain_0 = 1; + } /* 8111 */ - dev = dev_find_slot(1, PCI_DEVFN(0x01,0)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); @@ -89,7 +132,7 @@ void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, (2<<2)|3, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (2<<2)|3, apicid_8111, 0x13); //On Board AMD USB smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13); diff --git a/src/mainboard/tyan/s2850/reset.c b/src/mainboard/tyan/s2850/reset.c new file mode 100644 index 0000000000..3db3956ec6 --- /dev/null +++ b/src/mainboard/tyan/s2850/reset.c @@ -0,0 +1,6 @@ +#include "../../../southbridge/amd/amd8111/amd8111_reset.c" + +void hard_reset(void) +{ + amd8111_hard_reset(0, 0); +} diff --git a/src/mainboard/tyan/s2875/Config.lb b/src/mainboard/tyan/s2875/Config.lb index f042467f5c..bd61fcb34f 100644 --- a/src/mainboard/tyan/s2875/Config.lb +++ b/src/mainboard/tyan/s2875/Config.lb @@ -39,11 +39,34 @@ arch i386 end ## driver mainboard.o + +#dir /drivers/si/3114 + if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -#object reset.o +object reset.o + +if USE_DCACHE_RAM +if CONFIG_USE_INIT + +makerule ./auto.o + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" +end +else + +makerule ./auto.inc + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" + action "perl -e 's/.rodata/.rom.data/g' -pi $@" + action "perl -e 's/.text/.section .rom.text/g' -pi $@" +end + +end +else + ## ## Romcc output ## @@ -66,13 +89,22 @@ makerule ./auto.inc action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" end +end ## ## Build our 16 bit and 32 bit linuxBIOS entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds +if USE_DCACHE_RAM + if CONFIG_USE_INIT + ldscript /cpu/x86/32bit/entry32.lds + end + + if CONFIG_USE_INIT + ldscript /cpu/amd/car/cache_as_ram.lds + end +end ## ## Build our reset vector (This is where linuxBIOS is entered) @@ -85,8 +117,11 @@ else ldscript /cpu/x86/32bit/reset32.lds end +if USE_DCACHE_RAM +else ### Should this be in the northbridge code? mainboardinit arch/i386/lib/cpu_reset.inc +end ## ## Include an id string (For safe flashing) @@ -94,14 +129,25 @@ mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds +if USE_DCACHE_RAM +## +## Setup Cache-As-Ram +## +mainboardinit cpu/amd/car/cache_as_ram.inc +end + ### ### This is the early phase of linuxBIOS startup ### Things are delicate and we test to see if we should ### failover to another image. ### if USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc +if USE_DCACHE_RAM + ldscript /arch/i386/lib/failover.lds +else + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end end ### @@ -111,6 +157,19 @@ end ## ## Setup RAM ## +if USE_DCACHE_RAM + +if CONFIG_USE_INIT +initobject auto.o +else +mainboardinit ./auto.inc +end + +else + +## +## Setup RAM +## mainboardinit cpu/x86/fpu/enable_fpu.inc mainboardinit cpu/x86/mmx/enable_mmx.inc mainboardinit cpu/x86/sse/enable_sse.inc @@ -118,11 +177,13 @@ mainboardinit ./auto.inc mainboardinit cpu/x86/sse/disable_sse.inc mainboardinit cpu/x86/mmx/disable_mmx.inc +end + ## ## Include the secondary Configuration files ## if CONFIG_CHIP_NAME - config chip.h + config chip.h end # sample config for tyan/s2875 diff --git a/src/mainboard/tyan/s2875/Options.lb b/src/mainboard/tyan/s2875/Options.lb index 5851318be6..a584d1b436 100644 --- a/src/mainboard/tyan/s2875/Options.lb +++ b/src/mainboard/tyan/s2875/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -47,6 +44,7 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 uses HAVE_INIT_TIMER uses CONFIG_GDB_STUB +uses CONFIG_GDB_STUB uses CROSS_COMPILE uses CC uses HOSTCC @@ -56,6 +54,9 @@ uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses K8_E0_MEM_HOLE_SIZEK +uses USE_DCACHE_RAM +uses DCACHE_RAM_BASE +uses DCACHE_RAM_SIZE uses CONFIG_USE_INIT ### @@ -83,13 +84,6 @@ default HAVE_FALLBACK_BOOT=1 default HAVE_HARD_RESET=1 ## -## Funky hard reset implementation -## -default HARD_RESET_BUS=1 -default HARD_RESET_DEVICE=5 -default HARD_RESET_FUNCTION=0 - -## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 @@ -118,16 +112,28 @@ default LB_CKS_LOC=123 ## Only worry about 2 micro processors ## default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=2 +default CONFIG_MAX_CPUS=4 default CONFIG_MAX_PHYSICAL_CPUS=2 -default CONFIG_LOGICAL_CPUS=0 +default CONFIG_LOGICAL_CPUS=1 + +#CHIP_NAME ? +default CONFIG_CHIP_NAME=1 #1G memory hole default K8_E0_MEM_HOLE_SIZEK=0x100000 #VGA Console -#default CONFIG_CONSOLE_VGA=1 -#default CONFIG_PCI_ROM_RUN=1 +default CONFIG_CONSOLE_VGA=1 +default CONFIG_PCI_ROM_RUN=1 + + +## +## enable CACHE_AS_RAM specifics +## +default USE_DCACHE_RAM=1 +default DCACHE_RAM_BASE=0xcf000 +default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_INIT=1 ## ## Build code to setup a generic IOAPIC diff --git a/src/mainboard/tyan/s2875/auto.c b/src/mainboard/tyan/s2875/auto.c index 1b055bf2ec..7b75db20ab 100644 --- a/src/mainboard/tyan/s2875/auto.c +++ b/src/mainboard/tyan/s2875/auto.c @@ -27,20 +27,52 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +/* Look up a which bus a given node/link combination is on. + * return 0 when we can't find the answer. + */ +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + unsigned reg; + + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + unsigned config_map; + config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + if ((config_map & 3) != 3) { + continue; + } + if ((((config_map >> 4) & 7) == node) && + (((config_map >> 8) & 3) == link)) + { + return (config_map >> 16) & 0xff; + } + } + return 0; +} + static void hard_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3); + set_bios_reset(); /* enable cf9 */ - pci_write_config8(PCI_DEV(0, 0x05, 3), 0x41, 0xf1); + pci_write_config8(dev, 0x41, 0xf1); /* reset */ outb(0x0e, 0x0cf9); } static void soft_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0); + set_bios_reset(); - pci_write_config8(PCI_DEV(0, 0x05, 0), 0x47, 1); + pci_write_config8(dev, 0x47, 1); } static void memreset_setup(void) @@ -141,6 +173,7 @@ static void main(unsigned long bist) asm volatile ("jmp __cpu_reset"); } distinguish_cpu_resets(id.nodeid); +// start_other_core(id.nodeid); } #else nodeid = lapicid(); @@ -155,7 +188,7 @@ static void main(unsigned long bist) || (id.coreid != 0) #endif ) { - stop_this_cpu(); + stop_this_cpu(); // it will stop all cores except core0 of cpu0 } } diff --git a/src/mainboard/tyan/s2875/mptable.c b/src/mainboard/tyan/s2875/mptable.c index 9b93decd80..394410b5ba 100644 --- a/src/mainboard/tyan/s2875/mptable.c +++ b/src/mainboard/tyan/s2875/mptable.c @@ -7,6 +7,40 @@ #include <cpu/amd/dualcore.h> #endif +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + device_t dev; + unsigned reg; + + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + if (!dev) { + return 0; + } + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + uint32_t config_map; + unsigned dst_node; + unsigned dst_link; + unsigned bus_base; + config_map = pci_read_config32(dev, reg); + if ((config_map & 3) != 3) { + continue; + } + dst_node = (config_map >> 4) & 7; + dst_link = (config_map >> 8) & 3; + bus_base = (config_map >> 16) & 0xff; +#if 0 + printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", + dst_node, dst_link, bus_base, + reg, config_map); +#endif + if ((dst_node == node) && (dst_link == link)) + { + return bus_base; + } + } + return 0; +} + void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; @@ -16,6 +50,7 @@ void *smp_write_config_table(void *v) unsigned char bus_num; unsigned char bus_isa; + unsigned char bus_chain_0; unsigned char bus_8111_1; unsigned char bus_8151_1; unsigned apicid_base; @@ -43,8 +78,15 @@ void *smp_write_config_table(void *v) { device_t dev; + /* HT chain 0 */ + bus_chain_0 = node_link_to_bus(0, 0); + if (bus_chain_0 == 0) { + printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n"); + bus_chain_0 = 1; + } + /* 8111 */ - dev = dev_find_slot(1, PCI_DEVFN(0x04,0)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x04,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); @@ -58,7 +100,7 @@ void *smp_write_config_table(void *v) bus_isa = 4; } /* 8151 */ - dev = dev_find_slot(1, PCI_DEVFN(0x02,0)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0)); if (dev) { bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); printk_debug("bus_8151_1=%d\n",bus_8151_1); @@ -105,9 +147,9 @@ void *smp_write_config_table(void *v) //??? What - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, (5<<2)|3, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (5<<2)|3, apicid_8111, 0x13); //Onboard AMD AC97 Audio ??? - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, (5<<2)|1, apicid_8111, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (5<<2)|1, apicid_8111, 0x11); // Onboard AMD USB smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13); diff --git a/src/mainboard/tyan/s2875/reset.c b/src/mainboard/tyan/s2875/reset.c new file mode 100644 index 0000000000..3db3956ec6 --- /dev/null +++ b/src/mainboard/tyan/s2875/reset.c @@ -0,0 +1,6 @@ +#include "../../../southbridge/amd/amd8111/amd8111_reset.c" + +void hard_reset(void) +{ + amd8111_hard_reset(0, 0); +} diff --git a/src/mainboard/tyan/s2880/Config.lb b/src/mainboard/tyan/s2880/Config.lb index 6c4ac7b7c1..f7ad508347 100644 --- a/src/mainboard/tyan/s2880/Config.lb +++ b/src/mainboard/tyan/s2880/Config.lb @@ -39,10 +39,33 @@ arch i386 end ## driver mainboard.o + +#dir /drivers/si/3114 + if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -#object reset.o +object reset.o + +if USE_DCACHE_RAM + +if CONFIG_USE_INIT + +makerule ./auto.o + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" +end + +else + +makerule ./auto.inc + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" + action "perl -e 's/.rodata/.rom.data/g' -pi $@" + action "perl -e 's/.text/.section .rom.text/g' -pi $@" +end +end +else ## ## Romcc output @@ -66,13 +89,22 @@ makerule ./auto.inc action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" end +end ## ## Build our 16 bit and 32 bit linuxBIOS entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds +if USE_DCACHE_RAM + if CONFIG_USE_INIT + ldscript /cpu/x86/32bit/entry32.lds + end + + if CONFIG_USE_INIT + ldscript /cpu/amd/car/cache_as_ram.lds + end +end ## ## Build our reset vector (This is where linuxBIOS is entered) @@ -85,8 +117,11 @@ else ldscript /cpu/x86/32bit/reset32.lds end +if USE_DCACHE_RAM +else ### Should this be in the northbridge code? mainboardinit arch/i386/lib/cpu_reset.inc +end ## ## Include an id string (For safe flashing) @@ -94,14 +129,25 @@ mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds +if USE_DCACHE_RAM +## +## Setup Cache-As-Ram +## +mainboardinit cpu/amd/car/cache_as_ram.inc +end + ### ### This is the early phase of linuxBIOS startup ### Things are delicate and we test to see if we should ### failover to another image. ### if USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc +if USE_DCACHE_RAM + ldscript /arch/i386/lib/failover.lds +else + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end end ### @@ -111,6 +157,19 @@ end ## ## Setup RAM ## +if USE_DCACHE_RAM + +if CONFIG_USE_INIT +initobject auto.o +else +mainboardinit ./auto.inc +end + +else + +## +## Setup RAM +## mainboardinit cpu/x86/fpu/enable_fpu.inc mainboardinit cpu/x86/mmx/enable_mmx.inc mainboardinit cpu/x86/sse/enable_sse.inc @@ -118,11 +177,13 @@ mainboardinit ./auto.inc mainboardinit cpu/x86/sse/disable_sse.inc mainboardinit cpu/x86/mmx/disable_mmx.inc +end + ## ## Include the secondary Configuration files ## if CONFIG_CHIP_NAME - config chip.h + config chip.h end # sample config for tyan/s2880 diff --git a/src/mainboard/tyan/s2880/Options.lb b/src/mainboard/tyan/s2880/Options.lb index a6b4e86f50..1f929b0edc 100644 --- a/src/mainboard/tyan/s2880/Options.lb +++ b/src/mainboard/tyan/s2880/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -47,6 +44,7 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 uses HAVE_INIT_TIMER uses CONFIG_GDB_STUB +uses CONFIG_GDB_STUB uses CROSS_COMPILE uses CC uses HOSTCC @@ -56,6 +54,9 @@ uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses K8_E0_MEM_HOLE_SIZEK +uses USE_DCACHE_RAM +uses DCACHE_RAM_BASE +uses DCACHE_RAM_SIZE uses CONFIG_USE_INIT ### @@ -83,13 +84,6 @@ default HAVE_FALLBACK_BOOT=1 default HAVE_HARD_RESET=1 ## -## Funky hard reset implementation -## -default HARD_RESET_BUS=1 -default HARD_RESET_DEVICE=4 -default HARD_RESET_FUNCTION=0 - -## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 @@ -122,6 +116,9 @@ default CONFIG_MAX_CPUS=2 default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=0 +#CHIP_NAME ? +default CONFIG_CHIP_NAME=1 + #1G memory hole default K8_E0_MEM_HOLE_SIZEK=0x100000 @@ -129,6 +126,15 @@ default K8_E0_MEM_HOLE_SIZEK=0x100000 default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=1 + +## +## enable CACHE_AS_RAM specifics +## +default USE_DCACHE_RAM=1 +default DCACHE_RAM_BASE=0xcf000 +default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_INIT=1 + ## ## Build code to setup a generic IOAPIC ## @@ -137,7 +143,7 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="s2880" +default MAINBOARD_PART_NUMBER="S2880" default MAINBOARD_VENDOR="Tyan" default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2880 diff --git a/src/mainboard/tyan/s2880/auto.c b/src/mainboard/tyan/s2880/auto.c index 1ed43bc19e..2532386132 100644 --- a/src/mainboard/tyan/s2880/auto.c +++ b/src/mainboard/tyan/s2880/auto.c @@ -27,20 +27,52 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +/* Look up a which bus a given node/link combination is on. + * return 0 when we can't find the answer. + */ +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + unsigned reg; + + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + unsigned config_map; + config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + if ((config_map & 3) != 3) { + continue; + } + if ((((config_map >> 4) & 7) == node) && + (((config_map >> 8) & 3) == link)) + { + return (config_map >> 16) & 0xff; + } + } + return 0; +} + static void hard_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3); + set_bios_reset(); /* enable cf9 */ - pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + pci_write_config8(dev, 0x41, 0xf1); /* reset */ outb(0x0e, 0x0cf9); } static void soft_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0); + set_bios_reset(); - pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); + pci_write_config8(dev, 0x47, 1); } static void memreset_setup(void) @@ -155,7 +187,7 @@ static void main(unsigned long bist) || (id.coreid != 0) #endif ) { - stop_this_cpu(); + stop_this_cpu(); // it will stop all cores except core0 of cpu0 } } @@ -179,8 +211,4 @@ static void main(unsigned long bist) soft_reset(); } - enable_smbus(); - memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); - } diff --git a/src/mainboard/tyan/s2880/irq_tables.c b/src/mainboard/tyan/s2880/irq_tables.c index 4ffc5cffa0..08c51795fd 100644 --- a/src/mainboard/tyan/s2880/irq_tables.c +++ b/src/mainboard/tyan/s2880/irq_tables.c @@ -37,5 +37,5 @@ const struct irq_routing_table intel_irq_routing_table = { }; unsigned long write_pirq_routing_table(unsigned long addr) { - return copy_pirq_routing_table(addr); + return copy_pirq_routing_table(addr); } diff --git a/src/mainboard/tyan/s2880/mptable.c b/src/mainboard/tyan/s2880/mptable.c index 9c4764a77b..d013a463fa 100644 --- a/src/mainboard/tyan/s2880/mptable.c +++ b/src/mainboard/tyan/s2880/mptable.c @@ -7,6 +7,42 @@ #include <cpu/amd/dualcore.h> #endif + +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + device_t dev; + unsigned reg; + + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + if (!dev) { + return 0; + } + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + uint32_t config_map; + unsigned dst_node; + unsigned dst_link; + unsigned bus_base; + config_map = pci_read_config32(dev, reg); + if ((config_map & 3) != 3) { + continue; + } + dst_node = (config_map >> 4) & 7; + dst_link = (config_map >> 8) & 3; + bus_base = (config_map >> 16) & 0xff; +#if 0 + printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", + dst_node, dst_link, bus_base, + reg, config_map); +#endif + if ((dst_node == node) && (dst_link == link)) + { + return bus_base; + } + } + return 0; +} + + void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; @@ -16,6 +52,7 @@ void *smp_write_config_table(void *v) unsigned char bus_num; unsigned char bus_isa; + unsigned char bus_chain_0; unsigned char bus_8131_1; unsigned char bus_8131_2; unsigned char bus_8111_1; @@ -45,9 +82,16 @@ void *smp_write_config_table(void *v) { device_t dev; + + /* HT chain 0 */ + bus_chain_0 = node_link_to_bus(0, 0); + if (bus_chain_0 == 0) { + printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n"); + bus_chain_0 = 1; + } /* 8111 */ - dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); @@ -60,7 +104,7 @@ void *smp_write_config_table(void *v) bus_isa = 5; } /* 8131-1 */ - dev = dev_find_slot(1, PCI_DEVFN(0x01,0)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0)); if (dev) { bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); @@ -71,7 +115,7 @@ void *smp_write_config_table(void *v) bus_8131_1 = 2; } /* 8131-2 */ - dev = dev_find_slot(1, PCI_DEVFN(0x02,0)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0)); if (dev) { bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); @@ -105,14 +149,14 @@ void *smp_write_config_table(void *v) device_t dev; struct resource *res; - dev = dev_find_slot(1, PCI_DEVFN(0x1,1)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base); } } - dev = dev_find_slot(1, PCI_DEVFN(0x2,1)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { @@ -137,7 +181,7 @@ void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 1, (4<<2)|0, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (4<<2)|0, apicid_8111, 0x13); //On Board AMD USB diff --git a/src/mainboard/tyan/s2880/reset.c b/src/mainboard/tyan/s2880/reset.c new file mode 100644 index 0000000000..3db3956ec6 --- /dev/null +++ b/src/mainboard/tyan/s2880/reset.c @@ -0,0 +1,6 @@ +#include "../../../southbridge/amd/amd8111/amd8111_reset.c" + +void hard_reset(void) +{ + amd8111_hard_reset(0, 0); +} diff --git a/src/mainboard/tyan/s2881/Config.lb b/src/mainboard/tyan/s2881/Config.lb index 2e564ce9ea..02c6ec8255 100644 --- a/src/mainboard/tyan/s2881/Config.lb +++ b/src/mainboard/tyan/s2881/Config.lb @@ -44,8 +44,7 @@ driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -#object reset.o - +object reset.o if USE_DCACHE_RAM if CONFIG_USE_INIT @@ -67,6 +66,7 @@ end end else + ## ## Romcc output ## diff --git a/src/mainboard/tyan/s2881/Options.lb b/src/mainboard/tyan/s2881/Options.lb index 84fa34e568..38eb3be4ef 100644 --- a/src/mainboard/tyan/s2881/Options.lb +++ b/src/mainboard/tyan/s2881/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -87,13 +84,6 @@ default HAVE_FALLBACK_BOOT=1 default HAVE_HARD_RESET=1 ## -## Funky hard reset implementation -## -default HARD_RESET_BUS=1 -default HARD_RESET_DEVICE=4 -default HARD_RESET_FUNCTION=0 - -## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 diff --git a/src/mainboard/tyan/s2881/auto.c b/src/mainboard/tyan/s2881/auto.c index 391be78879..fc622793d3 100644 --- a/src/mainboard/tyan/s2881/auto.c +++ b/src/mainboard/tyan/s2881/auto.c @@ -27,20 +27,52 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +/* Look up a which bus a given node/link combination is on. + * return 0 when we can't find the answer. + */ +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + unsigned reg; + + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + unsigned config_map; + config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + if ((config_map & 3) != 3) { + continue; + } + if ((((config_map >> 4) & 7) == node) && + (((config_map >> 8) & 3) == link)) + { + return (config_map >> 16) & 0xff; + } + } + return 0; +} + static void hard_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 3); + set_bios_reset(); /* enable cf9 */ - pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + pci_write_config8(dev, 0x41, 0xf1); /* reset */ outb(0x0e, 0x0cf9); } static void soft_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 0); + set_bios_reset(); - pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); + pci_write_config8(dev, 0x47, 1); } static void memreset_setup(void) @@ -155,7 +187,7 @@ static void main(unsigned long bist) || (id.coreid != 0) #endif ) { - stop_this_cpu(); + stop_this_cpu(); // it will stop all cores except core0 of cpu0 } } diff --git a/src/mainboard/tyan/s2881/cache_as_ram_auto.c b/src/mainboard/tyan/s2881/cache_as_ram_auto.c index 5ac861d5da..bb037a4f61 100644 --- a/src/mainboard/tyan/s2881/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2881/cache_as_ram_auto.c @@ -13,6 +13,7 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" + #include "northbridge/amd/amdk8/cpu_rev.c" #define K8_HT_FREQ_1G_SUPPORT 0 #include "northbridge/amd/amdk8/incoherent_ht.c" @@ -37,20 +38,52 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +/* Look up a which bus a given node/link combination is on. + * return 0 when we can't find the answer. + */ +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + unsigned reg; + + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + unsigned config_map; + config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + if ((config_map & 3) != 3) { + continue; + } + if ((((config_map >> 4) & 7) == node) && + (((config_map >> 8) & 3) == link)) + { + return (config_map >> 16) & 0xff; + } + } + return 0; +} + static void hard_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 3); + set_bios_reset(); /* enable cf9 */ - pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + pci_write_config8(dev, 0x41, 0xf1); /* reset */ outb(0x0e, 0x0cf9); } static void soft_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 0); + set_bios_reset(); - pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); + pci_write_config8(dev, 0x47, 1); } static void memreset_setup(void) @@ -93,6 +126,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #include "cpu/amd/dualcore/dualcore.c" +#else +#include "cpu/amd/model_fxx/node_id.c" #endif #define FIRST_CPU 1 @@ -136,7 +171,6 @@ void amd64_main(unsigned long bist) } /* Is this a secondary cpu? */ -// post_code(0x21); if (!boot_cpu()) { if (last_boot_normal()) { goto normal_image; @@ -154,7 +188,6 @@ void amd64_main(unsigned long bist) amd8111_enable_rom(); /* Is this a deliberate reset by the bios */ -// post_code(0x22); if (bios_reset_detected() && last_boot_normal()) { goto normal_image; } @@ -166,13 +199,11 @@ void amd64_main(unsigned long bist) goto fallback_image; } normal_image: -// post_code(0x23); __asm__ volatile ("jmp __normal_image" : /* outputs */ : "a" (bist) /* inputs */ ); cpu_reset: -// post_code(0x24); #if 0 //CPU reset will reset memtroller ??? asm volatile ("jmp __cpu_reset" @@ -182,7 +213,6 @@ void amd64_main(unsigned long bist) #endif fallback_image: -// post_code(0x25); real_main(bist); } void real_main(unsigned long bist) @@ -275,17 +305,13 @@ void amd64_main(unsigned long bist) report_bist_failure(bist); setup_s2881_resource_map(); -#if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); - dump_pci_device(PCI_DEV(0, 0x19, 0)); -#endif needs_reset = setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched start_other_cores(); #endif - needs_reset |= ht_setup_chains_x(); if (needs_reset) { @@ -294,20 +320,10 @@ void amd64_main(unsigned long bist) } enable_smbus(); -#if 0 - dump_spd_registers(&cpu[0]); -#endif -#if 0 - dump_smbus_registers(); -#endif memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); -#if 0 - dump_pci_devices(); -#endif - #if 1 { /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ @@ -324,6 +340,8 @@ void amd64_main(unsigned long bist) } #endif +#if 1 + cpu_reset_x: @@ -386,6 +404,7 @@ cpu_reset_x: copy_and_run(new_cpu_reset); /* We will not return */ } +#endif print_debug("should not be here -\r\n"); diff --git a/src/mainboard/tyan/s2881/mptable.c b/src/mainboard/tyan/s2881/mptable.c index 06f1301ee5..ee92919db8 100644 --- a/src/mainboard/tyan/s2881/mptable.c +++ b/src/mainboard/tyan/s2881/mptable.c @@ -7,6 +7,41 @@ #include <cpu/amd/dualcore.h> #endif + +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + device_t dev; + unsigned reg; + + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + if (!dev) { + return 0; + } + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + uint32_t config_map; + unsigned dst_node; + unsigned dst_link; + unsigned bus_base; + config_map = pci_read_config32(dev, reg); + if ((config_map & 3) != 3) { + continue; + } + dst_node = (config_map >> 4) & 7; + dst_link = (config_map >> 8) & 3; + bus_base = (config_map >> 16) & 0xff; +#if 0 + printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", + dst_node, dst_link, bus_base, + reg, config_map); +#endif + if ((dst_node == node) && (dst_link == link)) + { + return bus_base; + } + } + return 0; +} + void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; @@ -16,6 +51,7 @@ void *smp_write_config_table(void *v) unsigned char bus_num; unsigned char bus_isa; + unsigned char bus_chain_0; unsigned char bus_8131_1; unsigned char bus_8131_2; unsigned char bus_8111_1; @@ -46,9 +82,16 @@ void *smp_write_config_table(void *v) { device_t dev; + + /* HT chain 0 */ + bus_chain_0 = node_link_to_bus(0, 2); + if (bus_chain_0 == 0) { + printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n"); + bus_chain_0 = 1; + } /* 8111 */ - dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); @@ -61,7 +104,7 @@ void *smp_write_config_table(void *v) bus_isa = 5; } /* 8131-1 */ - dev = dev_find_slot(1, PCI_DEVFN(0x01,0)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0)); if (dev) { bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); @@ -72,7 +115,7 @@ void *smp_write_config_table(void *v) bus_8131_1 = 2; } /* 8131-2 */ - dev = dev_find_slot(1, PCI_DEVFN(0x02,0)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0)); if (dev) { bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); @@ -106,14 +149,14 @@ void *smp_write_config_table(void *v) { device_t dev; struct resource *res; - dev = dev_find_slot(1, PCI_DEVFN(0x1,1)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base); } } - dev = dev_find_slot(1, PCI_DEVFN(0x2,1)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { @@ -138,7 +181,7 @@ void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf); //8111 LPC ???? - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 1, (4<<2)|0, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (4<<2)|0, apicid_8111, 0x13); //On Board AMD USB ??? smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13); diff --git a/src/mainboard/tyan/s2881/reset.c b/src/mainboard/tyan/s2881/reset.c new file mode 100644 index 0000000000..63958185f6 --- /dev/null +++ b/src/mainboard/tyan/s2881/reset.c @@ -0,0 +1,6 @@ +#include "../../../southbridge/amd/amd8111/amd8111_reset.c" + +void hard_reset(void) +{ + amd8111_hard_reset(0, 2); +} diff --git a/src/mainboard/tyan/s2882/Config.lb b/src/mainboard/tyan/s2882/Config.lb index 7739a67ca6..6f71a49864 100644 --- a/src/mainboard/tyan/s2882/Config.lb +++ b/src/mainboard/tyan/s2882/Config.lb @@ -44,7 +44,7 @@ driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -#object reset.o +object reset.o if USE_DCACHE_RAM @@ -278,36 +278,37 @@ chip northbridge/amd/amdk8/root_complex end device pci 1.1 on end device pci 1.2 on end - device pci 1.3 on -# chip drivers/generic/generic #dimm 0-0-0 -# device i2c 50 on end -# end -# chip drivers/generic/generic #dimm 0-0-1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #dimm 0-1-0 -# device i2c 52 on end -# end -# chip drivers/generic/generic #dimm 0-1-1 -# device i2c 53 on end -# end -# chip drivers/generic/generic #dimm 1-0-0 -# device i2c 54 on end -# end -# chip drivers/generic/generic #dimm 1-0-1 -# device i2c 55 on end -# end -# chip drivers/generic/generic #dimm 1-1-0 -# device i2c 56 on end -# end -# chip drivers/generic/generic #dimm 1-1-1 -# device i2c 57 on end -# end + device pci 1.3 on end + device pci 1.3 on +# chip drivers/generic/generic #dimm 0-0-0 +# device i2c 50 on end +# end +# chip drivers/generic/generic #dimm 0-0-1 +# device i2c 51 on end +# end +# chip drivers/generic/generic #dimm 0-1-0 +# device i2c 52 on end +# end +# chip drivers/generic/generic #dimm 0-1-1 +# device i2c 53 on end +# end +# chip drivers/generic/generic #dimm 1-0-0 +# device i2c 54 on end +# end +# chip drivers/generic/generic #dimm 1-0-1 +# device i2c 55 on end +# end +# chip drivers/generic/generic #dimm 1-1-0 +# device i2c 56 on end +# end +# chip drivers/generic/generic #dimm 1-1-1 +# device i2c 57 on end +# end end # acpi device pci 1.5 off end device pci 1.6 off end - register "ide0_enable" = "1" - register "ide1_enable" = "1" + register "ide0_enable" = "1" + register "ide1_enable" = "1" end end # device pci 18.0 diff --git a/src/mainboard/tyan/s2882/Options.lb b/src/mainboard/tyan/s2882/Options.lb index 1249719210..ffa34c4f08 100644 --- a/src/mainboard/tyan/s2882/Options.lb +++ b/src/mainboard/tyan/s2882/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -87,13 +84,6 @@ default HAVE_FALLBACK_BOOT=1 default HAVE_HARD_RESET=1 ## -## Funky hard reset implementation -## -default HARD_RESET_BUS=1 -default HARD_RESET_DEVICE=4 -default HARD_RESET_FUNCTION=0 - -## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 @@ -153,7 +143,7 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="s2882" +default MAINBOARD_PART_NUMBER="S2882" default MAINBOARD_VENDOR="Tyan" default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2882 diff --git a/src/mainboard/tyan/s2882/auto.c b/src/mainboard/tyan/s2882/auto.c index fb7a63abb5..910db9e8a5 100644 --- a/src/mainboard/tyan/s2882/auto.c +++ b/src/mainboard/tyan/s2882/auto.c @@ -27,20 +27,52 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +/* Look up a which bus a given node/link combination is on. + * return 0 when we can't find the answer. + */ +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + unsigned reg; + + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + unsigned config_map; + config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + if ((config_map & 3) != 3) { + continue; + } + if ((((config_map >> 4) & 7) == node) && + (((config_map >> 8) & 3) == link)) + { + return (config_map >> 16) & 0xff; + } + } + return 0; +} + static void hard_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3); + set_bios_reset(); - + /* enable cf9 */ - pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + pci_write_config8(dev, 0x41, 0xf1); /* reset */ outb(0x0e, 0x0cf9); } static void soft_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0); + set_bios_reset(); - pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); + pci_write_config8(dev, 0x47, 1); } #define REV_B_RESET 0 @@ -64,7 +96,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl) } } - static inline void activate_spd_rom(const struct mem_controller *ctrl) { /* nothing to do */ @@ -160,7 +191,7 @@ static void main(unsigned long bist) || (id.coreid != 0) #endif ) { - stop_this_cpu(); + stop_this_cpu(); // it will stop all cores except core0 of cpu0 } } @@ -176,7 +207,6 @@ static void main(unsigned long bist) #if CONFIG_LOGICAL_CPUS==1 start_other_cores(); #endif - // automatically set that for you, but you might meet tight space needs_reset |= ht_setup_chains_x(); if (needs_reset) { print_info("ht reset -\r\n"); diff --git a/src/mainboard/tyan/s2882/cache_as_ram_auto.c b/src/mainboard/tyan/s2882/cache_as_ram_auto.c index 1b3d77a206..f0adb4204b 100644 --- a/src/mainboard/tyan/s2882/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2882/cache_as_ram_auto.c @@ -36,21 +36,52 @@ #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +/* Look up a which bus a given node/link combination is on. + * return 0 when we can't find the answer. + */ +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + unsigned reg; + + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + unsigned config_map; + config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + if ((config_map & 3) != 3) { + continue; + } + if ((((config_map >> 4) & 7) == node) && + (((config_map >> 8) & 3) == link)) + { + return (config_map >> 16) & 0xff; + } + } + return 0; +} static void hard_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3); + set_bios_reset(); /* enable cf9 */ - pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + pci_write_config8(dev, 0x41, 0xf1); /* reset */ outb(0x0e, 0x0cf9); } static void soft_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0); + set_bios_reset(); - pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); + pci_write_config8(dev, 0x47, 1); } static void memreset_setup(void) @@ -93,6 +124,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #include "cpu/amd/dualcore/dualcore.c" +#else +#include "cpu/amd/model_fxx/node_id.c" #endif #define FIRST_CPU 1 @@ -236,6 +269,7 @@ void amd64_main(unsigned long bist) #if CONFIG_LOGICAL_CPUS==1 if(id.coreid == 0) { if (cpu_init_detected(id.nodeid)) { +// __asm__ volatile ("jmp __cpu_reset"); cpu_reset = 1; goto cpu_reset_x; } @@ -249,7 +283,6 @@ void amd64_main(unsigned long bist) distinguish_cpu_resets(nodeid); #endif - if (!boot_cpu() #if CONFIG_LOGICAL_CPUS==1 || (id.coreid != 0) @@ -261,7 +294,6 @@ void amd64_main(unsigned long bist) } } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); @@ -270,14 +302,11 @@ void amd64_main(unsigned long bist) report_bist_failure(bist); setup_default_resource_map(); -#if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); - dump_pci_device(PCI_DEV(0, 0x19, 0)); -#endif needs_reset = setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched start_other_cores(); #endif needs_reset |= ht_setup_chains_x(); @@ -288,21 +317,10 @@ void amd64_main(unsigned long bist) } enable_smbus(); -#if 0 - dump_spd_registers(&cpu[0]); -#endif -#if 0 - dump_smbus_registers(); -#endif memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); -#if 0 - dump_pci_devices(); -#endif - - #if 1 { /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ @@ -319,6 +337,7 @@ void amd64_main(unsigned long bist) } #endif +#if 1 cpu_reset_x: @@ -382,6 +401,7 @@ cpu_reset_x: copy_and_run(new_cpu_reset); /* We will not return */ } +#endif print_debug("should not be here -\r\n"); diff --git a/src/mainboard/tyan/s2882/irq_tables.c b/src/mainboard/tyan/s2882/irq_tables.c index cdff230a2f..add22b4e03 100644 --- a/src/mainboard/tyan/s2882/irq_tables.c +++ b/src/mainboard/tyan/s2882/irq_tables.c @@ -1,301 +1,48 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ -#include <console/console.h> -#include <device/pci.h> -#include <string.h> -#include <stdint.h> #include <arch/pirq_routing.h> +#include <device/pci.h> -const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*15, /* there can be total 15 devices on the bus */ - 1, /* Where the interrupt router lies (bus) */ - (4<<3)|3, /* Where the interrupt router lies (dev) */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x1022, /* Vendor */ - 0x746b, /* Device */ - 0, /* Crap (miniport) */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xff, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structu -re (including checksum) */ - { - {1,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0}, - {0x4,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0}, - {0x4,(6<<3)|0, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}, - {0x3,(3<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0}, - {0x3,(1<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0}, - {0x2,(3<<3)|0, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0}, - {0x2,(2<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0}, - {0x4,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0}, - {0x4,(5<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}, - {0x4,(8<<3)|0, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}, - {0x2,(6<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0}, - {0x2,(5<<3)|0, {{0x3, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}}, 0, 0}, - {0x2,(9<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0}, - {0x3,(4<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x6, 0}, - {0x3,(5<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x7, 0}, - } -}; - -static unsigned node_link_to_bus(unsigned node, unsigned link) -{ - device_t dev; - unsigned reg; +#define IRQ_ROUTER_BUS 1 +#define IRQ_ROUTER_DEVFN PCI_DEVFN(4,3) +#define IRQ_ROUTER_VENDOR 0x1022 +#define IRQ_ROUTER_DEVICE 0x746b - dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); - if (!dev) { - return 0; - } - for(reg = 0xE0; reg < 0xF0; reg += 0x04) { - uint32_t config_map; - unsigned dst_node; - unsigned dst_link; - unsigned bus_base; - config_map = pci_read_config32(dev, reg); - if ((config_map & 3) != 3) { - continue; - } - dst_node = (config_map >> 4) & 7; - dst_link = (config_map >> 8) & 3; - bus_base = (config_map >> 16) & 0xff; -#if 0 - printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", - dst_node, dst_link, bus_base, - reg, config_map); -#endif - if ((dst_node == node) && (dst_link == link)) - { - return bus_base; - } - } - return 0; -} +#define AVAILABLE_IRQS 0xdef8 +#define IRQ_SLOT(slot, bus, dev, fn, linka, linkb, linkc, linkd) \ + { bus, (dev<<3)|fn, {{ linka, AVAILABLE_IRQS}, { linkb, AVAILABLE_IRQS}, \ + {linkc, AVAILABLE_IRQS}, {linkd, AVAILABLE_IRQS}}, slot, 0} -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} +/* Each IRQ_SLOT entry consists of: + * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu + */ +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*IRQ_SLOT_COUNT, /* there can be total IRQ_SLOT_COUNT table entries */ + IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */ + IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */ + 0x00, /* IRQs devoted exclusively to PCI usage */ + IRQ_ROUTER_VENDOR, /* Vendor */ + IRQ_ROUTER_DEVICE, /* Device */ + 0x00, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xb0, /* u8 checksum , mod 256 checksum must give zero */ + { /* slot(0=onboard), devfn, irqlinks (line id, 0=not routed) */ + /* PCI Slot 1-6 */ + IRQ_SLOT(1, 3,1,0, 2,3,4,1 ), + IRQ_SLOT(2, 3,2,0, 3,4,1,2 ), + IRQ_SLOT(3, 2,1,0, 2,3,4,1 ), + IRQ_SLOT(4, 2,2,0, 3,4,1,2 ), + IRQ_SLOT(5, 4,5,0, 2,3,4,1 ), + IRQ_SLOT(6, 4,4,0, 1,2,3,4 ), + /* Onboard NICs */ + IRQ_SLOT(0, 2,3,0, 4,0,0,0 ), + IRQ_SLOT(0, 2,4,0, 4,0,0,0 ), + /* Let Linux know about bus 1 */ + IRQ_SLOT(0, 1,4,3, 0,0,0,0 ), + } +}; unsigned long write_pirq_routing_table(unsigned long addr) { - - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - unsigned slot_num; - uint8_t *v; - - uint8_t sum=0; - int i; - - unsigned char bus_chain_0; - unsigned char bus_8131_1; - unsigned char bus_8131_2; - unsigned char bus_8111_1; - { - device_t dev; - - /* HT chain 0 */ - bus_chain_0 = node_link_to_bus(0, 0); - if (bus_chain_0 == 0) { - printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n"); - bus_chain_0 = 1; - } - - /* 8111 */ - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0)); - if (dev) { - bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n"); - - bus_8111_1 = 4; - } - /* 8131-1 */ - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0)); - if (dev) { - bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - - } - else { - printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n"); - - bus_8131_1 = 2; - } - /* 8131-2 */ - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0)); - if (dev) { - bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - - } - else { - printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n"); - - bus_8131_2 = 3; - } - } - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be betweeen 0xf0000 & 0x100000 */ - printk_info("Writing IRQ routing tables to 0x%x...", addr); - - pirq = (void *)(addr); - v = (uint8_t *)(addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = bus_chain_0; - pirq->rtr_devfn = (4<<3)|3; - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1022; - pirq->rtr_device = 0x746b; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *) ( &pirq->checksum + 1); - slot_num = 0; - - { - device_t dev; - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x04,3)); - if (dev) { - /* initialize PCI interupts - these assignments depend - on the PCB routing of PINTA-D - - PINTA = IRQ5 - PINTB = IRQ9 - PINTC = IRQ11 - PINTD = IRQ10 - */ - pci_write_config16(dev, 0x56, 0xab95); - } - } - - printk_info("setting Onboard AMD Southbridge \n"); - static const unsigned char slotIrqs_1_4[4] = { 5, 9, 11, 10 }; - pci_assign_irqs(bus_chain_0, 4, slotIrqs_1_4); - write_pirq_info(pirq_info, bus_chain_0,(4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; slot_num++; - - printk_info("setting Onboard AMD USB \n"); - static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 10 }; - pci_assign_irqs(bus_8111_1, 0, slotIrqs_8111_1_0); - write_pirq_info(pirq_info, bus_8111_1,0, 0, 0, 0, 0, 0, 0, 0x4, 0xdef8, 0, 0); - pirq_info++; slot_num++; - - printk_info("setting Onboard ATI Display Adapter\n"); - static const unsigned char slotIrqs_8111_1_6[4] = { 11, 0, 0, 0 }; - pci_assign_irqs(bus_8111_1, 6, slotIrqs_8111_1_6); - write_pirq_info(pirq_info, bus_8111_1,(6<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); - pirq_info++; slot_num++; - - printk_info("setting Slot 1\n"); - static const unsigned char slotIrqs_8131_2_3[4] = { 5, 9, 11, 10 }; - pci_assign_irqs(bus_8131_2, 3, slotIrqs_8131_2_3); - write_pirq_info(pirq_info, bus_8131_2,(3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0); - pirq_info++; slot_num++; - - printk_info("setting Slot 2\n"); - static const unsigned char slotIrqs_8131_2_1[4] = { 9, 11, 10, 5 }; - pci_assign_irqs(bus_8131_2, 1, slotIrqs_8131_2_1); - write_pirq_info(pirq_info, bus_8131_2,(1<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0); - pirq_info++; slot_num++; - - printk_info("setting Slot 3\n"); - static const unsigned char slotIrqs_8131_1_3[4] = { 10, 5, 9, 11 }; - pci_assign_irqs(bus_8131_1, 3, slotIrqs_8131_1_3); - write_pirq_info(pirq_info, bus_8131_1,(3<<3)|0, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x3, 0); - pirq_info++; slot_num++; - - printk_info("setting Slot 4\n"); - static const unsigned char slotIrqs_8131_1_2[4] = { 11, 10, 5, 9 }; - pci_assign_irqs(bus_8131_1, 2, slotIrqs_8131_1_2); - write_pirq_info(pirq_info, bus_8131_1,(2<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0x4, 0); - pirq_info++; slot_num++; - - printk_info("setting Slot 5 \n"); - static const unsigned char slotIrqs_8111_1_4[4] = { 5, 9, 11, 10 }; - pci_assign_irqs(bus_8111_1, 4, slotIrqs_8111_1_4); - write_pirq_info(pirq_info, bus_8111_1,(4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x5, 0); - pirq_info++; slot_num++; - - printk_info("setting Onboard SI Serail ATA\n"); - static const unsigned char slotIrqs_8111_1_5[4] = { 10, 0, 0, 0 }; - pci_assign_irqs(bus_8111_1, 5, slotIrqs_8111_1_5); - write_pirq_info(pirq_info, bus_8111_1,(5<<3)|0, 0x4, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); - pirq_info++; slot_num++; - - printk_info("setting Onboard Intel NIC\n"); - static const unsigned char slotIrqs_8111_1_8[4] = { 11, 0, 0, 0 }; - pci_assign_irqs(bus_8111_1, 8, slotIrqs_8111_1_8); - write_pirq_info(pirq_info, bus_8111_1,(8<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); - pirq_info++; slot_num++; - - printk_info("setting Onboard Adaptec SCSI\n"); - static const unsigned char slotIrqs_8131_1_6[4] = { 5, 9, 0, 0 }; - pci_assign_irqs(bus_8131_1, 6, slotIrqs_8131_1_6); - write_pirq_info(pirq_info, bus_8131_1,(6<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0); - pirq_info++; slot_num++; -#if 0 - //?? - write_pirq_info(pirq_info, bus_8131_1,(5<<3)|0, 0x3, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0); - pirq_info++; slot_num++; -#endif - - printk_info("setting Onboard Broadcom NIC\n"); - static const unsigned char slotIrqs_8131_1_9[4] = { 5, 9, 0, 0 }; - pci_assign_irqs(bus_8131_1, 9, slotIrqs_8131_1_9); - write_pirq_info(pirq_info, bus_8131_1,(9<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0); - pirq_info++; slot_num++; -#if 0 - //?? what's this? - write_pirq_info(pirq_info, bus_8131_2,(4<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x6, 0); - pirq_info++; slot_num++; -#endif - -#if 0 - //?? what's this? - write_pirq_info(pirq_info, bus_8131_2,(5<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0x7, 0); - pirq_info++; slot_num++; -#endif - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - return (unsigned long) pirq_info; - + return copy_pirq_routing_table(addr); } diff --git a/src/mainboard/tyan/s2882/reset.c b/src/mainboard/tyan/s2882/reset.c new file mode 100644 index 0000000000..3db3956ec6 --- /dev/null +++ b/src/mainboard/tyan/s2882/reset.c @@ -0,0 +1,6 @@ +#include "../../../southbridge/amd/amd8111/amd8111_reset.c" + +void hard_reset(void) +{ + amd8111_hard_reset(0, 0); +} diff --git a/src/mainboard/tyan/s2885/Config.lb b/src/mainboard/tyan/s2885/Config.lb index a29c713ac6..f6ea627f8b 100644 --- a/src/mainboard/tyan/s2885/Config.lb +++ b/src/mainboard/tyan/s2885/Config.lb @@ -44,7 +44,7 @@ driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -#object reset.o +object reset.o if USE_DCACHE_RAM @@ -66,7 +66,7 @@ end end else - + ## ## Romcc output ## diff --git a/src/mainboard/tyan/s2885/Options.lb b/src/mainboard/tyan/s2885/Options.lb index 7bc324e606..79d60a3e3b 100644 --- a/src/mainboard/tyan/s2885/Options.lb +++ b/src/mainboard/tyan/s2885/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -87,13 +84,6 @@ default HAVE_FALLBACK_BOOT=1 default HAVE_HARD_RESET=1 ## -## Funky hard reset implementation -## -default HARD_RESET_BUS=3 -default HARD_RESET_DEVICE=4 -default HARD_RESET_FUNCTION=0 - -## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 diff --git a/src/mainboard/tyan/s2885/auto.c b/src/mainboard/tyan/s2885/auto.c index cff103b9cc..8275f6d5d7 100644 --- a/src/mainboard/tyan/s2885/auto.c +++ b/src/mainboard/tyan/s2885/auto.c @@ -26,20 +26,52 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +/* Look up a which bus a given node/link combination is on. + * return 0 when we can't find the answer. + */ +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + unsigned reg; + + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + unsigned config_map; + config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + if ((config_map & 3) != 3) { + continue; + } + if ((((config_map >> 4) & 7) == node) && + (((config_map >> 8) & 3) == link)) + { + return (config_map >> 16) & 0xff; + } + } + return 0; +} + static void hard_reset(void) { - set_bios_reset(); + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 3); + + set_bios_reset(); /* enable cf9 */ - pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + pci_write_config8(dev, 0x41, 0xf1); /* reset */ outb(0x0e, 0x0cf9); } static void soft_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 0); + set_bios_reset(); - pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); + pci_write_config8(dev, 0x47, 1); } static void memreset_setup(void) @@ -192,7 +224,7 @@ static void main(unsigned long bist) || (id.coreid != 0) #endif ) { - stop_this_cpu(); + stop_this_cpu(); // it will stop all cores except core0 of cpu0 } } @@ -223,4 +255,5 @@ static void main(unsigned long bist) sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + } diff --git a/src/mainboard/tyan/s2885/cache_as_ram_auto.c b/src/mainboard/tyan/s2885/cache_as_ram_auto.c index 3d27071031..85d4da9227 100644 --- a/src/mainboard/tyan/s2885/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2885/cache_as_ram_auto.c @@ -13,7 +13,6 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" - #include "northbridge/amd/amdk8/cpu_rev.c" #define K8_HT_FREQ_1G_SUPPORT 0 #include "northbridge/amd/amdk8/incoherent_ht.c" @@ -38,20 +37,52 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +/* Look up a which bus a given node/link combination is on. + * return 0 when we can't find the answer. + */ +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + unsigned reg; + + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + unsigned config_map; + config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + if ((config_map & 3) != 3) { + continue; + } + if ((((config_map >> 4) & 7) == node) && + (((config_map >> 8) & 3) == link)) + { + return (config_map >> 16) & 0xff; + } + } + return 0; +} + static void hard_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 3); + set_bios_reset(); /* enable cf9 */ - pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + pci_write_config8(dev, 0x41, 0xf1); /* reset */ outb(0x0e, 0x0cf9); } static void soft_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 0); + set_bios_reset(); - pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); + pci_write_config8(dev, 0x47, 1); } static void memreset_setup(void) @@ -103,6 +134,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #include "cpu/amd/dualcore/dualcore.c" +#else +#include "cpu/amd/model_fxx/node_id.c" #endif #define FIRST_CPU 1 @@ -159,6 +192,7 @@ void amd64_main(unsigned long bist) enumerate_ht_chain(); + /* Setup the ck804 */ amd8111_enable_rom(); /* Is this a deliberate reset by the bios */ @@ -296,15 +330,10 @@ void amd64_main(unsigned long bist) uart_init(); console_init(); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); setup_s2885_resource_map(); -#if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); - dump_pci_device(PCI_DEV(0, 0x19, 0)); -#endif needs_reset = setup_coherent_ht_domain(); @@ -319,17 +348,10 @@ void amd64_main(unsigned long bist) } enable_smbus(); -#if 0 - dump_spd_registers(&cpu[0]); -#endif -#if 0 - dump_smbus_registers(); -#endif memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); - #if 1 { /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ diff --git a/src/mainboard/tyan/s2885/mptable.c b/src/mainboard/tyan/s2885/mptable.c index 2396ade53e..a9683d577c 100644 --- a/src/mainboard/tyan/s2885/mptable.c +++ b/src/mainboard/tyan/s2885/mptable.c @@ -7,6 +7,42 @@ #include <cpu/amd/dualcore.h> #endif + +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + device_t dev; + unsigned reg; + + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + if (!dev) { + return 0; + } + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + uint32_t config_map; + unsigned dst_node; + unsigned dst_link; + unsigned bus_base; + config_map = pci_read_config32(dev, reg); + if ((config_map & 3) != 3) { + continue; + } + dst_node = (config_map >> 4) & 7; + dst_link = (config_map >> 8) & 3; + bus_base = (config_map >> 16) & 0xff; +#if 0 + printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", + dst_node, dst_link, bus_base, + reg, config_map); +#endif + if ((dst_node == node) && (dst_link == link)) + { + return bus_base; + } + } + return 0; +} + + void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; @@ -51,9 +87,14 @@ void *smp_write_config_table(void *v) { device_t dev; + /* HT chain 0 */ + bus_8151_0 = node_link_to_bus(0, 0); + if (bus_8151_0 == 0) { + printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n"); + bus_8151_0 = 1; + } /* 8151 */ - bus_8151_0 = 1; - dev = dev_find_slot(1, PCI_DEVFN(0x02,0)); + dev = dev_find_slot(bus_8151_0, PCI_DEVFN(0x02,0)); if (dev) { bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); // printk_debug("bus_8151_1=%d\n",bus_8151_1); diff --git a/src/mainboard/tyan/s2885/reset.c b/src/mainboard/tyan/s2885/reset.c new file mode 100644 index 0000000000..63958185f6 --- /dev/null +++ b/src/mainboard/tyan/s2885/reset.c @@ -0,0 +1,6 @@ +#include "../../../southbridge/amd/amd8111/amd8111_reset.c" + +void hard_reset(void) +{ + amd8111_hard_reset(0, 2); +} diff --git a/src/mainboard/tyan/s2891/Config.lb b/src/mainboard/tyan/s2891/Config.lb index 53a7fee36e..6341926115 100644 --- a/src/mainboard/tyan/s2891/Config.lb +++ b/src/mainboard/tyan/s2891/Config.lb @@ -346,12 +346,13 @@ chip northbridge/amd/amdk8/root_complex end # pci_domain # chip drivers/generic/debug # device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all +# device pnp 0.1 off end # pci_regs_all # device pnp 0.2 off end # mem # device pnp 0.3 off end # cpuid -# device pnp 0.4 on end # smbus_regs_all +# device pnp 0.4 off end # smbus_regs_all # device pnp 0.5 off end # dual core msr # device pnp 0.6 off end # cache size # device pnp 0.7 off end # tsc +# device pnp 0.8 on end # hard_reset # end end # root_complex diff --git a/src/mainboard/tyan/s2891/Options.lb b/src/mainboard/tyan/s2891/Options.lb index 7147c69d76..58b052e33d 100644 --- a/src/mainboard/tyan/s2891/Options.lb +++ b/src/mainboard/tyan/s2891/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -92,10 +89,6 @@ default HAVE_FALLBACK_BOOT=1 ## default HAVE_HARD_RESET=1 -#default HARD_RESET_BUS=1 -#default HARD_RESET_DEVICE=4 -#default HARD_RESET_FUNCTION=0 - ## ## Build code to export a programmable irq routing table ## @@ -134,7 +127,7 @@ default K8_E0_MEM_HOLE_SIZEK=0x100000 #CK804 setting -default CK804_DEVN_BASE=0 +#default CK804_DEVN_BASE=0 #BTEXT Console #default CONFIG_CONSOLE_BTEXT=1 diff --git a/src/mainboard/tyan/s2891/auto.c b/src/mainboard/tyan/s2891/auto.c index 4a8ef3f952..4637b4e9c6 100644 --- a/src/mainboard/tyan/s2891/auto.c +++ b/src/mainboard/tyan/s2891/auto.c @@ -87,7 +87,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) #define CK804_NUM 1 -#include "southbridge/nvidia/ck804/ck804_early_setup.h" #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" #include "southbridge/nvidia/ck804/ck804_early_setup.c" @@ -136,6 +135,7 @@ static void main(unsigned long bist) enable_lapic(); init_timer(); + #if CONFIG_LOGICAL_CPUS==1 id = get_node_core_id_x(); if(id.coreid == 0) { @@ -152,16 +152,19 @@ static void main(unsigned long bist) distinguish_cpu_resets(nodeid); #endif + post_code(0x31); if (!boot_cpu() #if CONFIG_LOGICAL_CPUS==1 || (id.coreid != 0) #endif ) { - stop_this_cpu(); + stop_this_cpu(); // it will stop all cores except core0 of cpu0 } } + post_code(0x32); + w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); @@ -174,6 +177,7 @@ static void main(unsigned long bist) needs_reset = setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched start_other_cores(); #endif needs_reset |= ht_setup_chains_x(); @@ -190,5 +194,4 @@ static void main(unsigned long bist) memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); - } diff --git a/src/mainboard/tyan/s2891/cache_as_ram_auto.c b/src/mainboard/tyan/s2891/cache_as_ram_auto.c index ba2dfc1f8c..b78a899764 100644 --- a/src/mainboard/tyan/s2891/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2891/cache_as_ram_auto.c @@ -15,6 +15,7 @@ #include "northbridge/amd/amdk8/cpu_rev.c" //#define K8_HT_FREQ_1G_SUPPORT 1 +//#define K8_SCAN_PCI_BUS 1 #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" @@ -84,6 +85,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #include "cpu/amd/dualcore/dualcore.c" +#else +#include "cpu/amd/model_fxx/node_id.c" #endif #define FIRST_CPU 1 @@ -259,6 +262,7 @@ void amd64_main(unsigned long bist) goto cpu_reset_x; } distinguish_cpu_resets(id.nodeid); +// start_other_core(id.nodeid); } #else if (cpu_init_detected(nodeid)) { @@ -292,16 +296,14 @@ void amd64_main(unsigned long bist) report_bist_failure(bist); setup_s2891_resource_map(); -#if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); - dump_pci_device(PCI_DEV(0, 0x19, 0)); -#endif needs_reset = setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched start_other_cores(); #endif + // automatically set that for you, but you might meet tight space needs_reset |= ht_setup_chains_x(); needs_reset |= ck804_early_setup_x(); @@ -312,20 +314,10 @@ void amd64_main(unsigned long bist) } enable_smbus(); -#if 0 - dump_spd_registers(&cpu[0]); -#endif -#if 0 - dump_smbus_registers(); -#endif memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); -#if 0 - dump_pci_devices(); -#endif - #if 1 { /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ @@ -342,6 +334,7 @@ void amd64_main(unsigned long bist) } #endif +#if 1 cpu_reset_x: @@ -386,7 +379,7 @@ cpu_reset_x: "movl %%ebx, %0\n\t" :"=a" (new_cpu_reset) ); - + /* We can not go back any more, we lost old stack data in cache as ram*/ if(new_cpu_reset==0) { print_debug("Use Ram as Stack now - done\r\n"); @@ -404,6 +397,7 @@ cpu_reset_x: copy_and_run(new_cpu_reset); /* We will not return */ } +#endif print_debug("should not be here -\r\n"); diff --git a/src/mainboard/tyan/s2891/irq_tables.c b/src/mainboard/tyan/s2891/irq_tables.c index d6f75a0950..0d880a23f6 100644 --- a/src/mainboard/tyan/s2891/irq_tables.c +++ b/src/mainboard/tyan/s2891/irq_tables.c @@ -18,7 +18,11 @@ const struct irq_routing_table intel_irq_routing_table = { 0x005c, /* Device */ 0, /* Crap (miniport) */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ +#if CK804_DEVN_BASE==0 0x5a, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ +#else + 0x4a, +#endif { {1,((CK804_DEVN_BASE+9)<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0}, {0x5,(1<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0}, diff --git a/src/mainboard/tyan/s2891/mptable.c b/src/mainboard/tyan/s2891/mptable.c index e8d5f4ccc9..e62ec6eef1 100644 --- a/src/mainboard/tyan/s2891/mptable.c +++ b/src/mainboard/tyan/s2891/mptable.c @@ -7,6 +7,41 @@ #include <cpu/amd/dualcore.h> #endif + +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + device_t dev; + unsigned reg; + + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + if (!dev) { + return 0; + } + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + uint32_t config_map; + unsigned dst_node; + unsigned dst_link; + unsigned bus_base; + config_map = pci_read_config32(dev, reg); + if ((config_map & 3) != 3) { + continue; + } + dst_node = (config_map >> 4) & 7; + dst_link = (config_map >> 8) & 3; + bus_base = (config_map >> 16) & 0xff; +#if 0 + printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", + dst_node, dst_link, bus_base, + reg, config_map); +#endif + if ((dst_node == node) && (dst_link == link)) + { + return bus_base; + } + } + return 0; +} + void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; @@ -52,22 +87,60 @@ void *smp_write_config_table(void *v) { device_t dev; + bus_ck804_0 = node_link_to_bus(0, 0); + if (bus_ck804_0 == 0) { + printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n"); + bus_ck804_0 = 1; + } /* CK804 */ - bus_ck804_0 = 1; dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x09,0)); if (dev) { bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); +#if 0 + bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_2++; +#else bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_ck804_4++; +#endif } else { printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x09); bus_ck804_1 = 2; +#if 0 + bus_ck804_2 = 3; +#else bus_ck804_4 = 3; +#endif } +#if 0 + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0b,0)); + if (dev) { + bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_3++; + } + else { + printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x0b); + + bus_ck804_3 = bus_ck804_2+1; + } + + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0c,0)); + if (dev) { + bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_4++; + } + else { + printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x0c); + + bus_ck804_4 = bus_ck804_3+1; + } +#endif dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0d,0)); if (dev) { bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS); @@ -157,12 +230,9 @@ void *smp_write_config_table(void *v) pci_write_config32(dev, 0x7c, dword); dword = 0x12008a00; - - pci_write_config32(dev, 0x80, dword); dword = 0x0000007d; - pci_write_config32(dev, 0x84, dword); } @@ -199,40 +269,51 @@ void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_ck804, 0xf); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+1)<<2)|1, apicid_ck804, 0xa); +// 10 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|0, apicid_ck804, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|0, apicid_ck804, 0x15); // 21 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|1, apicid_ck804, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|1, apicid_ck804, 0x14); // 20 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +7)<<2)|0, apicid_ck804, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +7)<<2)|0, apicid_ck804, 0x17); // 23 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +8)<<2)|0, apicid_ck804, 0x16); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +8)<<2)|0, apicid_ck804, 0x16); // 22 -#if 1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|0, apicid_ck804, 0x12); // +#if CK804_DEVN_BASE == 0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|0, apicid_ck804, 0x12); // 18 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|1, apicid_ck804, 0x13); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|2, apicid_ck804, 0x10); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|3, apicid_ck804, 0x11); // +#else + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|0, apicid_ck804, 0x11); // 17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|1, apicid_ck804, 0x12); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|2, apicid_ck804, 0x13); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|3, apicid_ck804, 0x10); // #endif -#if 1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|0, apicid_ck804, 0x11); // +#if CK804_DEVN_BASE == 0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|0, apicid_ck804, 0x11); // 17 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|1, apicid_ck804, 0x12); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|2, apicid_ck804, 0x13); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|3, apicid_ck804, 0x10); // +#else + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|0, apicid_ck804, 0x10); // 16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|1, apicid_ck804, 0x11); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|2, apicid_ck804, 0x12); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|3, apicid_ck804, 0x13); // #endif - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (7<<2)|0, apicid_ck804, 0x13); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (7<<2)|0, apicid_ck804, 0x13); // 19 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|0, apicid_8131_2, 0x0); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|0, apicid_8131_2, 0x0); //24+4+0 = 28 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|1, apicid_8131_2, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|0, apicid_8131_1, 0x0); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|0, apicid_8131_1, 0x0); // 24 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|1, apicid_8131_1, 0x1);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|2, apicid_8131_1, 0x2);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|3, apicid_8131_1, 0x3);// - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|0, apicid_8131_1, 0x2); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|0, apicid_8131_1, 0x2); // 26 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|1, apicid_8131_1, 0x3);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|2, apicid_8131_1, 0x0);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|3, apicid_8131_1, 0x1);// diff --git a/src/mainboard/tyan/s2892/Options.lb b/src/mainboard/tyan/s2892/Options.lb index 20b58bce85..8a229a1269 100644 --- a/src/mainboard/tyan/s2892/Options.lb +++ b/src/mainboard/tyan/s2892/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -92,10 +89,6 @@ default HAVE_FALLBACK_BOOT=1 ## default HAVE_HARD_RESET=1 -#default HARD_RESET_BUS=1 -#default HARD_RESET_DEVICE=4 -#default HARD_RESET_FUNCTION=0 - ## ## Build code to export a programmable irq routing table ## diff --git a/src/mainboard/tyan/s2892/auto.c b/src/mainboard/tyan/s2892/auto.c index d2512e9f61..25967056de 100644 --- a/src/mainboard/tyan/s2892/auto.c +++ b/src/mainboard/tyan/s2892/auto.c @@ -142,7 +142,6 @@ static void main(unsigned long bist) enable_lapic(); init_timer(); - #if CONFIG_LOGICAL_CPUS==1 id = get_node_core_id_x(); if(id.coreid == 0) { @@ -150,6 +149,7 @@ static void main(unsigned long bist) asm volatile ("jmp __cpu_reset"); } distinguish_cpu_resets(id.nodeid); +// start_other_core(id.nodeid); } #else nodeid = lapicid(); @@ -164,7 +164,7 @@ static void main(unsigned long bist) || (id.coreid != 0) #endif ) { - stop_this_cpu(); + stop_this_cpu(); // it will stop all cores except core0 of cpu0 } } @@ -174,13 +174,14 @@ static void main(unsigned long bist) console_init(); /* Halt if there was a built in self test failure */ - report_bist_failure(bist); +// report_bist_failure(bist); setup_s2892_resource_map(); needs_reset = setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched start_other_cores(); #endif needs_reset |= ht_setup_chains_x(); diff --git a/src/mainboard/tyan/s2892/cache_as_ram_auto.c b/src/mainboard/tyan/s2892/cache_as_ram_auto.c index 30a78f5a96..5158bccf55 100644 --- a/src/mainboard/tyan/s2892/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2892/cache_as_ram_auto.c @@ -86,6 +86,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #include "cpu/amd/dualcore/dualcore.c" +#else +#include "cpu/amd/model_fxx/node_id.c" #endif #define FIRST_CPU 1 @@ -295,15 +297,10 @@ void amd64_main(unsigned long bist) report_bist_failure(bist); setup_s2892_resource_map(); -#if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); - dump_pci_device(PCI_DEV(0, 0x19, 0)); -#endif needs_reset = setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS==1 - // It is said that we should start core1 after all core0 launched start_other_cores(); #endif needs_reset |= ht_setup_chains_x(); @@ -316,19 +313,10 @@ void amd64_main(unsigned long bist) } enable_smbus(); -#if 0 - dump_spd_registers(&cpu[0]); -#endif -#if 0 - dump_smbus_registers(); -#endif memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); -#if 0 - dump_pci_devices(); -#endif #if 1 { @@ -346,6 +334,7 @@ void amd64_main(unsigned long bist) } #endif +#if 1 cpu_reset_x: @@ -408,6 +397,7 @@ cpu_reset_x: copy_and_run(new_cpu_reset); /* We will not return */ } +#endif print_debug("should not be here -\r\n"); diff --git a/src/mainboard/tyan/s2892/mptable.c b/src/mainboard/tyan/s2892/mptable.c index b4f26aaeba..02754a1b34 100644 --- a/src/mainboard/tyan/s2892/mptable.c +++ b/src/mainboard/tyan/s2892/mptable.c @@ -7,6 +7,41 @@ #include <cpu/amd/dualcore.h> #endif + +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + device_t dev; + unsigned reg; + + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + if (!dev) { + return 0; + } + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + uint32_t config_map; + unsigned dst_node; + unsigned dst_link; + unsigned bus_base; + config_map = pci_read_config32(dev, reg); + if ((config_map & 3) != 3) { + continue; + } + dst_node = (config_map >> 4) & 7; + dst_link = (config_map >> 8) & 3; + bus_base = (config_map >> 16) & 0xff; +#if 0 + printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", + dst_node, dst_link, bus_base, + reg, config_map); +#endif + if ((dst_node == node) && (dst_link == link)) + { + return bus_base; + } + } + return 0; +} + void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; @@ -52,22 +87,60 @@ void *smp_write_config_table(void *v) { device_t dev; + bus_ck804_0 = node_link_to_bus(0, 0); + if (bus_ck804_0 == 0) { + printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n"); + bus_ck804_0 = 1; + } /* CK804 */ - bus_ck804_0 = 1; dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x09,0)); if (dev) { bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); +#if 0 + bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_2++; +#else bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_ck804_4++; +#endif } else { printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x09); bus_ck804_1 = 2; +#if 0 + bus_ck804_2 = 3; +#else bus_ck804_4 = 3; +#endif } +#if 0 + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0b,0)); + if (dev) { + bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_3++; + } + else { + printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x0b); + + bus_ck804_3 = bus_ck804_2+1; + } + + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0c,0)); + if (dev) { + bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_4++; + } + else { + printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x0c); + + bus_ck804_4 = bus_ck804_3+1; + } +#endif dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0d,0)); if (dev) { bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS); @@ -152,6 +225,8 @@ void *smp_write_config_table(void *v) smp_write_ioapic(mc, apicid_ck804, 0x11, res->base); } + /* Initialize interrupt mapping*/ + dword = 0x0000d218; pci_write_config32(dev, 0x7c, dword); @@ -195,57 +270,77 @@ void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_ck804, 0xf); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+1)<<2)|1, apicid_ck804, 0xa); +// 10 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|0, apicid_ck804, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|0, apicid_ck804, 0x15); // 21 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|1, apicid_ck804, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|1, apicid_ck804, 0x14); // 20 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +7)<<2)|0, apicid_ck804, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +7)<<2)|0, apicid_ck804, 0x17); // 23 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +8)<<2)|0, apicid_ck804, 0x16); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +8)<<2)|0, apicid_ck804, 0x16); // 22 -#if 1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|0, apicid_ck804, 0x12); // +#if CK804_DEVN_BASE == 0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|0, apicid_ck804, 0x12); // 18 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|1, apicid_ck804, 0x13); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|2, apicid_ck804, 0x10); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|3, apicid_ck804, 0x11); // +#else + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|0, apicid_ck804, 0x11); // 17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|1, apicid_ck804, 0x12); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|2, apicid_ck804, 0x13); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|3, apicid_ck804, 0x10); // #endif -#if 1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|0, apicid_ck804, 0x11); // +#if CK804_DEVN_BASE == 0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|0, apicid_ck804, 0x11); // 17 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|1, apicid_ck804, 0x12); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|2, apicid_ck804, 0x13); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|3, apicid_ck804, 0x10); // +#else + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|0, apicid_ck804, 0x10); // 16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|1, apicid_ck804, 0x11); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|2, apicid_ck804, 0x12); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|3, apicid_ck804, 0x13); // #endif - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|0, apicid_ck804, 0x10); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|1, apicid_ck804, 0x11); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|2, apicid_ck804, 0x12); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|3, apicid_ck804, 0x13); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (6<<2)|0, apicid_ck804, 0x12); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (8<<2)|0, apicid_ck804, 0x12); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|0, apicid_ck804, 0x10); // 16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|1, apicid_ck804, 0x11); // 17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|2, apicid_ck804, 0x12); // 18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|3, apicid_ck804, 0x13); // 19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (6<<2)|0, apicid_ck804, 0x12); // 18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (8<<2)|0, apicid_ck804, 0x12); // 18 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|0, apicid_8131_2, 0x0);// +//Channel B of 8131 + + +//Onboard Broadcom NIC + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|0, apicid_8131_2, 0x0);//24+4= 28 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|1, apicid_8131_2, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (7<<2)|0, apicid_8131_2, 0x0);// +//SO DIMM PCI-X + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (7<<2)|0, apicid_8131_2, 0x0);//28 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (7<<2)|1, apicid_8131_2, 0x1); - - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, apicid_8131_2, 0x2); // +//Slot 4 PCIX 133/100/66 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, apicid_8131_2, 0x2); // 30 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, apicid_8131_2, 0x3);// - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, apicid_8131_2, 0x0);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, apicid_8131_2, 0x0);// 28 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, apicid_8131_2, 0x1);// - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|0, apicid_8131_1, 0x3); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|1, apicid_8131_1, 0x0);// +//Channel A of 8131 + +//Slot 5 PCIX 133/100/66 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|0, apicid_8131_1, 0x3); //28 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|1, apicid_8131_1, 0x0);//24 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, apicid_8131_1, 0x1);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, apicid_8131_1, 0x2);// - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, apicid_8131_1, 0x2); // +//Slot 6 PCIX 133/100/66 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, apicid_8131_1, 0x2); // 27 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|1, apicid_8131_1, 0x3);// - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, apicid_8131_1, 0x0);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, apicid_8131_1, 0x0);// 24 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|3, apicid_8131_1, 0x1);// diff --git a/src/mainboard/tyan/s2895/Options.lb b/src/mainboard/tyan/s2895/Options.lb index e2d220201b..fc63823480 100644 --- a/src/mainboard/tyan/s2895/Options.lb +++ b/src/mainboard/tyan/s2895/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -90,10 +87,6 @@ default HAVE_FALLBACK_BOOT=1 ## default HAVE_HARD_RESET=1 -#default HARD_RESET_BUS=1 -#default HARD_RESET_DEVICE=4 -#default HARD_RESET_FUNCTION=0 - ## ## Build code to export a programmable irq routing table ## @@ -134,7 +127,7 @@ default CONFIG_LOGICAL_CPUS=1 default K8_E0_MEM_HOLE_SIZEK=0x100000 #CK804 setting -default CK804_DEVN_BASE=0 +#default CK804_DEVN_BASE=0 #VGA default CONFIG_CONSOLE_VGA=1 diff --git a/src/mainboard/tyan/s2895/auto.c b/src/mainboard/tyan/s2895/auto.c index b6f121e6e8..0a26f21735 100644 --- a/src/mainboard/tyan/s2895/auto.c +++ b/src/mainboard/tyan/s2895/auto.c @@ -14,7 +14,7 @@ #include "ram/ramtest.c" #include "northbridge/amd/amdk8/cpu_rev.c" -#define K8_HT_FREQ_1G_SUPPORT 1 +//#define K8_HT_FREQ_1G_SUPPORT 1 #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" @@ -70,8 +70,9 @@ static void sio_gpio_setup(void){ unsigned value; +// lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); // Already enable in failover.c + #if 1 - /*Enable onboard scsi*/ lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c); lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1))); @@ -117,10 +118,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) #define CK804_NUM 2 -#define CK804B_BUSN 0xc +#define CK804B_BUSN 0x80 #define CK804_USE_NIC 1 #define CK804_USE_ACI 1 -#include "southbridge/nvidia/ck804/ck804_early_setup.h" #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" //set GPIO to input mode @@ -192,11 +192,12 @@ static void main(unsigned long bist) enable_lapic(); init_timer(); + post_code(0x30); #if CONFIG_LOGICAL_CPUS==1 #if ENABLE_APIC_EXT_ID == 1 #if LIFT_BSP_APIC_ID == 0 - if( id.nodeid != 0 ) + if( id.nodeid != 0 ) //all except cores in node0 #endif lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); #endif @@ -213,7 +214,7 @@ static void main(unsigned long bist) #if LIFT_BSP_APIC_ID == 0 if(nodeid != 0) #endif - lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); + lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); // CPU apicid is from 0x10 #endif @@ -223,16 +224,18 @@ static void main(unsigned long bist) distinguish_cpu_resets(nodeid); #endif + post_code(0x31); if (!boot_cpu() #if CONFIG_LOGICAL_CPUS==1 || (id.coreid != 0) #endif ) { - stop_this_cpu(); + stop_this_cpu(); // it will stop all cores except core0 of cpu0 } } + post_code(0x32); lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); @@ -247,6 +250,7 @@ static void main(unsigned long bist) needs_reset = setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched start_other_cores(); #endif diff --git a/src/mainboard/tyan/s2895/cache_as_ram_auto.c b/src/mainboard/tyan/s2895/cache_as_ram_auto.c index fde94cc780..2cf73c333f 100644 --- a/src/mainboard/tyan/s2895/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2895/cache_as_ram_auto.c @@ -13,9 +13,10 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" - #include "northbridge/amd/amdk8/cpu_rev.c" -#define K8_HT_FREQ_1G_SUPPORT 0 +#define K8_HT_FREQ_1G_SUPPORT 1 +#define K8_ALLOCATE_IO_RANGE 1 +//#define K8_SCAN_PCI_BUS 1 #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" @@ -75,13 +76,11 @@ static void sio_gpio_setup(void){ unsigned value; +// lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); // Already enable in failover.c -#if 1 - /*Enable onboard scsi*/ lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c); lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1))); -#endif } @@ -114,6 +113,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #include "cpu/amd/dualcore/dualcore.c" +#else +#include "cpu/amd/model_fxx/node_id.c" #endif #define FIRST_CPU 1 @@ -121,8 +122,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) #define CK804_NUM 2 -//#define CK804B_BUSN 0x80 -#define CK804B_BUSN 0xc +#define CK804B_BUSN 0x80 #define CK804_USE_NIC 1 #define CK804_USE_ACI 1 @@ -155,13 +155,18 @@ static void sio_setup(void) uint8_t byte; + /* LPC Variable Range Decode 1 0x400-0x47f */ + /* to make sure lpc47b397 gpio on device work */ pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400); + /* subject decoding*/ byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); byte |= 0x20; pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte); + /* LPC Positive Decode 0 */ dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0); + /*decode VAR1, serial 0 */ dword |= (1<<29)|(1<<0); pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); @@ -311,7 +316,7 @@ void amd64_main(unsigned long bist) enable_lapic(); - init_timer(); +// init_timer(); #if CONFIG_LOGICAL_CPUS==1 @@ -323,10 +328,12 @@ void amd64_main(unsigned long bist) #endif if(id.coreid == 0) { if (cpu_init_detected(id.nodeid)) { +// __asm__ volatile ("jmp __cpu_reset"); cpu_reset = 1; goto cpu_reset_x; } distinguish_cpu_resets(id.nodeid); +// start_other_core(id.nodeid); } #else #if ENABLE_APIC_EXT_ID == 1 @@ -337,6 +344,7 @@ void amd64_main(unsigned long bist) #endif if (cpu_init_detected(nodeid)) { +// __asm__ volatile ("jmp __cpu_reset"); cpu_reset = 1; goto cpu_reset_x; } @@ -355,6 +363,8 @@ void amd64_main(unsigned long bist) } } + init_timer(); // only do it it first CPU + lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); @@ -364,10 +374,6 @@ void amd64_main(unsigned long bist) report_bist_failure(bist); setup_s2895_resource_map(); -#if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); - dump_pci_device(PCI_DEV(0, 0x19, 0)); -#endif needs_reset = setup_coherent_ht_domain(); @@ -376,15 +382,7 @@ void amd64_main(unsigned long bist) start_other_cores(); #endif -#if CK804B_BUSN == 0x80 - // You need to preset bus num in PCI_DEV(0, 0x18,1) 0xe0, 0xe4, 0xe8, 0xec - needs_reset |= ht_setup_chains(3); -#else - // automatically set that for you, but you might meet tight space - // Bcause it has two Ck804, we need to set CK804B_BUSN to 0xc (ht_setup_chains_x will let second CK804 use that bus num. - // otherwise ck804_eary_setup can not work rightly. needs_reset |= ht_setup_chains_x(); -#endif needs_reset |= ck804_early_setup_x(); @@ -394,20 +392,10 @@ void amd64_main(unsigned long bist) } enable_smbus(); -#if 0 - dump_spd_registers(&cpu[0]); -#endif -#if 0 - dump_smbus_registers(); -#endif memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); -#if 0 - dump_pci_devices(); -#endif - #if 1 { /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ @@ -424,6 +412,7 @@ void amd64_main(unsigned long bist) } #endif +#if 1 cpu_reset_x: @@ -486,6 +475,7 @@ cpu_reset_x: copy_and_run(new_cpu_reset); /* We will not return */ } +#endif print_err("should not be here -\r\n"); diff --git a/src/mainboard/tyan/s2895/irq_tables.c b/src/mainboard/tyan/s2895/irq_tables.c index cf1a438dc1..aa16866763 100644 --- a/src/mainboard/tyan/s2895/irq_tables.c +++ b/src/mainboard/tyan/s2895/irq_tables.c @@ -403,6 +403,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } + printk_info("done.\n"); + return (unsigned long) pirq_info; } diff --git a/src/mainboard/tyan/s2895/mptable.c b/src/mainboard/tyan/s2895/mptable.c index f6b534d866..810e234af6 100644 --- a/src/mainboard/tyan/s2895/mptable.c +++ b/src/mainboard/tyan/s2895/mptable.c @@ -8,6 +8,41 @@ #include <cpu/amd/dualcore.h> #endif + +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + device_t dev; + unsigned reg; + + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + if (!dev) { + return 0; + } + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + uint32_t config_map; + unsigned dst_node; + unsigned dst_link; + unsigned bus_base; + config_map = pci_read_config32(dev, reg); + if ((config_map & 3) != 3) { + continue; + } + dst_node = (config_map >> 4) & 7; + dst_link = (config_map >> 8) & 3; + bus_base = (config_map >> 16) & 0xff; +#if 0 + printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", + dst_node, dst_link, bus_base, + reg, config_map); +#endif + if ((dst_node == node) && (dst_link == link)) + { + return bus_base; + } + } + return 0; +} + void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; @@ -62,21 +97,71 @@ void *smp_write_config_table(void *v) device_t dev; + bus_ck804_0 = node_link_to_bus(0, 0); + if (bus_ck804_0 == 0) { + printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n"); + bus_ck804_0 = 1; + } /* CK804 */ - bus_ck804_0 = 1; dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x09,0)); if (dev) { bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); +#if 0 + bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_2++; +#else bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_ck804_5++; +#endif } else { printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x09); bus_ck804_1 = 2; +#if 0 + bus_ck804_2 = 3; +#else bus_ck804_5 = 3; +#endif + + } +#if 0 + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0b,0)); + if (dev) { + bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_3++; + } + else { + printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x0b); + + bus_ck804_3 = bus_ck804_2+1; + } + + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0c,0)); + if (dev) { + bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_4++; + } + else { + printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x0c); + + bus_ck804_4 = bus_ck804_3+1; + } + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0d,0)); + if (dev) { + bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_5++; } + else { + printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n",CK804_DEVN_BASE + 0x0d); + + bus_ck804_5 = bus_ck804_4+1; + } +#endif dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0e,0)); if (dev) { @@ -119,6 +204,59 @@ void *smp_write_config_table(void *v) /* CK804b */ +#if 0 + dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x09,0)); + if (dev) { + bus_ck804b_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804b_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804b_2++; + } + else { + printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,CK804_DEVN_BASE+0x09); + + bus_ck804b_1 = bus_ck804b_0+1; + bus_ck804b_2 = bus_ck804b_0+2; + } + + dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0b,0)); + if (dev) { + bus_ck804b_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804b_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804b_3++; + } + else { + printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,CK804_DEVN_BASE+0x0b); + + bus_ck804b_2 = bus_ck804b_0+1; + bus_ck804b_3 = bus_ck804b_0+2; + } + + dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0c,0)); + if (dev) { + bus_ck804b_3 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804b_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804b_4++; + } + else { + printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,CK804_DEVN_BASE+0x0c); + + bus_ck804b_4 = bus_ck804b_3+1; + } + + dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0d,0)); + if (dev) { + bus_ck804b_4 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804b_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804b_5++; + } + else { + printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,CK804_DEVN_BASE+0x0d); + + bus_ck804b_5 = bus_ck804b_4+1; + } + +#endif + dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0e,0)); if (dev) { bus_ck804b_5 = pci_read_config8(dev, PCI_SECONDARY_BUS); @@ -168,7 +306,7 @@ void *smp_write_config_table(void *v) smp_write_ioapic(mc, apicid_ck804, 0x11, res->base); } - dword = 0x0120d218; + dword = 0x0000d218; pci_write_config32(dev, 0x7c, dword); dword = 0x12008a00; @@ -229,58 +367,77 @@ void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_ck804, 0xf); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+1)<<2)|1, apicid_ck804, 0xa); +// 10 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|0, apicid_ck804, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|0, apicid_ck804, 0x15); // 21 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|1, apicid_ck804, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|1, apicid_ck804, 0x14); // 20 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+4)<<2)|0, apicid_ck804, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+4)<<2)|0, apicid_ck804, 0x14); // 20 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +7)<<2)|0, apicid_ck804, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +7)<<2)|0, apicid_ck804, 0x17); // 23 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +8)<<2)|0, apicid_ck804, 0x16); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +8)<<2)|0, apicid_ck804, 0x16); // 22 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +0x0a)<<2)|0, apicid_ck804, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +0x0a)<<2)|0, apicid_ck804, 0x15); // 21 -#if 1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|0, apicid_ck804, 0x12); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|1, apicid_ck804, 0x13); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|2, apicid_ck804, 0x10); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|3, apicid_ck804, 0x11); // +#if CK804_DEVN_BASE == 0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|0, apicid_ck804, 0x12); // 18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|1, apicid_ck804, 0x13); // 19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|2, apicid_ck804, 0x10); // 16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|3, apicid_ck804, 0x11); // 17 +#else + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|0, apicid_ck804, 0x11); // 17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|1, apicid_ck804, 0x12); // 18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|2, apicid_ck804, 0x13); // 19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|3, apicid_ck804, 0x10); // 16 #endif - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05<<2)|0, apicid_ck804, 0x13); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05<<2)|0, apicid_ck804, 0x13); // 19 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|0, apicid_ck804, 0x10); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|1, apicid_ck804, 0x11); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|2, apicid_ck804, 0x12); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|3, apicid_ck804, 0x13); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|0, apicid_ck804, 0x10); // 16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|1, apicid_ck804, 0x11); // 17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|2, apicid_ck804, 0x12); // 18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|3, apicid_ck804, 0x13); // 19 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((CK804_DEVN_BASE+0x0a)<<2)|0, apicid_ck804b, 0x15);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((CK804_DEVN_BASE+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21=53 -#if 1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|0, apicid_ck804b, 0x12);// - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|1, apicid_ck804b, 0x13); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|2, apicid_ck804b, 0x10); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|3, apicid_ck804b, 0x11); // +#if CK804_DEVN_BASE == 0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|0, apicid_ck804b, 0x12);//18+24+4+4=50 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|1, apicid_ck804b, 0x13); // 19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|2, apicid_ck804b, 0x10); // 16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|3, apicid_ck804b, 0x11); // 17 +#else + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|0, apicid_ck804b, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|1, apicid_ck804b, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|2, apicid_ck804b, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|3, apicid_ck804b, 0x10); #endif - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|0, apicid_8131_2, 0x0); // +//Channel B of 8131 + +//Slot 4 PCI-X 100/66 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|0, apicid_8131_2, 0x0); //24+4 = 28 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|1, apicid_8131_2, 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|2, apicid_8131_2, 0x2); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|3, apicid_8131_2, 0x3); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|0, apicid_8131_2, 0x1); // +//Slot 5 PCIX 100/66 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|0, apicid_8131_2, 0x1); //24+4+1 = 29 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|1, apicid_8131_2, 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|2, apicid_8131_2, 0x3);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|3, apicid_8131_2, 0x0);// +//OnBoard LSI SCSI + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|0, apicid_8131_2, 0x2); // 24+4+2 = 30 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|1, apicid_8131_2, 0x3); // 31 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|0, apicid_8131_2, 0x2); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|1, apicid_8131_2, 0x3); +//Channel A of 8131 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|0, apicid_8131_1, 0x0); // +//Slot 6 PCIX 133/100/66 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|0, apicid_8131_1, 0x0); // 24 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|1, apicid_8131_1, 0x1);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|2, apicid_8131_1, 0x2);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|3, apicid_8131_1, 0x3);// diff --git a/src/mainboard/tyan/s4880/Config.lb b/src/mainboard/tyan/s4880/Config.lb index 3b3806f6ac..e3c5b03b40 100644 --- a/src/mainboard/tyan/s4880/Config.lb +++ b/src/mainboard/tyan/s4880/Config.lb @@ -43,7 +43,7 @@ arch i386 end driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -##object reset.o +object reset.o if USE_DCACHE_RAM if CONFIG_USE_INIT diff --git a/src/mainboard/tyan/s4880/Options.lb b/src/mainboard/tyan/s4880/Options.lb index f3d73515ee..fc98b83255 100644 --- a/src/mainboard/tyan/s4880/Options.lb +++ b/src/mainboard/tyan/s4880/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -87,14 +84,6 @@ default HAVE_FALLBACK_BOOT=1 default HAVE_HARD_RESET=1 ## -## Funky hard reset implementation -## -default HARD_RESET_BUS=3 -default HARD_RESET_DEVICE=4 -default HARD_RESET_FUNCTION=0 - - -## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 diff --git a/src/mainboard/tyan/s4880/auto.c b/src/mainboard/tyan/s4880/auto.c index fc1bf58e91..3e0d4825df 100644 --- a/src/mainboard/tyan/s4880/auto.c +++ b/src/mainboard/tyan/s4880/auto.c @@ -95,65 +95,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl) } } -#if 0 -static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes) -{ - /* Routing Table Node i - * - * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c - * i: 0, 1, 2, 3, 4, 5, 6, 7 - * - * [ 0: 3] Request Route - * [0] Route to this node - * [1] Route to Link 0 - * [2] Route to Link 1 - * [3] Route to Link 2 - * [11: 8] Response Route - * [0] Route to this node - * [1] Route to Link 0 - * [2] Route to Link 1 - * [3] Route to Link 2 - * [19:16] Broadcast route - * [0] Route to this node - * [1] Route to Link 0 - * [2] Route to Link 1 - * [3] Route to Link 2 - */ - uint32_t ret=0x00010101; /* default row entry */ - -/* - (L1) (L2) - CPU3-------------CPU1 - (L0)| |(L0) - | | - | | - | | - | | - (L0)| |(L0) - CPU2-------------CPU0---------8131----------8111 - (L2) (L1) (L2) -*/ - - /* Link0 of CPU0 to Link0 of CPU1 */ - /* Link1 of CPU0 to Link2 of CPU2 */ - /* Link2 of CPU1 to Link1 of CPU3 */ - /* Link0 of CPU2 to Link0 of CPU3 */ - - static const unsigned int rows_4p[4][4] = { - { 0x00070101, 0x00010202, 0x00030404, 0x00010204 }, - { 0x00010202, 0x000b0101, 0x00010208, 0x00030808 }, - { 0x00030808, 0x00010208, 0x000b0101, 0x00010202 }, - { 0x00010204, 0x00030404, 0x00010202, 0x00070101 } - }; - - if (!(node>=maxnodes || row>=maxnodes)) { - ret=rows_4p[node][row]; - } - - return ret; -} -#endif - static inline void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_HUB 0x18 @@ -161,6 +102,14 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) smbus_write_byte(SMBUS_HUB , 0x01, device); smbus_write_byte(SMBUS_HUB , 0x03, 0); } +#if 0 +static inline void change_i2c_mux(unsigned device) +{ +#define SMBUS_HUB 0x18 + smbus_write_byte(SMBUS_HUB , 0x01, device); + smbus_write_byte(SMBUS_HUB , 0x03, 0); +} +#endif static inline int spd_read_byte(unsigned device, unsigned address) { @@ -308,22 +257,19 @@ static void main(unsigned long bist) needs_reset = setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS==1 - // It is said that we should start core1 after all core0 launched start_other_cores(); #endif -#if 0 - needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xc0); -#else - // automatically set that for you, but you might meet tight space needs_reset |= ht_setup_chains_x(); -#endif if (needs_reset) { print_info("ht reset -\r\n"); soft_reset(); } +#if 0 + dump_pci_devices(); +#endif enable_smbus(); memreset_setup(); diff --git a/src/mainboard/tyan/s4880/cache_as_ram_auto.c b/src/mainboard/tyan/s4880/cache_as_ram_auto.c index f39ff15b4d..bddcd08820 100644 --- a/src/mainboard/tyan/s4880/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s4880/cache_as_ram_auto.c @@ -325,6 +325,7 @@ void amd64_main(unsigned long bist) enable_lapic(); init_timer(); +// post_code(0x30); #if CONFIG_LOGICAL_CPUS==1 #if ENABLE_APIC_EXT_ID == 1 @@ -355,7 +356,6 @@ void amd64_main(unsigned long bist) distinguish_cpu_resets(nodeid); #endif - if (!boot_cpu() #if CONFIG_LOGICAL_CPUS==1 || (id.coreid != 0) @@ -380,9 +380,9 @@ void amd64_main(unsigned long bist) needs_reset = setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched start_other_cores(); #endif - needs_reset |= ht_setup_chains_x(); if (needs_reset) { diff --git a/src/mainboard/tyan/s4880/reset.c b/src/mainboard/tyan/s4880/reset.c new file mode 100644 index 0000000000..63958185f6 --- /dev/null +++ b/src/mainboard/tyan/s4880/reset.c @@ -0,0 +1,6 @@ +#include "../../../southbridge/amd/amd8111/amd8111_reset.c" + +void hard_reset(void) +{ + amd8111_hard_reset(0, 2); +} diff --git a/src/mainboard/tyan/s4882/Config.lb b/src/mainboard/tyan/s4882/Config.lb index 95ef0464fe..18fec090cf 100644 --- a/src/mainboard/tyan/s4882/Config.lb +++ b/src/mainboard/tyan/s4882/Config.lb @@ -43,7 +43,7 @@ arch i386 end driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -#object reset.o +object reset.o if USE_DCACHE_RAM if CONFIG_USE_INIT diff --git a/src/mainboard/tyan/s4882/Options.lb b/src/mainboard/tyan/s4882/Options.lb index 56a2548228..0c5571aa07 100644 --- a/src/mainboard/tyan/s4882/Options.lb +++ b/src/mainboard/tyan/s4882/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -31,9 +28,9 @@ uses USE_OPTION_TABLE uses LB_CKS_RANGE_START uses LB_CKS_RANGE_END uses LB_CKS_LOC +uses MAINBOARD uses MAINBOARD_PART_NUMBER uses MAINBOARD_VENDOR -uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses LINUXBIOS_EXTRA_VERSION @@ -87,13 +84,6 @@ default HAVE_FALLBACK_BOOT=1 default HAVE_HARD_RESET=1 ## -## Funky hard reset implementation -## -default HARD_RESET_BUS=3 -default HARD_RESET_DEVICE=4 -default HARD_RESET_FUNCTION=0 - -## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 @@ -153,8 +143,8 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="s4882" default MAINBOARD_VENDOR="Tyan" +default MAINBOARD_PART_NUMBER="s4882" default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4882 diff --git a/src/mainboard/tyan/s4882/auto.c b/src/mainboard/tyan/s4882/auto.c index 21d459b6e4..e8d46e7961 100644 --- a/src/mainboard/tyan/s4882/auto.c +++ b/src/mainboard/tyan/s4882/auto.c @@ -26,26 +26,52 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +/* Look up a which bus a given node/link combination is on. + * return 0 when we can't find the answer. + */ +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + unsigned reg; + + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + unsigned config_map; + config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + if ((config_map & 3) != 3) { + continue; + } + if ((((config_map >> 4) & 7) == node) && + (((config_map >> 8) & 3) == link)) + { + return (config_map >> 16) & 0xff; + } + } + return 0; +} + static void hard_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 3); + set_bios_reset(); /* enable cf9 */ - pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + pci_write_config8(dev, 0x41, 0xf1); /* reset */ outb(0x0e, 0x0cf9); } static void soft_reset(void) { - set_bios_reset(); - pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); -} + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 0); -static void soft2_reset(void) -{ set_bios_reset(); - pci_write_config8(PCI_DEV(3, 0x04, 0), 0x47, 1); + pci_write_config8(dev, 0x47, 1); } static void memreset_setup(void) @@ -73,6 +99,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) #define SMBUS_HUB 0x18 int ret,i; unsigned device=(ctrl->channel0[0])>>8; + /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ i=2; do { ret = smbus_write_byte(SMBUS_HUB, 0x01, device); @@ -194,7 +221,7 @@ static void main(unsigned long bist) #if CONFIG_LOGICAL_CPUS==1 set_apicid_cpuid_lo(); - id = get_node_core_id_x(); + id = get_node_core_id_x(); // that is initid #if ENABLE_APIC_EXT_ID == 1 if(id.coreid == 0) { enable_apic_ext_id(id.nodeid); @@ -213,7 +240,7 @@ static void main(unsigned long bist) #if CONFIG_LOGICAL_CPUS==1 #if ENABLE_APIC_EXT_ID == 1 #if LIFT_BSP_APIC_ID == 0 - if( id.nodeid != 0 ) + if( id.nodeid != 0 ) //all except cores in node0 #endif lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); #endif @@ -241,7 +268,7 @@ static void main(unsigned long bist) || (id.coreid != 0) #endif ) { - stop_this_cpu(); + stop_this_cpu(); // it will stop all cores except core0 of cpu0 } } @@ -257,10 +284,10 @@ static void main(unsigned long bist) needs_reset = setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched start_other_cores(); #endif - // automatically set that for you, but you might meet tight space needs_reset |= ht_setup_chains_x(); if (needs_reset) { print_info("ht reset -\r\n"); diff --git a/src/mainboard/tyan/s4882/cache_as_ram_auto.c b/src/mainboard/tyan/s4882/cache_as_ram_auto.c index bbcc49a9cf..234e3a0a58 100644 --- a/src/mainboard/tyan/s4882/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s4882/cache_as_ram_auto.c @@ -37,20 +37,52 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +/* Look up a which bus a given node/link combination is on. + * return 0 when we can't find the answer. + */ +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + unsigned reg; + + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + unsigned config_map; + config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + if ((config_map & 3) != 3) { + continue; + } + if ((((config_map >> 4) & 7) == node) && + (((config_map >> 8) & 3) == link)) + { + return (config_map >> 16) & 0xff; + } + } + return 0; +} + static void hard_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 3); + set_bios_reset(); /* enable cf9 */ - pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + pci_write_config8(dev, 0x41, 0xf1); /* reset */ outb(0x0e, 0x0cf9); } static void soft_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 0); + set_bios_reset(); - pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); + pci_write_config8(dev, 0x47, 1); } static void memreset_setup(void) @@ -77,6 +109,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) #define SMBUS_HUB 0x18 int ret,i; unsigned device=(ctrl->channel0[0])>>8; + /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ i=2; do { ret = smbus_write_byte(SMBUS_HUB, 0x01, device); @@ -109,6 +142,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #include "cpu/amd/dualcore/dualcore.c" +#else +#include "cpu/amd/model_fxx/node_id.c" #endif #define FIRST_CPU 1 #define SECOND_CPU 1 @@ -325,7 +360,6 @@ void amd64_main(unsigned long bist) distinguish_cpu_resets(nodeid); #endif - if (!boot_cpu() #if CONFIG_LOGICAL_CPUS==1 || (id.coreid != 0) @@ -337,22 +371,15 @@ void amd64_main(unsigned long bist) } } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); - dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); setup_s4882_resource_map(); -#if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); - dump_pci_device(PCI_DEV(0, 0x19, 0)); -#endif - + needs_reset = setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS==1 @@ -387,6 +414,7 @@ void amd64_main(unsigned long bist) } #endif +#if 1 cpu_reset_x: @@ -450,6 +478,7 @@ cpu_reset_x: copy_and_run(new_cpu_reset); /* We will not return */ } +#endif print_debug("should not be here -\r\n"); diff --git a/src/mainboard/tyan/s4882/reset.c b/src/mainboard/tyan/s4882/reset.c new file mode 100644 index 0000000000..7f58d01410 --- /dev/null +++ b/src/mainboard/tyan/s4882/reset.c @@ -0,0 +1,6 @@ +#include "../../../southbridge/amd/amd8111/amd8111_reset.c" + +void hard_reset(void) +{ + amd8111_hard_reset(0, 1); +} |