diff options
Diffstat (limited to 'src/mainboard/tyan/s4882')
| -rw-r--r-- | src/mainboard/tyan/s4882/Options.lb | 23 | ||||
| -rw-r--r-- | src/mainboard/tyan/s4882/auto.c | 225 | ||||
| -rw-r--r-- | src/mainboard/tyan/s4882/cmos.layout | 1 | ||||
| -rw-r--r-- | src/mainboard/tyan/s4882/failover.c | 38 | ||||
| -rw-r--r-- | src/mainboard/tyan/s4882/irq_tables.c | 2 | ||||
| -rw-r--r-- | src/mainboard/tyan/s4882/mptable.c | 117 | ||||
| -rw-r--r-- | src/mainboard/tyan/s4882/resourcemap.c | 2 |
7 files changed, 201 insertions, 207 deletions
diff --git a/src/mainboard/tyan/s4882/Options.lb b/src/mainboard/tyan/s4882/Options.lb index 5d592596ba..e1a431bde3 100644 --- a/src/mainboard/tyan/s4882/Options.lb +++ b/src/mainboard/tyan/s4882/Options.lb @@ -9,6 +9,9 @@ uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS +uses CONFIG_MAX_PHYSICAL_CPUS +uses CONFIG_LOGICAL_CPUS +uses SERIAL_CPU_INIT uses CONFIG_IOAPIC uses CONFIG_SMP uses FALLBACK_SIZE @@ -50,6 +53,10 @@ uses CC uses HOSTCC uses OBJCOPY uses CONFIG_CHIP_NAME +uses CONFIG_CONSOLE_BTEXT +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN +uses K8_E0_MEM_HOLE_SIZEK ### ### Build options @@ -111,7 +118,21 @@ default LB_CKS_LOC=123 ## Only worry about 2 micro processors ## default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 +default CONFIG_MAX_CPUS=8 +default CONFIG_MAX_PHYSICAL_CPUS=4 +default CONFIG_LOGICAL_CPUS=1 + +#default SERIAL_CPU_INIT=0 + +#1G memory hole +default K8_E0_MEM_HOLE_SIZEK=0x100000 + +#BTEXT Console +#default CONFIG_CONSOLE_BTEXT=1 + +#VGA Console +default CONFIG_CONSOLE_VGA=1 +default CONFIG_PCI_ROM_RUN=1 ## ## Build code to setup a generic IOAPIC diff --git a/src/mainboard/tyan/s4882/auto.c b/src/mainboard/tyan/s4882/auto.c index e7d46d2187..21d459b6e4 100644 --- a/src/mainboard/tyan/s4882/auto.c +++ b/src/mainboard/tyan/s4882/auto.c @@ -6,13 +6,11 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> -#include <arch/cpu.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" -#include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" @@ -20,6 +18,7 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" +#include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/cpu_rev.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" @@ -69,100 +68,47 @@ static void memreset(int controllers, const struct mem_controller *ctrl) } } -static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes) -{ - /* Routing Table Node i - * - * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c - * i: 0, 1, 2, 3, 4, 5, 6, 7 - * - * [ 0: 3] Request Route - * [0] Route to this node - * [1] Route to Link 0 - * [2] Route to Link 1 - * [3] Route to Link 2 - * [11: 8] Response Route - * [0] Route to this node - * [1] Route to Link 0 - * [2] Route to Link 1 - * [3] Route to Link 2 - * [19:16] Broadcast route - * [0] Route to this node - * [1] Route to Link 0 - * [2] Route to Link 1 - * [3] Route to Link 2 - */ - uint32_t ret=0x00010101; /* default row entry */ - -/* - (L2) (L1) - CPU3-------------CPU1 - (L0)| |(L0) - | | - | | - | | - | | - (L0)| |(L0) - CPU2-------------CPU0---------8131----------8111 - (L1) (L2) (L1) -*/ - - /* Link0 of CPU0 to Link0 of CPU1 */ - /* Link2 of CPU0 to Link1 of CPU2 */ - /* Link1 of CPU1 to Link2 of CPU3 */ - /* Link0 of CPU2 to Link0 of CPU3 */ - - static const unsigned int rows_4p[4][4] = { - { 0x000b0101, 0x00010202, 0x00030808, 0x00010208 }, - { 0x00010202, 0x00070101, 0x00010204, 0x00030404 }, - { 0x00030404, 0x00010204, 0x00070101, 0x00010202 }, - { 0x00010208, 0x00030808, 0x00010202, 0x000b0101 } - }; - - if (!(node>=maxnodes || row>=maxnodes)) { - ret=rows_4p[node][row]; - } - - return ret; -} - static inline void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_HUB 0x18 + int ret,i; unsigned device=(ctrl->channel0[0])>>8; - smbus_write_byte(SMBUS_HUB , 0x01, device); - smbus_write_byte(SMBUS_HUB , 0x03, 0); -} -#if 0 -static inline void change_i2c_mux(unsigned device) -{ -#define SMBUS_HUB 0x18 - smbus_write_byte(SMBUS_HUB , 0x01, device); - smbus_write_byte(SMBUS_HUB , 0x03, 0); + i=2; + do { + ret = smbus_write_byte(SMBUS_HUB, 0x01, device); + } while ((ret!=0) && (i-->0)); + + smbus_write_byte(SMBUS_HUB, 0x03, 0); } -#endif static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } -//#include "northbridge/amd/amdk8/setup_resource_map.c" +#include "northbridge/amd/amdk8/setup_resource_map.c" +#define K8_4RANK_DIMM_SUPPORT 1 #include "northbridge/amd/amdk8/raminit.c" - -#if 1 +#if 0 #define ENABLE_APIC_EXT_ID 1 #define APIC_ID_OFFSET 0x10 -#else + #define LIFT_BSP_APIC_ID 0 +#else #define ENABLE_APIC_EXT_ID 0 #endif - #include "northbridge/amd/amdk8/coherent_ht.c" #include "sdram/generic_sdram.c" /* tyan does not want the default */ #include "resourcemap.c" +#if CONFIG_LOGICAL_CPUS==1 +#define SET_NB_CFG_54 1 +#include "cpu/amd/dualcore/dualcore.c" +#else +#include "cpu/amd/model_fxx/node_id.c" +#endif + #define FIRST_CPU 1 #define SECOND_CPU 1 @@ -171,10 +117,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU + THIRD_CPU + FOURTH_CPU) -#define RC0 ((1<<1)<<8) -#define RC1 ((1<<2)<<8) -#define RC2 ((1<<3)<<8) -#define RC3 ((1<<4)<<8) +#define RC0 ((1<<2)<<8) +#define RC1 ((1<<1)<<8) +#define RC2 ((1<<4)<<8) +#define RC3 ((1<<3)<<8) #define DIMM0 0x50 #define DIMM1 0x51 @@ -235,28 +181,69 @@ static void main(unsigned long bist) }; int i; int needs_reset; - unsigned nodeid; +#if CONFIG_LOGICAL_CPUS==1 + struct node_core_id id; +#else + unsigned nodeid; +#endif + if (bist == 0) { /* Skip this if there was a built in self test failure */ amd_early_mtrr_init(); + +#if CONFIG_LOGICAL_CPUS==1 + set_apicid_cpuid_lo(); + + id = get_node_core_id_x(); + #if ENABLE_APIC_EXT_ID == 1 + if(id.coreid == 0) { + enable_apic_ext_id(id.nodeid); + } + #endif +#else + nodeid = get_node_id(); + #if ENABLE_APIC_EXT_ID == 1 + enable_apic_ext_id(nodeid); + #endif +#endif + enable_lapic(); init_timer(); - nodeid = lapicid() & 0xf; + +#if CONFIG_LOGICAL_CPUS==1 #if ENABLE_APIC_EXT_ID == 1 - enable_apic_ext_id(nodeid); - if(nodeid != 0) { - lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); // CPU apicid is from 0x10 - } + #if LIFT_BSP_APIC_ID == 0 + if( id.nodeid != 0 ) + #endif + lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); + #endif + if(id.coreid == 0) { + if (cpu_init_detected(id.nodeid)) { + asm volatile ("jmp __cpu_reset"); + } + distinguish_cpu_resets(id.nodeid); + } +#else + #if ENABLE_APIC_EXT_ID == 1 + #if LIFT_BSP_APIC_ID == 0 + if(nodeid != 0) + #endif + lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); // CPU apicid is from 0x10 #endif if (cpu_init_detected(nodeid)) { asm volatile ("jmp __cpu_reset"); } distinguish_cpu_resets(nodeid); - - if (!boot_cpu()) { - stop_this_cpu(); - } - } +#endif + + if (!boot_cpu() +#if CONFIG_LOGICAL_CPUS==1 + || (id.coreid != 0) +#endif + ) { + stop_this_cpu(); + } + } w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); @@ -264,69 +251,25 @@ static void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - + setup_s4882_resource_map(); + needs_reset = setup_coherent_ht_domain(); -#if 0 - needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xa0); -#else + +#if CONFIG_LOGICAL_CPUS==1 + start_other_cores(); +#endif + // automatically set that for you, but you might meet tight space needs_reset |= ht_setup_chains_x(); -#endif if (needs_reset) { print_info("ht reset -\r\n"); soft_reset(); } -#if 0 - dump_pci_devices(); -#endif enable_smbus(); -#if 0 -// activate_spd_rom(&cpu[0]); -// dump_spd_registers(&cpu[0]); - -// for(i=0;i<4;i++) { -// activate_spd_rom(&cpu[i]); -// dump_smbus_registers(); -// } - for(i=1;i<256;i=i*2) { - change_i2c_mux(i); - dump_smbus_registers(); - } - -#endif memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); - -#if 0 - dump_pci_devices(); -#endif -#if 0 - dump_pci_device(PCI_DEV(0, 0x18, 1)); -#endif - - /* Check all of memory */ -#if 0 - msr_t msr; - msr = rdmsr(TOP_MEM2); - print_debug("TOP_MEM2: "); - print_debug_hex32(msr.hi); - print_debug_hex32(msr.lo); - print_debug("\r\n"); -#endif -/* -#if 0 - ram_check(0x00000000, msr.lo+(msr.hi<<32)); -#else -#if TOTAL_CPUS < 2 - // Check 16MB of memory @ 0 - ram_check(0x00000000, 0x01000000); -#else - // Check 16MB of memory @ 2GB - ram_check(0x80000000, 0x81000000); -#endif -#endif -*/ + } diff --git a/src/mainboard/tyan/s4882/cmos.layout b/src/mainboard/tyan/s4882/cmos.layout index ea027282c4..c1f3d75316 100644 --- a/src/mainboard/tyan/s4882/cmos.layout +++ b/src/mainboard/tyan/s4882/cmos.layout @@ -32,6 +32,7 @@ entries 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock +399 1 e 2 dual_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first diff --git a/src/mainboard/tyan/s4882/failover.c b/src/mainboard/tyan/s4882/failover.c index 2c8fb0041b..9d793f447f 100644 --- a/src/mainboard/tyan/s4882/failover.c +++ b/src/mainboard/tyan/s4882/failover.c @@ -11,18 +11,33 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" +#if CONFIG_LOGICAL_CPUS==1 +#include "cpu/amd/dualcore/dualcore_id.c" +#else +#include "cpu/amd/model_fxx/node_id.c" +#endif + + static unsigned long main(unsigned long bist) -{ - - unsigned nodeid; - - /* Make cerain my local apic is useable */ - enable_lapic(); - - nodeid = lapicid() & 0xf; - - /* Is this a cpu only reset? */ - if (cpu_init_detected(nodeid)) { +{ +#if CONFIG_LOGICAL_CPUS==1 + struct node_core_id id; +#else + unsigned nodeid; +#endif + /* Make cerain my local apic is useable */ +// enable_lapic(); + +#if CONFIG_LOGICAL_CPUS==1 + id = get_node_core_id_x(); + /* Is this a cpu only reset? */ + if (cpu_init_detected(id.nodeid)) { +#else +// nodeid = lapicid() & 0xf; + nodeid = get_node_id(); + /* Is this a cpu only reset? */ + if (cpu_init_detected(nodeid)) { +#endif if (last_boot_normal()) { goto normal_image; } else { @@ -37,7 +52,6 @@ static unsigned long main(unsigned long bist) goto fallback_image; } } - /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ diff --git a/src/mainboard/tyan/s4882/irq_tables.c b/src/mainboard/tyan/s4882/irq_tables.c index dd293ca966..6bd4a2123a 100644 --- a/src/mainboard/tyan/s4882/irq_tables.c +++ b/src/mainboard/tyan/s4882/irq_tables.c @@ -18,7 +18,7 @@ const struct irq_routing_table intel_irq_routing_table = { 0x7400, /* Device */ 0, /* Crap (miniport) */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x9a, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0x5b, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { {0,0xc0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, {1,(3<<3)|0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, diff --git a/src/mainboard/tyan/s4882/mptable.c b/src/mainboard/tyan/s4882/mptable.c index 98dd0cbf64..c16603a926 100644 --- a/src/mainboard/tyan/s4882/mptable.c +++ b/src/mainboard/tyan/s4882/mptable.c @@ -3,12 +3,15 @@ #include <device/pci.h> #include <string.h> #include <stdint.h> +#if CONFIG_LOGICAL_CPUS==1 +#include <cpu/amd/dualcore.h> +#endif void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "TYAN "; - static const char productid[12] = "S48822 "; + static const char productid[12] = "S4882 "; struct mp_config_table *mc; unsigned char bus_num; @@ -16,6 +19,10 @@ void *smp_write_config_table(void *v) unsigned char bus_8131_1; unsigned char bus_8131_2; unsigned char bus_8111_1; + unsigned apicid_base; + unsigned apicid_8111; + unsigned apicid_8131_1; + unsigned apicid_8131_2; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); @@ -86,7 +93,15 @@ void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ - smp_write_ioapic(mc, 4, 0x11, 0xfec00000); +#if CONFIG_LOGICAL_CPUS==1 + apicid_base = get_apicid_base(3); +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#endif + apicid_8111 = apicid_base+0; + apicid_8131_1 = apicid_base+1; + apicid_8131_2 = apicid_base+2; + smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000); { device_t dev; struct resource *res; @@ -94,91 +109,91 @@ void *smp_write_config_table(void *v) if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { - smp_write_ioapic(mc, 0x05, 0x11, res->base); + smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base); } } dev = dev_find_slot(1, PCI_DEVFN(0x2,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { - smp_write_ioapic(mc, 0x06, 0x11, res->base); + smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base); } } } /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# -*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x4, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, 0x4, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x4, 0x2); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, 0x4, 0x3); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, 0x4, 0x4); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x5, 0x4, 0x5); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, 0x4, 0x6); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, 0x4, 0x7); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, 0x4, 0x8); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x9, 0x4, 0x9); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xa, 0x4, 0xa); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xb, 0x4, 0xb); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, 0x4, 0xc); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, 0x4, 0xd); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, 0x4, 0xe); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, 0x4, 0xf); +*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_8111, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_8111, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_8111, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x5, apicid_8111, 0x5); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid_8111, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, apicid_8111, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, apicid_8111, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x9, apicid_8111, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xa, apicid_8111, 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xb, apicid_8111, 0xb); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_8111, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_8111, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_8111, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 1, (4<<2)|0, 0x4, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 1, (4<<2)|0, apicid_8111, 0x13); //On Board AMD USB - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, 0x4, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13); //On Board Via USB 1.1 and 2 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|0, 0x4, 0x11); //1.1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|1, 0x4, 0x10); //1.1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|2, 0x4, 0x12); //2 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|0, apicid_8111, 0x11); //1.1 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|1, apicid_8111, 0x10); //1.1 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|2, apicid_8111, 0x12); //2 //Slot 5 PCI 32 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|0, 0x4, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|1, 0x4, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|2, 0x4, 0x12); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|3, 0x4, 0x13); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|0, apicid_8111, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|1, apicid_8111, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|2, apicid_8111, 0x12); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|3, apicid_8111, 0x13); // //On Board SI Serial ATA - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, 0x4, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, apicid_8111, 0x13); //On Board ATI Display Adapter - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, 0x4, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, apicid_8111, 0x12); //Slot 4 PCIX 100/66 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|0, 0x5, 0x3); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|1, 0x5, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, 0x5, 0x1);// - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, 0x5, 0x2);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|0, apicid_8131_1, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|1, apicid_8131_1, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, apicid_8131_1, 0x1);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, apicid_8131_1, 0x2);// //Slot 3 PCIX 100/66 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, 0x5, 0x2); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|1, 0x5, 0x3);// - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, 0x5, 0x0);// - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|3, 0x5, 0x1);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, apicid_8131_1, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|1, apicid_8131_1, 0x3);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, apicid_8131_1, 0x0);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|3, apicid_8131_1, 0x1);// //On Board LSI scsi and NIC - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|0, 0x5, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|1, 0x5, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, 0x5, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|1, 0x5, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|0, apicid_8131_1, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|1, apicid_8131_1, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, apicid_8131_1, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|1, apicid_8131_1, 0x1); //Slot 2 PCI-X 133/100/66 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, 0x6, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, 0x6, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, 0x6, 0x2); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, 0x6, 0x3); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, apicid_8131_2, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, apicid_8131_2, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, apicid_8131_2, 0x2); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, apicid_8131_2, 0x3); // //Slot 1 PCI-X 133/100/66 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|0, 0x6, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|1, 0x6, 0x2); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|2, 0x6, 0x3);// - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|3, 0x6, 0x0);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|0, apicid_8131_2, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|1, apicid_8131_2, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|2, apicid_8131_2, 0x3);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|3, apicid_8131_2, 0x0);// /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); diff --git a/src/mainboard/tyan/s4882/resourcemap.c b/src/mainboard/tyan/s4882/resourcemap.c index 423ac3cf00..8d9307c68f 100644 --- a/src/mainboard/tyan/s4882/resourcemap.c +++ b/src/mainboard/tyan/s4882/resourcemap.c @@ -252,7 +252,7 @@ static void setup_s4882_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ - PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000103, +// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000103, PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, |