summaryrefslogtreecommitdiff
path: root/src/mainboard/tyan/s2912_fam10
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard/tyan/s2912_fam10')
-rw-r--r--src/mainboard/tyan/s2912_fam10/romstage.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index 76f339e70a..e8bca07ce5 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -182,7 +182,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 wants_reset;
msr_t msr;
- if (!((cpu_init_detectedx) || (!boot_cpu()))) {
+ if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */