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-rw-r--r--src/mainboard/tyan/s2891/Config.lb4
-rw-r--r--src/mainboard/tyan/s2891/Options.lb16
-rw-r--r--src/mainboard/tyan/s2891/auto.c2
-rw-r--r--src/mainboard/tyan/s2891/cache_as_ram_auto.c48
-rw-r--r--src/mainboard/tyan/s2891/cmos.layout8
-rw-r--r--src/mainboard/tyan/s2891/get_bus_conf.c53
-rw-r--r--src/mainboard/tyan/s2891/irq_tables.c18
-rw-r--r--src/mainboard/tyan/s2891/mptable.c8
-rw-r--r--src/mainboard/tyan/s2891/resourcemap.c4
9 files changed, 101 insertions, 60 deletions
diff --git a/src/mainboard/tyan/s2891/Config.lb b/src/mainboard/tyan/s2891/Config.lb
index 67c7b3c8a9..f23e75b7e2 100644
--- a/src/mainboard/tyan/s2891/Config.lb
+++ b/src/mainboard/tyan/s2891/Config.lb
@@ -314,8 +314,8 @@ chip northbridge/amd/amdk8/root_complex
# chip drivers/ati/ragexl
chip drivers/pci/onboard
device pci 7.0 on end
- # register "rom_address" = "0xfff80000" #for 512K
- register "rom_address" = "0xfff00000" #for 1M
+ register "rom_address" = "0xfff80000" #for 512K
+ # register "rom_address" = "0xfff00000" #for 1M
end
end
device pci a.0 off end # NIC
diff --git a/src/mainboard/tyan/s2891/Options.lb b/src/mainboard/tyan/s2891/Options.lb
index 366b745151..933390b025 100644
--- a/src/mainboard/tyan/s2891/Options.lb
+++ b/src/mainboard/tyan/s2891/Options.lb
@@ -54,7 +54,6 @@ uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
-uses K8_HT_FREQ_1G_SUPPORT
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
@@ -74,12 +73,13 @@ uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
uses CONFIG_LB_MEM_TOPK
+
## ROM_SIZE is the size of boot ROM that this board will use.
#512K bytes
-#default ROM_SIZE=524288
+default ROM_SIZE=524288
#1M bytes
-default ROM_SIZE=1048576
+#default ROM_SIZE=1048576
##
@@ -139,9 +139,6 @@ default CONFIG_LOGICAL_CPUS=1
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000
-#Opteron K8 1G HT Support
-default K8_HT_FREQ_1G_SUPPORT=1
-
##HT Unit ID offset, default is 1, the typical one
default HT_CHAIN_UNITID_BASE=0x0
@@ -152,8 +149,7 @@ default HT_CHAIN_UNITID_BASE=0x0
default SB_HT_CHAIN_ON_BUS0=2
##only offset for SB chain?, default is yes(1)
-default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
+#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
#BTEXT Console
#default CONFIG_CONSOLE_BTEXT=1
@@ -229,8 +225,8 @@ default CONFIG_ROM_STREAM = 1
##
## The default compiler
##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CROSS_COMPILE)gcc-3.3.6 -m32"
+default HOSTCC="gcc-3.3.6"
##
## Disable the gdb stub by default
diff --git a/src/mainboard/tyan/s2891/auto.c b/src/mainboard/tyan/s2891/auto.c
index e772a1ab62..be81f89e11 100644
--- a/src/mainboard/tyan/s2891/auto.c
+++ b/src/mainboard/tyan/s2891/auto.c
@@ -12,7 +12,7 @@
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
-#include <cpu/amd/model_fxx_rev.h>
+#include "northbridge/amd/amdk8/cpu_rev.c"
#define K8_HT_FREQ_1G_SUPPORT 0
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
diff --git a/src/mainboard/tyan/s2891/cache_as_ram_auto.c b/src/mainboard/tyan/s2891/cache_as_ram_auto.c
index b83839a19c..aceffc33fa 100644
--- a/src/mainboard/tyan/s2891/cache_as_ram_auto.c
+++ b/src/mainboard/tyan/s2891/cache_as_ram_auto.c
@@ -2,7 +2,7 @@
#define __ROMCC__
//used by raminit
-#define K8_4RANK_DIMM_SUPPORT 1
+#define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
@@ -21,7 +21,19 @@
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
+#if 0
+static void post_code(uint8_t value) {
+#if 1
+ int i;
+ for(i=0;i<0x80000;i++) {
+ outb(value, 0x80);
+ }
+#endif
+}
+#endif
+
#include <cpu/amd/model_fxx_rev.h>
+
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
@@ -42,6 +54,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
static void memreset_setup(void)
{
}
@@ -92,15 +105,21 @@ static void sio_setup(void)
uint32_t dword;
uint8_t byte;
- byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
+ /* subject decoding*/
+ byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
byte |= 0x20;
pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
+ /* LPC Positive Decode 0 */
dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
+ /* Serial 0, Serial 1 */
dword |= (1<<0) | (1<<1);
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
#if 1
+ /* s2891 has onboard LPC port 80 */
+ /*Hope I can enable port 80 here
+ It will decode port 80 to LPC, If you are using PCI post code you can not do this */
dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4);
dword |= (1<<16);
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
@@ -133,6 +152,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
ck804_enable_rom();
/* Is this a deliberate reset by the bios */
+// post_code(0x22);
if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image;
}
@@ -144,12 +164,14 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
goto fallback_image;
}
normal_image:
+// post_code(0x23);
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) , "b" (cpu_init_detectedx)/* inputs */
);
fallback_image:
+// post_code(0x25);
;
}
#endif
@@ -187,6 +209,8 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
bsp_apicid = init_cpus(cpu_init_detectedx);
}
+// post_code(0x32);
+
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
@@ -195,6 +219,10 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
report_bist_failure(bist);
setup_s2891_resource_map();
+#if 0
+ dump_pci_device(PCI_DEV(0, 0x18, 0));
+ dump_pci_device(PCI_DEV(0, 0x19, 0));
+#endif
needs_reset = setup_coherent_ht_domain();
@@ -211,7 +239,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (needs_reset) {
print_info("ht reset -\r\n");
- soft_reset();
+// soft_reset();
}
allow_all_aps_stop(bsp_apicid);
@@ -221,9 +249,23 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
fill_mem_ctrl(nodes, ctrl, spd_addr);
enable_smbus();
+#if 0
+ dump_spd_registers(&cpu[0]);
+#endif
+#if 0
+ dump_smbus_registers();
+#endif
memreset_setup();
sdram_initialize(nodes, ctrl);
+#if 0
+ print_pci_devices();
+#endif
+
+#if 0
+ dump_pci_devices();
+#endif
+
post_cache_as_ram();
}
diff --git a/src/mainboard/tyan/s2891/cmos.layout b/src/mainboard/tyan/s2891/cmos.layout
index 5eb88b9a5a..c1f3d75316 100644
--- a/src/mainboard/tyan/s2891/cmos.layout
+++ b/src/mainboard/tyan/s2891/cmos.layout
@@ -78,10 +78,10 @@ enumerations
7 9 Fallback_HDD
7 10 Fallback_Floppy
#7 3 ROM
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
+8 0 200Mhz
+8 1 166Mhz
+8 2 133Mhz
+8 3 100Mhz
9 0 off
9 1 87.5%
9 2 75.0%
diff --git a/src/mainboard/tyan/s2891/get_bus_conf.c b/src/mainboard/tyan/s2891/get_bus_conf.c
index aeb1ef4473..8093f96332 100644
--- a/src/mainboard/tyan/s2891/get_bus_conf.c
+++ b/src/mainboard/tyan/s2891/get_bus_conf.c
@@ -7,6 +7,7 @@
#include <cpu/amd/dualcore.h>
#endif
+#include <cpu/amd/amdk8_sysconf.h>
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
//busnum is default
@@ -24,9 +25,9 @@
unsigned apicid_ck804;
unsigned apicid_8131_1;
unsigned apicid_8131_2;
+
-unsigned sblk;
-unsigned pci1234[] =
+unsigned pci1234x[] =
{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
0x0000000,
@@ -38,9 +39,7 @@ unsigned pci1234[] =
// 0x0000ff0,
// 0x0000ff0
};
-unsigned hc_possible_num;
-unsigned sbdn;
-unsigned hcdn[] =
+unsigned hcdnx[] =
{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
0x20202020,
0x20202020,
@@ -65,27 +64,27 @@ void get_bus_conf(void)
unsigned apicid_base;
device_t dev;
+ unsigned sbdn;
+ int i;
- if(get_bus_conf_done==1) return; //do it only once
+ if(get_bus_conf_done==1) return; //do it only once
- get_bus_conf_done = 1;
+ get_bus_conf_done = 1;
- hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]);
-
- get_sblk_pci1234();
-
- sbdn = (hcdn[0] & 0xff); // first byte of first chain
+ sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+ for(i=0;i<sysconf.hc_possible_num; i++) {
+ sysconf.pci1234[i] = pci1234x[i];
+ sysconf.hcdn[i] = hcdnx[i];
+ }
- sbdn3 = (hcdn[1] & 0xff); // first byte of second chain
+ get_sblk_pci1234();
+
+ sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
+ sbdn = sysconf.sbdn;
-// bus_ck804_0 = node_link_to_bus(0, sblk);
- bus_ck804_0 = (pci1234[0] >> 16) & 0xff;
-
- if(pci1234[2] & 1) {
- bus_coproc_0 = (pci1234[2] >> 16) & 0xff;
- coprocdn = (hcdn[2] & 0xff);
- }
+ sbdn3 = (sysconf.hcdn[1] & 0xff); // first byte of second chain
+ bus_ck804_0 = (sysconf.pci1234[0] >> 16) & 0xff;
/* CK804 */
@@ -153,16 +152,14 @@ void get_bus_conf(void)
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x0e,0));
if (dev) {
bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_8131_0 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_8131_0++;
- bus_isa = bus_8131_0; // incase only one installed
+ bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_isa++;
}
else {
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e);
-
}
- bus_8131_0 = (pci1234[1] >> 16) & 0xff;
+ bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff;
/* 8131-1 */
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0));
@@ -191,7 +188,11 @@ void get_bus_conf(void)
bus_isa = bus_8131_1+2;
}
-
+ if(sysconf.pci1234[2] & 1) {
+ bus_coproc_0 = (sysconf.pci1234[2] >> 16) & 0xff;
+ coprocdn = (sysconf.hcdn[2] & 0xff);
+ }
+
/*I/O APICs: APIC ID Version State Address*/
#if CONFIG_LOGICAL_CPUS==1
diff --git a/src/mainboard/tyan/s2891/irq_tables.c b/src/mainboard/tyan/s2891/irq_tables.c
index b051989532..f694c85924 100644
--- a/src/mainboard/tyan/s2891/irq_tables.c
+++ b/src/mainboard/tyan/s2891/irq_tables.c
@@ -10,6 +10,8 @@
#include <stdint.h>
#include <arch/pirq_routing.h>
+#include <cpu/amd/amdk8_sysconf.h>
+
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
uint8_t slot, uint8_t rfu)
@@ -40,10 +42,7 @@ extern unsigned char bus_8131_1;//8
extern unsigned char bus_8131_2;//9
extern unsigned char bus_coproc_0;
-extern unsigned sbdn;
-extern unsigned hcdn[];
extern unsigned sbdn3;
-extern unsigned pci1234[];
extern unsigned coprocdn;
extern void get_bus_conf(void);
@@ -58,8 +57,10 @@ unsigned long write_pirq_routing_table(unsigned long addr)
uint8_t sum=0;
int i;
+ unsigned sbdn;
- get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
+ get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
+ sbdn = sysconf.sbdn;
/* Align the table to be 16 byte aligned. */
addr += 15;
@@ -94,12 +95,11 @@ unsigned long write_pirq_routing_table(unsigned long addr)
//pcix bridge
write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++;
-
//co processor
- if(pci1234[2] & 1) {
- write_pirq_info(pirq_info, bus_coproc_0, (coprocdn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++; slot_num++;
- }
+ if(sysconf.pci1234[2] & 1) {
+ write_pirq_info(pirq_info, bus_coproc_0, (coprocdn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+ pirq_info++; slot_num++;
+ }
#if 0
//smbus
diff --git a/src/mainboard/tyan/s2891/mptable.c b/src/mainboard/tyan/s2891/mptable.c
index 8e4be7d061..b383aae2b7 100644
--- a/src/mainboard/tyan/s2891/mptable.c
+++ b/src/mainboard/tyan/s2891/mptable.c
@@ -4,6 +4,8 @@
#include <string.h>
#include <stdint.h>
+#include <cpu/amd/amdk8_sysconf.h>
+
extern unsigned char bus_isa;
extern unsigned char bus_ck804_0; //1
extern unsigned char bus_ck804_1; //2
@@ -18,8 +20,6 @@ extern unsigned apicid_ck804;
extern unsigned apicid_8131_1;
extern unsigned apicid_8131_2;
-extern unsigned sbdn;
-extern unsigned hcdn[];
extern unsigned sbdn3;
extern void get_bus_conf(void);
@@ -30,6 +30,7 @@ void *smp_write_config_table(void *v)
static const char oem[8] = "TYAN ";
static const char productid[12] = "S2891 ";
struct mp_config_table *mc;
+ unsigned sbdn;
unsigned char bus_num;
int i;
@@ -54,6 +55,7 @@ void *smp_write_config_table(void *v)
smp_write_processors(mc);
get_bus_conf();
+ sbdn = sysconf.sbdn;
/*Bus: Bus ID Type*/
/* define bus and isa numbers */
@@ -75,6 +77,7 @@ void *smp_write_config_table(void *v)
smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
}
+ /* Initialize interrupt mapping*/
dword = 0x0000d218;
pci_write_config32(dev, 0x7c, dword);
@@ -83,7 +86,6 @@ void *smp_write_config_table(void *v)
pci_write_config32(dev, 0x80, dword);
dword = 0x0000007d;
-
pci_write_config32(dev, 0x84, dword);
}
diff --git a/src/mainboard/tyan/s2891/resourcemap.c b/src/mainboard/tyan/s2891/resourcemap.c
index 625e19f11c..ad559b2ded 100644
--- a/src/mainboard/tyan/s2891/resourcemap.c
+++ b/src/mainboard/tyan/s2891/resourcemap.c
@@ -258,8 +258,8 @@ static void setup_s2891_resource_map(void)
* This field defines the highest bus number in configuration region i
*/
#if 1
-// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003,
-// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203,
+// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */
+// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
#endif
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-19 08:04:42 +0000