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Diffstat (limited to 'src/mainboard/tyan/s2885/auto.c')
-rw-r--r--src/mainboard/tyan/s2885/auto.c194
1 files changed, 84 insertions, 110 deletions
diff --git a/src/mainboard/tyan/s2885/auto.c b/src/mainboard/tyan/s2885/auto.c
index aacb4b007b..cff103b9cc 100644
--- a/src/mainboard/tyan/s2885/auto.c
+++ b/src/mainboard/tyan/s2885/auto.c
@@ -6,13 +6,11 @@
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
@@ -20,6 +18,7 @@
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
+#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
@@ -43,17 +42,6 @@ static void soft_reset(void)
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
}
-#define AMD8111_RESET PCI_DEV( \
- HARD_RESET_BUS, \
- HARD_RESET_DEVICE, \
- HARD_RESET_FUNCTION)
-
-static void soft2_reset(void)
-{
- set_bios_reset();
- pci_write_config8(AMD8111_RESET, 0x47, 1);
-}
-
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
@@ -74,61 +62,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
}
}
-static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
-{
- /* Routing Table Node i
- *
- * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
- * i: 0, 1, 2, 3, 4, 5, 6, 7
- *
- * [ 0: 3] Request Route
- * [0] Route to this node
- * [1] Route to Link 0
- * [2] Route to Link 1
- * [3] Route to Link 2
- * [11: 8] Response Route
- * [0] Route to this node
- * [1] Route to Link 0
- * [2] Route to Link 1
- * [3] Route to Link 2
- * [19:16] Broadcast route
- * [0] Route to this node
- * [1] Route to Link 0
- * [2] Route to Link 1
- * [3] Route to Link 2
- */
-
- uint32_t ret=0x00010101; /* default row entry */
-/*
- (L1) (L1) (L2)
- CPU1-------------CPU0--------8131------8111
- |(L0)
- |
- |
- |
- |
- |
- 8151
-*/
- /* Link1 of CPU0 to Link1 of CPU1 */
- static const unsigned int rows_2p[2][2] = {
- { 0x00050101, 0x00010404 },
- { 0x00010404, 0x00050101 }
- };
-
- if(maxnodes>2) {
- print_debug("this mainboard is only designed for 2 cpus\r\n");
- maxnodes=2;
- }
-
-
- if (!(node>=maxnodes || row>=maxnodes)) {
- ret=rows_2p[node][row];
- }
-
- return ret;
-}
-
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
@@ -140,16 +73,33 @@ static inline int spd_read_byte(unsigned device, unsigned address)
}
//#include "northbridge/amd/amdk8/setup_resource_map.c"
+#define K8_4RANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c"
+
+#if 0
+ #define ENABLE_APIC_EXT_ID 1
+ #define APIC_ID_OFFSET 0x10
+ #define LIFT_BSP_APIC_ID 0
+#else
+ #define ENABLE_APIC_EXT_ID 0
+#endif
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
/* tyan does not want the default */
#include "resourcemap.c"
+#if CONFIG_LOGICAL_CPUS==1
+#define SET_NB_CFG_54 1
+#include "cpu/amd/dualcore/dualcore.c"
+#else
+#include "cpu/amd/model_fxx/node_id.c"
+#endif
+
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
+
static void main(unsigned long bist)
{
static const struct mem_controller cpu[] = {
@@ -178,22 +128,71 @@ static void main(unsigned long bist)
};
int needs_reset;
+#if CONFIG_LOGICAL_CPUS==1
+ struct node_core_id id;
+#else
unsigned nodeid;
+#endif
if (bist == 0) {
/* Skip this if there was a built in self test failure */
amd_early_mtrr_init();
+
+#if CONFIG_LOGICAL_CPUS==1
+ set_apicid_cpuid_lo();
+
+ id = get_node_core_id_x(); // that is initid
+ #if ENABLE_APIC_EXT_ID == 1
+ if(id.coreid == 0) {
+ enable_apic_ext_id(id.nodeid);
+ }
+ #endif
+#else
+ nodeid = get_node_id();
+ #if ENABLE_APIC_EXT_ID == 1
+ enable_apic_ext_id(nodeid);
+ #endif
+#endif
+
enable_lapic();
init_timer();
- nodeid = lapicid() & 0xf;
-
- if (cpu_init_detected(nodeid)) {
- asm volatile ("jmp __cpu_reset");
- }
- distinguish_cpu_resets(nodeid);
- if (!boot_cpu()) {
- stop_this_cpu();
+#if CONFIG_LOGICAL_CPUS==1
+ #if ENABLE_APIC_EXT_ID == 1
+ #if LIFT_BSP_APIC_ID == 0
+ if( id.nodeid != 0 ) //all except cores in node0
+ #endif
+ lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) );
+ #endif
+
+ if(id.coreid == 0) {
+ if (cpu_init_detected(id.nodeid)) {
+ asm volatile ("jmp __cpu_reset");
+ }
+ distinguish_cpu_resets(id.nodeid);
+ }
+
+#else
+ #if ENABLE_APIC_EXT_ID == 1
+ #if LIFT_BSP_APIC_ID == 0
+ if(nodeid != 0)
+ #endif
+ lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); // CPU apicid is from 0x10
+
+ #endif
+
+ if (cpu_init_detected(nodeid)) {
+ asm volatile ("jmp __cpu_reset");
+ }
+ distinguish_cpu_resets(nodeid);
+#endif
+
+ if (!boot_cpu()
+#if CONFIG_LOGICAL_CPUS==1
+ || (id.coreid != 0)
+#endif
+ ) {
+ stop_this_cpu();
}
}
@@ -202,51 +201,26 @@ static void main(unsigned long bist)
console_init();
/* Halt if there was a built in self test failure */
-// report_bist_failure(bist);
-
+ report_bist_failure(bist);
+
setup_s2885_resource_map();
needs_reset = setup_coherent_ht_domain();
-#if 0
- needs_reset |= ht_setup_chains(2);
-#else
- needs_reset |= ht_setup_chains_x();
+
+#if CONFIG_LOGICAL_CPUS==1
+ start_other_cores();
#endif
+
+ // automatically set that for you, but you might meet tight space
+ needs_reset |= ht_setup_chains_x();
+
if (needs_reset) {
print_info("ht reset -\r\n");
soft_reset();
}
enable_smbus();
-#if 0
- dump_spd_registers(&cpu[0]);
-#endif
memreset_setup();
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
-#if 0
- dump_pci_devices();
-#endif
-
- /* Check all of memory */
-#if 0
- msr_t msr;
- msr = rdmsr(TOP_MEM2);
- print_debug("TOP_MEM2: ");
- print_debug_hex32(msr.hi);
- print_debug_hex32(msr.lo);
- print_debug("\r\n");
-#endif
-
-#if 0
- ram_check(0x00000000, msr.lo+(msr.hi<<32));
-#endif
-
-#if 0
- // Check 16MB of memory @ 0
- ram_check(0x00000000, 0x00100000);
- // Check 16MB of memory @ 2GB
- ram_check(0x80000000, 0x80100000);
-#endif
-
}