diff options
Diffstat (limited to 'src/mainboard/tyan/s2885/auto.c')
| -rw-r--r-- | src/mainboard/tyan/s2885/auto.c | 61 |
1 files changed, 34 insertions, 27 deletions
diff --git a/src/mainboard/tyan/s2885/auto.c b/src/mainboard/tyan/s2885/auto.c index 2915886cc9..712ff731d1 100644 --- a/src/mainboard/tyan/s2885/auto.c +++ b/src/mainboard/tyan/s2885/auto.c @@ -1,4 +1,5 @@ -#define ASSEMBLY 1 +#define ASSEMBLY 1 + #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -41,21 +42,22 @@ static void soft_reset(void) static void memreset_setup(void) { - if (is_cpu_pre_c0()) { - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 - } else { - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 - } + if (is_cpu_pre_c0()) { + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 + } + else { + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 + } + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); } static void memreset(int controllers, const struct mem_controller *ctrl) { - if (is_cpu_pre_c0()) { - udelay(800); - outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 - udelay(90); - } + if (is_cpu_pre_c0()) { + udelay(800); + outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 + udelay(90); + } } static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes) @@ -82,20 +84,21 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes) * [3] Route to Link 2 */ - uint32_t ret = 0x00010101; /* default row entry */ + uint32_t ret=0x00010101; /* default row entry */ static const unsigned int rows_2p[2][2] = { { 0x00050101, 0x00010404 }, { 0x00010404, 0x00050101 } }; - if (maxnodes > 2) { + if(maxnodes>2) { print_debug("this mainboard is only designed for 2 cpus\r\n"); - maxnodes = 2; + maxnodes=2; } - if (!(node >= maxnodes || row >= maxnodes)) { - ret = rows_2p[node][row]; + + if (!(node>=maxnodes || row>=maxnodes)) { + ret=rows_2p[node][row]; } return ret; @@ -147,10 +150,10 @@ static void main(void) #endif }; +#if 1 static const struct ht_chain ht_c[] = { { .udev = PCI_DEV(0, 0x18, 0), - /* LDT2 */ .upos = 0xc0, .devreg = 0xe0, }, @@ -160,27 +163,28 @@ static void main(void) .devreg = 0xe4, }, }; - int needs_reset; +#endif + int needs_reset; enable_lapic(); init_timer(); - if (cpu_init_detected()) { asm("jmp __cpu_reset"); } - distinguish_cpu_resets(); if (!boot_cpu()) { stop_this_cpu(); } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); - setup_s2885_resource_map(); needs_reset = setup_coherent_ht_domain(); +#if 0 + needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xc0); +#else needs_reset |= ht_setup_chains(ht_c, sizeof(ht_c)/sizeof(ht_c[0])); +#endif if (needs_reset) { print_info("ht reset -\r\n"); soft_reset(); @@ -189,22 +193,20 @@ static void main(void) dump_pci_devices(); #endif - #if 0 print_pci_devices(); #endif - enable_smbus(); - #if 0 dump_spd_registers(&cpu[0]); #endif - memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); #if 0 dump_pci_devices(); +#endif +#if 0 dump_pci_device(PCI_DEV(0, 0x18, 1)); #endif @@ -216,7 +218,11 @@ static void main(void) print_debug_hex32(msr.hi); print_debug_hex32(msr.lo); print_debug("\r\n"); +#endif +/* +#if 0 ram_check(0x00000000, msr.lo+(msr.hi<<32)); +#else #if TOTAL_CPUS < 2 // Check 16MB of memory @ 0 ram_check(0x00000000, 0x00100000); @@ -225,4 +231,5 @@ static void main(void) ram_check(0x80000000, 0x80100000); #endif #endif +*/ } |