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-rw-r--r--src/mainboard/traverse/geos/Kconfig6
-rw-r--r--src/mainboard/traverse/geos/romstage.c6
2 files changed, 7 insertions, 5 deletions
diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig
index 40679fe1f1..3139d7dc1b 100644
--- a/src/mainboard/traverse/geos/Kconfig
+++ b/src/mainboard/traverse/geos/Kconfig
@@ -11,6 +11,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select UDELAY_TSC
select BOARD_ROMSIZE_KB_1024
select POWER_BUTTON_DEFAULT_DISABLE
+ select PLL_MANUAL_CONFIG
+ select CORE_GLIU_500_400
config MAINBOARD_DIR
string
@@ -24,4 +26,8 @@ config IRQ_SLOT_COUNT
int
default 6
+config PLLMSRlo
+ hex
+ default 0x00de602e
+
endif # BOARD_TRAVERSE_GEOS
diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c
index 588681bfbb..0b61d41122 100644
--- a/src/mainboard/traverse/geos/romstage.c
+++ b/src/mainboard/traverse/geos/romstage.c
@@ -39,10 +39,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
return smbus_read_byte(device, address);
}
-#define ManualConf 1 /* Do automatic strapped PLL config */
-#define PLLMSRhi 0x0000059C /* manual settings for the PLL */
-#define PLLMSRlo 0x00DE602E
-
#include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c"
@@ -75,7 +71,7 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- pll_reset(ManualConf);
+ pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);