diff options
Diffstat (limited to 'src/mainboard/totalimpact/briq/Options.lb')
| -rw-r--r-- | src/mainboard/totalimpact/briq/Options.lb | 137 |
1 files changed, 0 insertions, 137 deletions
diff --git a/src/mainboard/totalimpact/briq/Options.lb b/src/mainboard/totalimpact/briq/Options.lb deleted file mode 100644 index b33efdd4a0..0000000000 --- a/src/mainboard/totalimpact/briq/Options.lb +++ /dev/null @@ -1,137 +0,0 @@ -## -## Config file for the Total Impact briQ -## - -uses CONFIG_TTYS0_DIV -uses CONFIG_CBFS -uses CONFIG_ARCH_X86 -uses CONFIG_TTYS0_BASE -uses CONFIG_BRIQ_750FX -uses CONFIG_BRIQ_7400 -uses CONFIG_ISA_IO_BASE -uses CONFIG_ISA_MEM_BASE -uses CONFIG_PCIC0_CFGADDR -uses CONFIG_PCIC0_CFGDATA -uses CONFIG_IO_BASE -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_COMPRESS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_USE_INIT -uses CONFIG_NO_POST -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_IDE_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_IDE_BOOT_DRIVE -uses CONFIG_IDE_SWAB CONFIG_IDE_OFFSET -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_RESET -uses CONFIG_EXCEPTION_VECTORS -uses CONFIG_ROMBASE -uses CONFIG_ROMSTART -uses CONFIG_RAMBASE -uses CONFIG_RAMSTART -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_BRIQ_750FX -uses CONFIG_BRIQ_7400 -uses CONFIG_SYS_CLK_FREQ - -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY - -## -## Set memory map -## -default CONFIG_ISA_IO_BASE=0x80000000 -default CONFIG_ISA_MEM_BASE=0xc0000000 -default CONFIG_PCIC0_CFGADDR=0xff5f8000 -default CONFIG_PCIC0_CFGDATA=0xff5f8010 -default CONFIG_IO_BASE=CONFIG_ISA_IO_BASE - -## -## The briQ uses weird clocking, 4 = 115200 -## -default CONFIG_TTYS0_DIV=4 -## -## Set UART base address -## -default CONFIG_TTYS0_BASE=0x3f8 - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc" -default HOSTCC="gcc" -## use a cross compiler -#default CONFIG_CROSS_COMPILE="powerpc-eabi-" -#default CONFIG_CROSS_COMPILE="ppc_74xx-" -default CONFIG_ARCH_X86=0 - -## Use stage 1 initialization code -default CONFIG_USE_INIT=1 - -## We don't use compressed image -default CONFIG_COMPRESS=0 - -## Turn off POST codes -default CONFIG_NO_POST=1 - -## Enable serial console -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -default CONFIG_CONSOLE_SERIAL8250=1 - -## Boot linux from IDE -default CONFIG_IDE_PAYLOAD=1 -default CONFIG_IDE_BOOT_DRIVE=0 -default CONFIG_IDE_SWAB=1 -default CONFIG_IDE_OFFSET=0 - -# ROM is 1Mb -default CONFIG_ROM_SIZE=1048576 -default CONFIG_ROM_IMAGE_SIZE=128*1024 - -# Set stack and heap sizes (stage 2) -default CONFIG_STACK_SIZE=0x10000 -default CONFIG_HEAP_SIZE=0x10000 - -## -## System clock -## -default CONFIG_SYS_CLK_FREQ=33 - -# Sandpoint Demo Board -## Base of ROM -default CONFIG_ROMBASE=0xfff00000 - -## Sandpoint reset vector -default CONFIG_RESET=CONFIG_ROMBASE+0x100 - -## Exception vectors (other than reset vector) -default CONFIG_EXCEPTION_VECTORS=CONFIG_RESET+0x100 - -## Start of coreboot in the boot rom -## = CONFIG_RESET + exeception vector table size -default CONFIG_ROMSTART=CONFIG_RESET+0x3100 - -## Coreboot C code runs at this location in RAM -default CONFIG_RAMBASE=0x00100000 -default CONFIG_RAMSTART=0x00100000 - -default CONFIG_BRIQ_750FX=1 -#default CONFIG_BRIQ_7400=1 - -### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 -end |