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-rw-r--r--src/mainboard/system76/addw1/devicetree.cb42
-rw-r--r--src/mainboard/system76/bonw14/devicetree.cb44
-rw-r--r--src/mainboard/system76/cml-u/variants/darp6/overridetree.cb36
-rw-r--r--src/mainboard/system76/cml-u/variants/galp4/overridetree.cb36
-rw-r--r--src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb36
-rw-r--r--src/mainboard/system76/gaze15/devicetree.cb34
-rw-r--r--src/mainboard/system76/oryp5/devicetree.cb40
-rw-r--r--src/mainboard/system76/oryp6/devicetree.cb28
-rw-r--r--src/mainboard/system76/whl-u/devicetree.cb36
9 files changed, 183 insertions, 149 deletions
diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb
index 94f1bdda60..529767c568 100644
--- a/src/mainboard/system76/addw1/devicetree.cb
+++ b/src/mainboard/system76/addw1/devicetree.cb
@@ -66,23 +66,25 @@ chip soc/intel/cannonlake
device pci 12.6 off end # GSPI #2
device pci 13.0 off end # Integrated Sensor Hub
device pci 14.0 on # USB xHCI
- # USB2
- register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C and DisplayPort
- register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C
- register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 2
- register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 1 audio
- register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 1 back
- register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
- register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Per-Key RGB keyboard
- register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Camera
- register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
- # USB3
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C and DisplayPort
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 right
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C (without TBT)
- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C (without TBT)
- register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 1 audio
- register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 1 back
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_TYPE_C(OC_SKIP), /* USB 3.1 Gen 2 TYPE-C and DisplayPort */
+ [1] = USB2_PORT_TYPE_C(OC_SKIP), /* USB 3.1 Gen 2 TYPE-C */
+ [2] = USB2_PORT_MID(OC_SKIP), /* USB 3.1 Gen 2 */
+ [4] = USB2_PORT_MID(OC_SKIP), /* USB 3.1 Gen 1 audio */
+ [5] = USB2_PORT_MID(OC_SKIP), /* USB 3.1 Gen 1 back */
+ [6] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */
+ [7] = USB2_PORT_MID(OC_SKIP), /* Per-Key RGB keyboard */
+ [8] = USB2_PORT_MID(OC_SKIP), /* Camera */
+ [13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
+ }"
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.1 Gen 2 TYPE-C and DisplayPort */
+ [1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.1 Gen 2 right */
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.1 Gen 2 TYPE-C (without TBT) */
+ [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.1 Gen 2 TYPE-C (without TBT) */
+ [4] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.1 Gen 1 audio */
+ [5] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.1 Gen 1 back */
+ }"
end
device pci 14.2 on end # Shared SRAM
device pci 14.3 on # CNVi wifi
@@ -103,8 +105,10 @@ chip soc/intel/cannonlake
device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 on # SATA
- register "SataPortsEnable[0]" = "1" # HDD (SATA0B)
- register "SataPortsEnable[1]" = "1" # SSD1 (SATA1A)
+ register "SataPortsEnable" = "{
+ [0] = 1, /* HDD (SATA0B) */
+ [1] = 1, /* SSD1 (SATA1A) */
+ }"
end
device pci 19.2 off end # UART #2
device pci 1a.0 off end # eMMC
diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb
index 59a1c14cea..d79aa76659 100644
--- a/src/mainboard/system76/bonw14/devicetree.cb
+++ b/src/mainboard/system76/bonw14/devicetree.cb
@@ -73,23 +73,25 @@ chip soc/intel/cannonlake
device pci 12.6 off end # GSPI #2
device pci 13.0 off end # Integrated Sensor Hub
device pci 14.0 on # USB xHCI
- # USB2
- register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_2
- register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_1
- register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_4
- register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_3
- register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Per-key RGB
- register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB Type-C
- register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # XFI
- register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
- register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Light guide
- register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
- register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
- # USB3
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_2
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # ANX7440
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_4
- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_3
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_MID(OC_SKIP), /* USB 3_2 */
+ [1] = USB2_PORT_MID(OC_SKIP), /* USB 3_1 */
+ [2] = USB2_PORT_MID(OC_SKIP), /* USB 3_4 */
+ [3] = USB2_PORT_MID(OC_SKIP), /* USB 3_3 */
+ [4] = USB2_PORT_MID(OC_SKIP), /* Per-key RGB */
+ [5] = USB2_PORT_TYPE_C(OC_SKIP), /* USB Type-C */
+ [6] = USB2_PORT_MID(OC_SKIP), /* XFI */
+ [7] = USB2_PORT_MID(OC_SKIP), /* Camera */
+ [8] = USB2_PORT_MID(OC_SKIP), /* Light guide */
+ [9] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */
+ [13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
+ }"
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3_2 */
+ [1] = USB3_PORT_DEFAULT(OC_SKIP), /* ANX7440 */
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3_4 */
+ [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3_3 */
+ }"
end
device pci 14.2 on end # Shared SRAM
device pci 14.3 on # CNVi wifi
@@ -119,9 +121,11 @@ chip soc/intel/cannonlake
device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 on # SATA
- register "SataPortsEnable[1]" = "1" # SATA1A (SSD)
- register "SataPortsEnable[3]" = "1" # SATA3 (M.2_SATA3)
- register "SataPortsEnable[4]" = "1" # SATA4 (SSD2)
+ register "SataPortsEnable" = "{
+ [1] = 1, /* SATA1A (SSD) */
+ [3] = 1, /* SATA3 (M.2_SATA3) */
+ [4] = 1, /* SATA4 (SSD2) */
+ }"
end
device pci 19.2 off end # UART #2
device pci 1a.0 off end # eMMC
diff --git a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb
index a39622cea3..b34976201c 100644
--- a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb
+++ b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb
@@ -3,20 +3,22 @@ chip soc/intel/cannonlake
subsystemid 0x1558 0x1404 inherit
device pci 14.0 on # USB xHCI
- # USB2
- register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1
- register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # 3G / LTE
- register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 3
- register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB Board port 4
- register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera
- register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
- # USB3
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 1
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port 3
- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Board port 4
- register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Used by TBT
- register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Used by TBT
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_MID(OC_SKIP), /* Type-A port 1 */
+ [1] = USB2_PORT_MID(OC_SKIP), /* 3G / LTE */
+ [2] = USB2_PORT_TYPE_C(OC_SKIP), /* Type-C port 3 */
+ [3] = USB2_PORT_MID(OC_SKIP), /* USB Board port 4 */
+ [6] = USB2_PORT_MAX(OC_SKIP), /* Camera */
+ [9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
+ }"
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A port 1 */
+ [1] = USB3_PORT_DEFAULT(OC_SKIP), /* 4G */
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C port 3 */
+ [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB Board port 4 */
+ [4] = USB3_PORT_EMPTY, /* Used by TBT */
+ [5] = USB3_PORT_EMPTY, /* Used by TBT */
+ }"
end
device pci 15.0 on # I2C #0
chip drivers/i2c/hid
@@ -29,8 +31,10 @@ chip soc/intel/cannonlake
end
end
device pci 17.0 on # SATA
- register "SataPortsEnable[0]" = "1"
- register "SataPortsEnable[2]" = "1"
+ register "SataPortsEnable" = "{
+ [0] = 1,
+ [2] = 1,
+ }"
end
device pci 1c.4 on # PCI Express Port 5
# PCI Express Root port #5 x4, Clock 4 (TBT)
diff --git a/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb b/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb
index f6be0eb358..bbfc2ea208 100644
--- a/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb
+++ b/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb
@@ -3,27 +3,31 @@ chip soc/intel/cannonlake
subsystemid 0x1558 0x1403 inherit
device pci 14.0 on # USB xHCI
- # USB2
- register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1
- register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # 3G / LTE
- register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 3
- register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB Board port 4
- register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera
- register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
- # USB3
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 1
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port 3
- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Board port 4
- register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Used by TBT
- register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Used by TBT
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_MID(OC_SKIP), /* Type-A port 1 */
+ [1] = USB2_PORT_MID(OC_SKIP), /* 3G / LTE */
+ [2] = USB2_PORT_TYPE_C(OC_SKIP), /* Type-C port 3 */
+ [3] = USB2_PORT_MID(OC_SKIP), /* USB Board port 4 */
+ [6] = USB2_PORT_MAX(OC_SKIP), /* Camera */
+ [9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
+ }"
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A port 1 */
+ [1] = USB3_PORT_DEFAULT(OC_SKIP), /* 4G */
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C port 3 */
+ [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB Board port 4 */
+ [4] = USB3_PORT_EMPTY, /* Used by TBT */
+ [5] = USB3_PORT_EMPTY, /* Used by TBT */
+ }"
end
device pci 15.0 on # I2C #0
# I2C HID not supported on galp4
end
device pci 17.0 on # SATA
- register "SataPortsEnable[0]" = "1"
- register "SataPortsEnable[2]" = "1"
+ register "SataPortsEnable" = "{
+ [0] = 1,
+ [2] = 1,
+ }"
end
device pci 1c.4 on # PCI Express Port 5
# PCI Express Root port #5 x4, Clock 4 (TBT)
diff --git a/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb b/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb
index e85cf63623..164774a42d 100644
--- a/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb
+++ b/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb
@@ -3,16 +3,18 @@ chip soc/intel/cannonlake
subsystemid 0x1558 0x1401 inherit
device pci 14.0 on # USB xHCI
- # USB2
- register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1
- register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 2
- register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 3
- register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera
- register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
- # USB3
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 1
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port 2
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 3
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_MID(OC_SKIP), /* Type-A port 1 */
+ [1] = USB2_PORT_TYPE_C(OC_SKIP), /* Type-C port 2 */
+ [2] = USB2_PORT_MID(OC_SKIP), /* Type-A port 3 */
+ [6] = USB2_PORT_MAX(OC_SKIP), /* Camera */
+ [9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
+ }"
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A port 1 */
+ [1] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C port 2 */
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A port 3 */
+ }"
end
device pci 15.0 on # I2C #0
chip drivers/i2c/hid
@@ -26,12 +28,14 @@ chip soc/intel/cannonlake
end
device pci 17.0 on # SATA
register "SataSalpSupport" = "1"
- # Port 2 (J_SSD2)
- register "SataPortsEnable[1]" = "1"
- register "SataPortsDevSlp[1]" = "1"
- # Port 3 (J_SSD1)
- register "SataPortsEnable[2]" = "1"
- register "SataPortsDevSlp[2]" = "1"
+ register "SataPortsEnable" = "{
+ [1] = 1, /* Port 2 (J_SSD2) */
+ [2] = 1, /* Port 3 (J_SSD1) */
+ }"
+ register "SataPortsDevSlp" = "{
+ [1] = 1, /* Port 2 (J_SSD2) */
+ [2] = 1, /* Port 3 (J_SSD1) */
+ }"
end
device pci 1c.5 on # PCI Express Port 6
device pci 00.0 on end # x1 Card reader
diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb
index d25b18a43e..4ae412d155 100644
--- a/src/mainboard/system76/gaze15/devicetree.cb
+++ b/src/mainboard/system76/gaze15/devicetree.cb
@@ -67,19 +67,21 @@ chip soc/intel/cannonlake
device pci 12.6 off end # GSPI #2
device pci 13.0 off end # Integrated Sensor Hub
device pci 14.0 on # USB xHCI
- # USB2
- register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Right
- register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Left
- register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C
- register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 2 Left
- register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
- register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
- register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
- # USB3
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Right
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Left
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_MID(OC_SKIP), /* USB 3 Right */
+ [1] = USB2_PORT_MID(OC_SKIP), /* USB 3 Left */
+ [2] = USB2_PORT_TYPE_C(OC_SKIP), /* Type-C */
+ [5] = USB2_PORT_MID(OC_SKIP), /* USB 2 Left */
+ [7] = USB2_PORT_MID(OC_SKIP), /* Camera */
+ [9] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */
+ [13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
+ }"
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3 Right */
+ [1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3 Left */
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C */
+ [3] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C */
+ }"
end
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 on end # Shared SRAM
@@ -100,8 +102,10 @@ chip soc/intel/cannonlake
device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 on # SATA
- register "SataPortsEnable[1]" = "1" # SSD (SATA1A)
- register "SataPortsEnable[4]" = "1" # HDD (SATA4)
+ register "SataPortsEnable" = "{
+ [1] = 1, /* SSD (SATA1A) */
+ [4] = 1, /* HDD (SATA4) */
+ }"
end
device pci 19.0 off end # I2C #4
device pci 19.1 off end # I2C #5
diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb
index 733d020979..f17862f4af 100644
--- a/src/mainboard/system76/oryp5/devicetree.cb
+++ b/src/mainboard/system76/oryp5/devicetree.cb
@@ -75,22 +75,24 @@ chip soc/intel/cannonlake
device pci 12.6 off end # GSPI #2
device pci 13.0 off end # Integrated Sensor Hub
device pci 14.0 on # USB xHCI
- # USB2
- register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C
- register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C/DP
- register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Right
- register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Left
- register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Per-key RGB
- register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # 3G/LTE
- register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
- register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
- register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # WLAN/Bluetooth
- # USB3
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C/DP
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Right
- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Left
- register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 3G/LTE
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_TYPE_C(OC_SKIP), /* Type-C */
+ [1] = USB2_PORT_TYPE_C(OC_SKIP), /* Type-C/DP */
+ [2] = USB2_PORT_MID(OC_SKIP), /* USB 3 Right */
+ [3] = USB2_PORT_MID(OC_SKIP), /* USB 3 Left */
+ [4] = USB2_PORT_MID(OC_SKIP), /* Per-key RGB */
+ [6] = USB2_PORT_MID(OC_SKIP), /* 3G/LTE */
+ [7] = USB2_PORT_MID(OC_SKIP), /* Camera */
+ [9] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */
+ [13] = USB2_PORT_MID(OC_SKIP), /* WLAN/Bluetooth */
+ }"
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C */
+ [1] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C/DP */
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3 Right */
+ [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3 Left */
+ [6] = USB3_PORT_DEFAULT(OC_SKIP), /* 3G/LTE */
+ }"
end
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 on end # Shared SRAM
@@ -113,8 +115,10 @@ chip soc/intel/cannonlake
device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 on # SATA
- register "SataPortsEnable[1]" = "1" # SSD (SATA1A)
- register "SataPortsEnable[4]" = "1" # HDD (SATA4)
+ register "SataPortsEnable" = "{
+ [1] = 1, /* SSD (SATA1A) */
+ [4] = 1, /* HDD (SATA4) */
+ }"
end
device pci 19.0 off end # I2C #4
device pci 19.1 off end # I2C #5
diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb
index a05b5bd9e6..c0c1b4a12a 100644
--- a/src/mainboard/system76/oryp6/devicetree.cb
+++ b/src/mainboard/system76/oryp6/devicetree.cb
@@ -72,19 +72,21 @@ chip soc/intel/cannonlake
device pci 12.6 off end # GSPI #2
device pci 13.0 off end # Integrated Sensor Hub
device pci 14.0 on # USB xHCI
- # USB2
- register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Left
- register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C
- register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Right 1
- register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Right 2
- register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Per-key RGB
- register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
- register "usb2_ports[10]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
- register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
- # USB3
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Left
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 right 1
- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 right 2
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_MID(OC_SKIP), /* USB 3 Left */
+ [1] = USB2_PORT_TYPE_C(OC_SKIP), /* Type-C */
+ [2] = USB2_PORT_MID(OC_SKIP), /* USB 3 Right 1 */
+ [3] = USB2_PORT_MID(OC_SKIP), /* USB 3 Right 2 */
+ [4] = USB2_PORT_MID(OC_SKIP), /* Per-key RGB */
+ [7] = USB2_PORT_MID(OC_SKIP), /* Camera */
+ [10] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */
+ [13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
+ }"
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3 Left */
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3 right 1 */
+ [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3 right 2 */
+ }"
end
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 on end # Shared SRAM
diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb
index b153855385..0899f624ec 100644
--- a/src/mainboard/system76/whl-u/devicetree.cb
+++ b/src/mainboard/system76/whl-u/devicetree.cb
@@ -69,20 +69,22 @@ chip soc/intel/cannonlake
device pci 12.6 off end # GSPI #2
device pci 13.0 off end # Integrated Sensor Hub
device pci 14.0 on # USB xHCI
- # USB2
- register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB-A
- register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # 3G / LTE
- register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C
- register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB-A
- register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera
- register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
- # USB3
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-A
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G on galp3-c, NC on darp5
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C
- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-A
- register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Used by TBT
- register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Used by TBT
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_MID(OC_SKIP), /* USB-A */
+ [1] = USB2_PORT_MID(OC_SKIP), /* 3G / LTE */
+ [2] = USB2_PORT_TYPE_C(OC_SKIP), /* USB-C */
+ [3] = USB2_PORT_MID(OC_SKIP), /* USB-A */
+ [6] = USB2_PORT_MAX(OC_SKIP), /* Camera */
+ [9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
+ }"
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-A */
+ [1] = USB3_PORT_DEFAULT(OC_SKIP), /* 4G on galp3-c, NC on darp5 */
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-C */
+ [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-A */
+ [4] = USB3_PORT_EMPTY, /* Used by TBT */
+ [5] = USB3_PORT_EMPTY, /* Used by TBT */
+ }"
end
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.3 on # CNVi wifi
@@ -103,8 +105,10 @@ chip soc/intel/cannonlake
device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 on # SATA
- register "SataPortsEnable[0]" = "1"
- register "SataPortsEnable[2]" = "1"
+ register "SataPortsEnable" = "{
+ [0] = 1,
+ [2] = 1,
+ }"
end
device pci 19.0 off end # I2C #4
device pci 19.1 off end # I2C #5
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 16:21:48 +0000