summaryrefslogtreecommitdiff
path: root/src/mainboard/system76/addw1
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard/system76/addw1')
-rw-r--r--src/mainboard/system76/addw1/Kconfig65
-rw-r--r--src/mainboard/system76/addw1/Kconfig.name2
-rw-r--r--src/mainboard/system76/addw1/Makefile.inc11
-rw-r--r--src/mainboard/system76/addw1/acpi/gpe.asl11
-rw-r--r--src/mainboard/system76/addw1/acpi/mainboard.asl13
-rw-r--r--src/mainboard/system76/addw1/acpi/sleep.asl11
-rw-r--r--src/mainboard/system76/addw1/board_info.txt6
-rw-r--r--src/mainboard/system76/addw1/bootblock.c9
-rw-r--r--src/mainboard/system76/addw1/cmos.default3
-rw-r--r--src/mainboard/system76/addw1/cmos.layout39
-rw-r--r--src/mainboard/system76/addw1/devicetree.cb205
-rw-r--r--src/mainboard/system76/addw1/dsdt.asl30
-rw-r--r--src/mainboard/system76/addw1/include/variant/gpio.h9
-rw-r--r--src/mainboard/system76/addw1/ramstage.c13
-rw-r--r--src/mainboard/system76/addw1/romstage.c27
-rw-r--r--src/mainboard/system76/addw1/variants/addw1/board_info.txt2
-rw-r--r--src/mainboard/system76/addw1/variants/addw1/data.vbtbin0 -> 6144 bytes
-rw-r--r--src/mainboard/system76/addw1/variants/addw1/gpio.c264
-rw-r--r--src/mainboard/system76/addw1/variants/addw1/gpio_early.c16
-rw-r--r--src/mainboard/system76/addw1/variants/addw1/hda_verb.c30
-rw-r--r--src/mainboard/system76/addw1/variants/addw1/overridetree.cb21
-rw-r--r--src/mainboard/system76/addw1/variants/addw1/tas5825m.c1479
22 files changed, 2266 insertions, 0 deletions
diff --git a/src/mainboard/system76/addw1/Kconfig b/src/mainboard/system76/addw1/Kconfig
new file mode 100644
index 0000000000..038dc1fe56
--- /dev/null
+++ b/src/mainboard/system76/addw1/Kconfig
@@ -0,0 +1,65 @@
+if BOARD_SYSTEM76_ADDW1
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_16384
+ select DRIVERS_I2C_HID
+ select DRIVERS_I2C_TAS5825M
+ select EC_SYSTEM76_EC
+ select EC_SYSTEM76_EC_BAT_THRESHOLDS
+ select EC_SYSTEM76_EC_COLOR_KEYBOARD
+ select EC_SYSTEM76_EC_OLED
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select HAVE_CMOS_DEFAULT
+ select HAVE_OPTION_TABLE
+ select INTEL_GMA_HAVE_VBT
+ select INTEL_LPSS_UART_FOR_CONSOLE
+ select MAINBOARD_HAS_LPC_TPM
+ select MAINBOARD_HAS_TPM2
+ select NO_UART_ON_SUPERIO
+ select PCIEXP_HOTPLUG
+ select SOC_INTEL_CANNONLAKE_PCH_H
+ select SOC_INTEL_COFFEELAKE if BOARD_SYSTEM76_ADDW1
+ select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+ select SPD_READ_BY_WORD
+ select SYSTEM_TYPE_LAPTOP
+ select TPM_RDRESP_NEED_DELAY
+
+config MAINBOARD_DIR
+ default "system76/addw1"
+
+config VARIANT_DIR
+ default "addw1" if BOARD_SYSTEM76_ADDW1
+
+config OVERRIDE_DEVICETREE
+ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config MAINBOARD_PART_NUMBER
+ default "addw1" if BOARD_SYSTEM76_ADDW1
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+ default "Adder WS"
+
+config MAINBOARD_VERSION
+ default "addw1" if BOARD_SYSTEM76_ADDW1
+
+config CBFS_SIZE
+ default 0xA00000
+
+config CONSOLE_POST
+ default y
+
+config ONBOARD_VGA_IS_PRIMARY
+ default y
+
+config UART_FOR_CONSOLE
+ default 2
+
+config DIMM_MAX
+ default 2
+
+config POST_DEVICE
+ default n
+
+endif
diff --git a/src/mainboard/system76/addw1/Kconfig.name b/src/mainboard/system76/addw1/Kconfig.name
new file mode 100644
index 0000000000..9bd91fa926
--- /dev/null
+++ b/src/mainboard/system76/addw1/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_SYSTEM76_ADDW1
+ bool "addw1"
diff --git a/src/mainboard/system76/addw1/Makefile.inc b/src/mainboard/system76/addw1/Makefile.inc
new file mode 100644
index 0000000000..fedde68c13
--- /dev/null
+++ b/src/mainboard/system76/addw1/Makefile.inc
@@ -0,0 +1,11 @@
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+
+bootblock-y += bootblock.c
+bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
+
+romstage-y += romstage.c
+
+ramstage-y += ramstage.c
+ramstage-y += variants/$(VARIANT_DIR)/gpio.c
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
+ramstage-y += variants/$(VARIANT_DIR)/tas5825m.c
diff --git a/src/mainboard/system76/addw1/acpi/gpe.asl b/src/mainboard/system76/addw1/acpi/gpe.asl
new file mode 100644
index 0000000000..7ef9a989c0
--- /dev/null
+++ b/src/mainboard/system76/addw1/acpi/gpe.asl
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// GPP_K6 SCI
+Method (_L06, 0, Serialized) {
+ Debug = Concatenate("GPE _L06: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO))
+ If (\_SB.PCI0.LPCB.EC0.ECOK) {
+ If (\_SB.PCI0.LPCB.EC0.WFNO == 1) {
+ Notify(\_SB.LID0, 0x80)
+ }
+ }
+}
diff --git a/src/mainboard/system76/addw1/acpi/mainboard.asl b/src/mainboard/system76/addw1/acpi/mainboard.asl
new file mode 100644
index 0000000000..4e67439c56
--- /dev/null
+++ b/src/mainboard/system76/addw1/acpi/mainboard.asl
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define EC_GPE_SCI 0x03 /* GPP_K3 */
+#define EC_GPE_SWI 0x06 /* GPP_K6 */
+#include <ec/system76/ec/acpi/ec.asl>
+
+Scope (\_SB) {
+ #include "sleep.asl"
+}
+
+Scope (\_GPE) {
+ #include "gpe.asl"
+}
diff --git a/src/mainboard/system76/addw1/acpi/sleep.asl b/src/mainboard/system76/addw1/acpi/sleep.asl
new file mode 100644
index 0000000000..48c50e075e
--- /dev/null
+++ b/src/mainboard/system76/addw1/acpi/sleep.asl
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Method called from _PTS prior to enter sleep state */
+Method (MPTS, 1) {
+ \_SB.PCI0.LPCB.EC0.PTS (Arg0)
+}
+
+/* Method called from _WAK prior to wakeup */
+Method (MWAK, 1) {
+ \_SB.PCI0.LPCB.EC0.WAK (Arg0)
+}
diff --git a/src/mainboard/system76/addw1/board_info.txt b/src/mainboard/system76/addw1/board_info.txt
new file mode 100644
index 0000000000..badfb66706
--- /dev/null
+++ b/src/mainboard/system76/addw1/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: System76
+Category: laptop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/system76/addw1/bootblock.c b/src/mainboard/system76/addw1/bootblock.c
new file mode 100644
index 0000000000..b351fbd8ef
--- /dev/null
+++ b/src/mainboard/system76/addw1/bootblock.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <variant/gpio.h>
+
+void bootblock_mainboard_early_init(void)
+{
+ variant_configure_early_gpios();
+}
diff --git a/src/mainboard/system76/addw1/cmos.default b/src/mainboard/system76/addw1/cmos.default
new file mode 100644
index 0000000000..d56495357c
--- /dev/null
+++ b/src/mainboard/system76/addw1/cmos.default
@@ -0,0 +1,3 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Enable
diff --git a/src/mainboard/system76/addw1/cmos.layout b/src/mainboard/system76/addw1/cmos.layout
new file mode 100644
index 0000000000..ca7c7a4c5c
--- /dev/null
+++ b/src/mainboard/system76/addw1/cmos.layout
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+entries
+
+0 384 r 0 reserved_memory
+
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+
+# RTC_CLK_ALTCENTURY
+400 8 r 0 century
+
+409 2 e 7 power_on_after_fail
+412 4 e 6 debug_level
+984 16 h 0 check_sum
+
+enumerations
+
+4 0 Fallback
+4 1 Normal
+
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+
+7 0 Disable
+7 1 Enable
+7 2 Keep
+
+checksums
+
+checksum 408 983 984
diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb
new file mode 100644
index 0000000000..00cc3b89e1
--- /dev/null
+++ b/src/mainboard/system76/addw1/devicetree.cb
@@ -0,0 +1,205 @@
+chip soc/intel/cannonlake
+ register "common_soc_config" = "{
+ // Touchpad I2C bus
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 80,
+ .fall_time_ns = 110,
+ },
+ }"
+
+# CPU (soc/intel/cannonlake/cpu.c)
+ # Power limit
+ register "power_limits_config" = "{
+ .tdp_pl1_override = 45,
+ .tdp_pl2_override = 90,
+ }"
+
+ # Enable Enhanced Intel SpeedStep
+ register "eist_enable" = "1"
+
+# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
+ register "enable_c6dram" = "1"
+
+# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
+ # Misc
+ register "AcousticNoiseMitigation" = "1"
+
+ # Power
+ register "PchPmSlpS3MinAssert" = "3" # 50ms
+ register "PchPmSlpS4MinAssert" = "1" # 1s
+ register "PchPmSlpSusMinAssert" = "4" # 4s
+ register "PchPmSlpAMinAssert" = "4" # 2s
+
+ # Thermal
+ register "tcc_offset" = "8"
+
+ # Serial IRQ Continuous
+ register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+# PM Util (soc/intel/cannonlake/pmutil.c)
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "gpe0_dw0" = "PMC_GPP_K"
+ register "gpe0_dw1" = "PMC_GPP_G"
+ register "gpe0_dw2" = "PMC_GPP_E"
+
+# Actual device tree
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+
+ device domain 0 on
+ subsystemid 0x1558 0x65d1 inherit
+ device pci 00.0 on end # Host Bridge
+ device pci 01.0 on # GPU Port
+ # PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
+ register "PcieClkSrcUsage[8]" = "0x40"
+ register "PcieClkSrcClkReq[8]" = "8"
+ end
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 04.0 on # SA Thermal device
+ register "Device4Enable" = "1"
+ end
+ device pci 12.0 on end # Thermal Subsystem
+ device pci 12.5 off end # UFS SCS
+ device pci 12.6 off end # GSPI #2
+ device pci 13.0 off end # Integrated Sensor Hub
+ device pci 14.0 on # USB xHCI
+ # USB2
+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C and DisplayPort
+ register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 2
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 1 audio
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 1 back
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+ register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Per-Key RGB keyboard
+ register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+ register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+ # USB3
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C and DisplayPort
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 right
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C (without TBT)
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C (without TBT)
+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 1 audio
+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 1 back
+ end
+ device pci 14.2 on end # Shared SRAM
+ device pci 14.3 on # CNVi wifi
+ chip drivers/wifi/generic
+ register "wake" = "PME_B0_EN_BIT"
+ device generic 0 on end
+ end
+ end
+ device pci 14.5 off end # SDCard
+ device pci 15.0 on end # I2C #0
+ device pci 15.1 off end # I2C #1
+ device pci 15.2 off end # I2C #2
+ device pci 15.3 off end # I2C #3
+ device pci 16.0 off end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 16.5 off end # Management Engine Interface 4
+ device pci 17.0 on # SATA
+ register "SataPortsEnable[0]" = "1" # HDD (SATA0B)
+ register "SataPortsEnable[1]" = "1" # SSD1 (SATA1A)
+ end
+ device pci 19.2 off end # UART #2
+ device pci 1a.0 off end # eMMC
+ device pci 1b.0 on # PCI Express Port 17
+ # PCI Express root port #17 x4, Clock 0 (Thunderbolt)
+ register "PcieRpEnable[16]" = "1"
+ register "PcieRpLtrEnable[16]" = "1"
+ register "PcieRpHotPlug[16]" = "1"
+ register "PcieClkSrcUsage[0]" = "16"
+ register "PcieClkSrcClkReq[0]" = "0"
+ end
+ device pci 1b.1 off end # PCI Express Port 18
+ device pci 1b.2 off end # PCI Express Port 19
+ device pci 1b.3 off end # PCI Express Port 20
+ device pci 1b.4 on # PCI Express Port 21
+ # PCI Express root port #21 x4, Clock 10 (SSD2)
+ register "PcieRpEnable[20]" = "1"
+ register "PcieRpLtrEnable[20]" = "1"
+ register "PcieClkSrcUsage[10]" = "20"
+ register "PcieClkSrcClkReq[10]" = "10"
+ register "PcieRpSlotImplemented[20]" = "1"
+ end
+ device pci 1b.5 off end # PCI Express Port 22
+ device pci 1b.6 off end # PCI Express Port 23
+ device pci 1b.7 off end # PCI Express Port 24
+ device pci 1c.0 off end # PCI Express Port 1
+ device pci 1c.1 off end # PCI Express Port 2
+ device pci 1c.2 off end # PCI Express Port 3
+ device pci 1c.3 off end # PCI Express Port 4
+ device pci 1c.4 off end # PCI Express Port 5
+ device pci 1c.5 off end # PCI Express Port 6
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 off end # PCI Express Port 8
+ device pci 1d.0 on # PCI Express Port 9
+ # PCI Express root port #9 x4, Clock 9 (SSD1)
+ register "PcieRpEnable[8]" = "1"
+ register "PcieRpLtrEnable[8]" = "1"
+ register "PcieClkSrcUsage[9]" = "8"
+ register "PcieClkSrcClkReq[9]" = "9"
+ register "PcieRpSlotImplemented[8]" = "1"
+ end
+ device pci 1d.1 off end # PCI Express Port 10
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
+ device pci 1d.4 off end # PCI Express Port 13
+ device pci 1d.5 on # PCI Express Port 14
+ # PCI Express root port #14 x1, Clock 5 (GLAN)
+ register "PcieRpEnable[13]" = "1"
+ register "PcieRpLtrEnable[13]" = "1"
+ register "PcieClkSrcUsage[5]" = "13"
+ register "PcieClkSrcClkReq[5]" = "5"
+ register "PcieRpSlotImplemented[13]" = "1"
+ end
+ device pci 1d.6 on # PCI Express Port 15
+ # PCI Express root port #15 x1, Clock 7 (Card Reader)
+ register "PcieRpEnable[14]" = "1"
+ register "PcieRpLtrEnable[14]" = "1"
+ register "PcieClkSrcUsage[7]" = "14"
+ register "PcieClkSrcClkReq[7]" = "7"
+ register "PcieRpSlotImplemented[14]" = "1"
+ end
+ device pci 1d.7 on # PCI Express Port 16
+ # PCI Express root port #16 x1, Clock 6 (WLAN)
+ register "PcieRpEnable[15]" = "1"
+ register "PcieRpLtrEnable[15]" = "1"
+ register "PcieClkSrcUsage[6]" = "15"
+ register "PcieClkSrcClkReq[6]" = "6"
+ register "PcieRpSlotImplemented[15]" = "1"
+ end
+ device pci 1e.0 off end # UART #0
+ device pci 1e.1 off end # UART #1
+ device pci 1e.2 off end # GSPI #0
+ device pci 1e.3 off end # GSPI #1
+ device pci 1f.0 on # LPC Interface
+ register "gen1_dec" = "0x00040069"
+ register "gen2_dec" = "0x00fc0e01"
+ register "gen3_dec" = "0x00fc0f01"
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+ end
+ device pci 1f.1 off end # P2SB
+ device pci 1f.2 hidden end # Power Management Controller
+ device pci 1f.3 on # Intel HDA
+ register "PchHdaAudioLinkHda" = "1"
+ end
+ device pci 1f.4 on # SMBus
+ chip drivers/i2c/tas5825m
+ register "id" = "0"
+ device i2c 4e on end # (8bit address: 0x9c)
+ end
+ end
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 off end # GbE
+ end
+end
diff --git a/src/mainboard/system76/addw1/dsdt.asl b/src/mainboard/system76/addw1/dsdt.asl
new file mode 100644
index 0000000000..a48382b578
--- /dev/null
+++ b/src/mainboard/system76/addw1/dsdt.asl
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725
+)
+{
+ #include <acpi/dsdt_top.asl>
+ #include <soc/intel/common/block/acpi/acpi/platform.asl>
+ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Device (\_SB.PCI0) {
+ #include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+ #include <soc/intel/cannonlake/acpi/southbridge.asl>
+ }
+
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Scope (\_SB.PCI0.LPCB) {
+ #include <drivers/pc80/pc/ps2_controller.asl>
+ }
+
+ #include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/system76/addw1/include/variant/gpio.h b/src/mainboard/system76/addw1/include/variant/gpio.h
new file mode 100644
index 0000000000..95d576294f
--- /dev/null
+++ b/src/mainboard/system76/addw1/include/variant/gpio.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+void variant_configure_early_gpios(void);
+void variant_configure_gpios(void);
+
+#endif
diff --git a/src/mainboard/system76/addw1/ramstage.c b/src/mainboard/system76/addw1/ramstage.c
new file mode 100644
index 0000000000..ca6f64b158
--- /dev/null
+++ b/src/mainboard/system76/addw1/ramstage.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <variant/gpio.h>
+
+static void mainboard_init(void *chip_info)
+{
+ variant_configure_gpios();
+}
+
+struct chip_operations mainboard_ops = {
+ .init = mainboard_init,
+};
diff --git a/src/mainboard/system76/addw1/romstage.c b/src/mainboard/system76/addw1/romstage.c
new file mode 100644
index 0000000000..b2b6e47ed4
--- /dev/null
+++ b/src/mainboard/system76/addw1/romstage.c
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/cnl_memcfg_init.h>
+#include <soc/romstage.h>
+
+static const struct cnl_mb_cfg memcfg = {
+ .spd[0] = {
+ .read_type = READ_SMBUS,
+ .spd_spec = {.spd_smbus_address = 0xa0},
+ },
+ .spd[2] = {
+ .read_type = READ_SMBUS,
+ .spd_spec = {.spd_smbus_address = 0xa4},
+ },
+ .rcomp_resistor = { 121, 75, 100 },
+ .rcomp_targets = { 50, 25, 20, 20, 26 },
+ .dq_pins_interleaved = 1,
+ .vref_ca_config = 2,
+};
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+ // Allow higher memory speeds
+ memupd->FspmConfig.SaOcSupport = 1;
+
+ cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
+}
diff --git a/src/mainboard/system76/addw1/variants/addw1/board_info.txt b/src/mainboard/system76/addw1/variants/addw1/board_info.txt
new file mode 100644
index 0000000000..702a8e0c53
--- /dev/null
+++ b/src/mainboard/system76/addw1/variants/addw1/board_info.txt
@@ -0,0 +1,2 @@
+Board name: addw1
+Release year: 2019
diff --git a/src/mainboard/system76/addw1/variants/addw1/data.vbt b/src/mainboard/system76/addw1/variants/addw1/data.vbt
new file mode 100644
index 0000000000..d4a3dc0815
--- /dev/null
+++ b/src/mainboard/system76/addw1/variants/addw1/data.vbt
Binary files differ
diff --git a/src/mainboard/system76/addw1/variants/addw1/gpio.c b/src/mainboard/system76/addw1/variants/addw1/gpio.c
new file mode 100644
index 0000000000..179e9ebb91
--- /dev/null
+++ b/src/mainboard/system76/addw1/variants/addw1/gpio.c
@@ -0,0 +1,264 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include <variant/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+ /* ------- GPIO Group GPD ------- */
+ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), // PM_BATLOW#
+ PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
+ PAD_NC(GPD2, NONE),
+ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
+ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
+ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
+ PAD_NC(GPD6, NONE),
+ PAD_NC(GPD7, NONE),
+ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK
+ PAD_NC(GPD9, NONE),
+ PAD_NC(GPD10, NONE),
+ PAD_NC(GPD11, NONE),
+
+ /* ------- GPIO Group GPP_A ------- */
+ PAD_CFG_GPO(GPP_A0, 0, DEEP), // SB_KBCRST#
+ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), // LPC_AD0
+ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), // LPC_AD1
+ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), // LPC_AD2
+ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), // LPC_AD3
+ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
+ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ
+ PAD_CFG_GPI(GPP_A7, NONE, DEEP), // SCI#_GPP_A7
+ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // ECCLKRUN#
+ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // PCLK_KBC
+ PAD_NC(GPP_A10, DN_20K),
+ PAD_NC(GPP_A11, UP_20K),
+ PAD_NC(GPP_A12, NONE),
+ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN#
+ PAD_NC(GPP_A14, NONE),
+ PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), // SUS_PWR_ACK#
+ PAD_NC(GPP_A16, DN_20K),
+ PAD_CFG_GPI(GPP_A17, NONE, DEEP), // AMP_TYPE_DET
+ PAD_CFG_GPO(GPP_A18, 1, DEEP), // SB_BLON
+ PAD_NC(GPP_A19, NONE),
+ PAD_CFG_GPO(GPP_A20, 1, DEEP), // PEX_WAKE#
+ PAD_NC(GPP_A21, NONE),
+ PAD_CFG_GPO(GPP_A22, 1, DEEP), // SMARTAMP_SW
+ PAD_CFG_GPI(GPP_A23, NONE, DEEP), // SMART AMP PWR (L:3.3VS H:3.3V)
+
+ /* ------- GPIO Group GPP_B ------- */
+ PAD_CFG_GPI(GPP_B0, NONE, DEEP), // TPM_PIRQ#
+ PAD_NC(GPP_B1, NONE),
+ PAD_NC(GPP_B2, NONE),
+ // PCH_GPP_B3 (touchpad interrupt)
+ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, EDGE_SINGLE, INVERT),
+ PAD_NC(GPP_B4, NONE),
+ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // TBT_CLKREQ#
+ PAD_NC(GPP_B6, NONE),
+ PAD_NC(GPP_B7, NONE),
+ PAD_NC(GPP_B8, NONE),
+ PAD_NC(GPP_B9, NONE),
+ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // GLAN_CLKREQ#
+ PAD_NC(GPP_B11, NONE),
+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+ _PAD_CFG_STRUCT(GPP_B13, 0x44000601, 0x0000), // PLT_RST#
+ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
+ PAD_NC(GPP_B15, NONE),
+ PAD_NC(GPP_B16, NONE),
+ PAD_NC(GPP_B17, NONE),
+ PAD_CFG_GPI(GPP_B18, NONE, DEEP), // NO REBOOT STRAP
+ PAD_NC(GPP_B19, NONE),
+ PAD_CFG_GPI(GPP_B20, NONE, DEEP), // SMI#_GPP_B20
+ PAD_NC(GPP_B21, NONE),
+ PAD_CFG_GPI(GPP_B22, NONE, DEEP), // BOOT BIOS STRAP
+ PAD_CFG_GPI(GPP_B23, NONE, DEEP), // DCI-OOB STRAP
+
+ /* ------- GPIO Group GPP_C ------- */
+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
+ _PAD_CFG_STRUCT(GPP_C2, 0x40880100, 0x0000), // CNVI_WAKE#
+ PAD_NC(GPP_C3, NONE),
+ PAD_NC(GPP_C4, NONE),
+ PAD_CFG_GPI(GPP_C5, NONE, DEEP), // WLAN_WAKEUP#
+ PAD_NC(GPP_C6, NONE),
+ PAD_NC(GPP_C7, NONE),
+ PAD_NC(GPP_C8, NONE),
+ PAD_CFG_GPI(GPP_C9, NONE, DEEP), // BOARD_ID2
+ PAD_CFG_GPI(GPP_C10, NONE, DEEP), // BOARD_ID1
+ PAD_CFG_GPI(GPP_C11, NONE, DEEP), // TBT_DET#
+ PAD_CFG_GPI(GPP_C12, NONE, DEEP), // GC6_FB_EN_PCH
+ PAD_CFG_GPI(GPP_C13, NONE, DEEP), // TPM_DET
+ PAD_CFG_GPO(GPP_C14, 1, DEEP), // GPU_EVENT#
+ PAD_CFG_GPI(GPP_C15, NONE, DEEP), // 100K pull-down
+ PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // TP_DAT_PCH_I2C0
+ PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // TP_CLK_PCH_I2C0
+ PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), // I2C1_SDA
+ PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1), // I2C1_SCL
+ //PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
+ //PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
+ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), // UART2_RTS#
+ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), // UART2_CTS#
+
+ /* ------- GPIO Group GPP_D ------- */
+ PAD_NC(GPP_D0, NONE),
+ PAD_NC(GPP_D1, NONE),
+ PAD_NC(GPP_D2, NONE),
+ PAD_NC(GPP_D3, NONE),
+ PAD_NC(GPP_D4, NONE),
+ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // CNVI_RST#
+ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // CNVI_CLKREQ
+ PAD_NC(GPP_D7, NONE),
+ PAD_NC(GPP_D8, NONE),
+ PAD_NC(GPP_D9, NONE),
+ PAD_NC(GPP_D10, NONE),
+ PAD_NC(GPP_D11, NONE),
+ PAD_NC(GPP_D12, NONE),
+ PAD_NC(GPP_D13, NONE),
+ PAD_NC(GPP_D14, NONE),
+ PAD_NC(GPP_D15, NONE),
+ PAD_NC(GPP_D16, NONE),
+ PAD_NC(GPP_D17, NONE),
+ PAD_NC(GPP_D18, NONE),
+ PAD_NC(GPP_D19, NONE),
+ PAD_NC(GPP_D20, NONE),
+ PAD_NC(GPP_D21, NONE),
+ PAD_NC(GPP_D22, NONE),
+ PAD_NC(GPP_D23, NONE),
+
+ /* ------- GPIO Group GPP_E ------- */
+ PAD_NC(GPP_E0, NONE),
+ PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), // SATAGP1
+ PAD_NC(GPP_E2, NONE),
+ PAD_NC(GPP_E3, NONE),
+ PAD_NC(GPP_E4, NONE),
+ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), // SATA_DEVSLP1
+ PAD_CFG_GPO(GPP_E6, 1, DEEP), // PCH_MUTE#
+ PAD_NC(GPP_E7, NONE),
+ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATAHDD_LED#
+ PAD_NC(GPP_E9, NONE),
+ PAD_NC(GPP_E10, NONE),
+ PAD_NC(GPP_E11, NONE),
+ PAD_NC(GPP_E12, NONE),
+
+ /* ------- GPIO Group GPP_F ------- */
+ PAD_NC(GPP_F0, NONE),
+ PAD_NC(GPP_F1, NONE),
+ PAD_NC(GPP_F2, NONE),
+ PAD_CFG_GPO(GPP_F3, 1, DEEP), // GPP_F3_LAN_RST#
+ PAD_CFG_GPO(GPP_F4, 1, DEEP), // GPP_F4_TBT_RST#
+ PAD_NC(GPP_F5, NONE),
+ PAD_NC(GPP_F6, NONE),
+ PAD_NC(GPP_F7, NONE),
+ PAD_NC(GPP_F8, NONE),
+ PAD_CFG_GPO(GPP_F9, 0, DEEP), // PS8331_SW
+ PAD_CFG_GPI(GPP_F10, NONE, DEEP), // BIOS RECOVERY ENABLE STRAP
+ PAD_NC(GPP_F11, NONE),
+ PAD_NC(GPP_F12, NONE),
+ PAD_NC(GPP_F13, NONE),
+ PAD_CFG_GPI(GPP_F14, NONE, DEEP), // H_SKTOCC_N
+ PAD_NC(GPP_F15, NONE),
+ PAD_NC(GPP_F16, NONE),
+ PAD_NC(GPP_F17, NONE),
+ PAD_NC(GPP_F18, NONE),
+ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
+ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
+ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
+ //PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH
+ //PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN
+
+ /* ------- GPIO Group GPP_G ------- */
+ PAD_CFG_GPI(GPP_G0, NONE, DEEP), // GSYNC_DET
+ PAD_NC(GPP_G1, NONE), // test point
+ PAD_CFG_GPI(GPP_G2, NONE, DEEP), // NVSR_DET#
+ PAD_NC(GPP_G3, NONE),
+ PAD_NC(GPP_G4, NONE),
+ PAD_NC(GPP_G5, NONE),
+ PAD_CFG_GPI(GPP_G6, NONE, DEEP), // SWI#_GPP_G6
+ PAD_NC(GPP_G7, NONE),
+
+ /* ------- GPIO Group GPP_H ------- */
+ PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // WLAN_CLKREQ#
+ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // SD4.0_CLKREQ#
+ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // PEG_CLKREQ#
+ PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), // SSD1_CLKREQ#
+ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // SSD2_CLKREQ#
+ PAD_NC(GPP_H5, NONE),
+ PAD_CFG_GPO(GPP_H6, 1, DEEP), // PCIE_SSD1_RST#
+ PAD_CFG_GPO(GPP_H7, 1, DEEP), // PCIE_SSD2_RST#
+ PAD_CFG_GPI(GPP_H8, NONE, DEEP), // GPP_H8_LAN_RST#
+ PAD_CFG_GPI(GPP_H9, NONE, DEEP), // TBT_GPIO_WAKE#
+ PAD_NC(GPP_H10, NONE),
+ PAD_NC(GPP_H11, NONE),
+ PAD_CFG_GPI(GPP_H12, NONE, DEEP), // ESPI FLASH SHARING STRAP
+ PAD_CFG_GPI(GPP_H13, NONE, DEEP), // TBTA_HRESET
+ PAD_NC(GPP_H14, NONE),
+ PAD_CFG_GPI(GPP_H15, NONE, DEEP), // RESERVED STRAP
+ _PAD_CFG_STRUCT(GPP_H16, 0x44000101, 0x0000), // TBT_RTD3_PWR_EN
+ PAD_CFG_GPO(GPP_H17, 0, PLTRST), // TBT_FORCE_PWR
+ PAD_NC(GPP_H18, NONE),
+ PAD_NC(GPP_H19, NONE),
+ PAD_NC(GPP_H20, NONE),
+ PAD_CFG_GPI(GPP_H21, NONE, DEEP), // XTAL FREQUENCY SELECT STRAP
+ PAD_NC(GPP_H22, NONE),
+ _PAD_CFG_STRUCT(GPP_H23, 0x82880100, 0x0000), // TBCIO_PLUG_EVENT#
+
+ /* ------- GPIO Group GPP_I ------- */
+ PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), // ANX7411_HPD
+ PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), // HDMI_HPD
+ PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), // MDP_E_HPD
+ PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1), // MDP_A_TBT_HPD
+ PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // SB_IEDP_HPD
+ PAD_CFG_GPO(GPP_I5, 1, DEEP), // TBT_GPIO_RST#
+ PAD_NC(GPP_I6, NONE),
+ PAD_NC(GPP_I7, NONE),
+ PAD_CFG_GPO(GPP_I8, 1, DEEP), // SSD1_PWR_EN
+ PAD_CFG_GPO(GPP_I9, 1, DEEP), // SSD2_PWR_EN
+ PAD_NC(GPP_I10, NONE),
+ PAD_NC(GPP_I11, NONE),
+ PAD_CFG_GPO(GPP_I12, 1, DEEP), // SATA_PWR_EN
+ PAD_NC(GPP_I13, NONE),
+ PAD_NC(GPP_I14, NONE),
+
+ /* ------- GPIO Group GPP_J ------- */
+ PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+ PAD_CFG_GPO(GPP_J1, 1, DEEP), // GPP_J1
+ PAD_NC(GPP_J2, NONE),
+ PAD_NC(GPP_J3, NONE),
+ PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_BRI_DT
+ PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+ PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_RGI_DT
+ PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+ PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
+ PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
+ PAD_NC(GPP_J10, NONE),
+ PAD_NC(GPP_J11, DN_20K),
+
+ /* ------- GPIO Group GPP_K ------- */
+ PAD_CFG_GPO(GPP_K0, 0, DEEP), // GPP_K0_SPK_MUTE
+ PAD_CFG_GPO(GPP_K1, 0, DEEP), // GPP_K1_WOOFER_MUTE
+ PAD_NC(GPP_K2, NONE),
+ _PAD_CFG_STRUCT(GPP_K3, 0x40880100, 0x0000), // SCI#_GPP_K3
+ PAD_NC(GPP_K4, NONE),
+ PAD_NC(GPP_K5, NONE),
+ _PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI#_GPP_K6
+ PAD_CFG_GPI(GPP_K7, NONE, DEEP), // GPP_K7_LAN_WAKEUP#
+ PAD_CFG_GPO(GPP_K8, 1, DEEP), // GPP_K8_LAN_RTD3
+ PAD_NC(GPP_K9, NONE),
+ PAD_NC(GPP_K10, NONE),
+ PAD_NC(GPP_K11, NONE),
+ PAD_CFG_GPO(GPP_K12, 1, DEEP), // PCH_GPP_K12
+ PAD_NC(GPP_K13, NONE),
+ PAD_CFG_GPO(GPP_K14, 0, DEEP), // GPP_K14_TEST_R
+ _PAD_CFG_STRUCT(GPP_K15, 0x80100100, 0x0000), // GPP_K15_INTP_OUT
+ PAD_NC(GPP_K16, NONE),
+ PAD_NC(GPP_K17, NONE),
+ PAD_CFG_GPO(GPP_K18, 1, DEEP), // GPP_K18_TBT_WAKE#
+ _PAD_CFG_STRUCT(GPP_K19, 0x42800101, 0x0000), // SMI#_GPP_K19
+ PAD_NC(GPP_K20, NONE),
+ PAD_NC(GPP_K21, NONE),
+ PAD_NC(GPP_K22, NONE),
+ PAD_NC(GPP_K23, NONE),
+};
+
+void variant_configure_gpios(void)
+{
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/system76/addw1/variants/addw1/gpio_early.c b/src/mainboard/system76/addw1/variants/addw1/gpio_early.c
new file mode 100644
index 0000000000..9af888be4c
--- /dev/null
+++ b/src/mainboard/system76/addw1/variants/addw1/gpio_early.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include <variant/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
+ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
+ PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH
+ PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN
+};
+
+void variant_configure_early_gpios(void)
+{
+ gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/system76/addw1/variants/addw1/hda_verb.c b/src/mainboard/system76/addw1/variants/addw1/hda_verb.c
new file mode 100644
index 0000000000..ca440e4707
--- /dev/null
+++ b/src/mainboard/system76/addw1/variants/addw1/hda_verb.c
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* Realtek, ALC1220 */
+ 0x10ec1220, /* Vendor ID */
+ 0x155865d1, /* Subsystem ID */
+ 12, /* Number of entries */
+ AZALIA_SUBVENDOR(0, 0x155865d1),
+ AZALIA_PIN_CFG(0, 0x12, 0x90a60130), // DMIC
+ AZALIA_PIN_CFG(0, 0x14, 0x0421101f), // FRONT (Port-D)
+ AZALIA_PIN_CFG(0, 0x15, 0x40000000), // SURR (Port-A)
+ AZALIA_PIN_CFG(0, 0x16, 0x411111f0), // CENTER/LFE (Port-G)
+ AZALIA_PIN_CFG(0, 0x17, 0x411111f0), // SIDE (Port-H)
+ AZALIA_PIN_CFG(0, 0x18, 0x04a11040), // MIC1 (Port-B)
+ AZALIA_PIN_CFG(0, 0x19, 0x411111f0), // MIC2 (Port-F)
+ AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), // LINE1 (Port-C)
+ AZALIA_PIN_CFG(0, 0x1b, 0x90170110), // LINE2 (Port-E)
+ AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d), // PCBEEP
+ AZALIA_PIN_CFG(0, 0x1e, 0x04451150), // S/PDIF-OUT
+};
+
+const u32 pc_beep_verbs[] = {
+ // Enable DMIC microphone on ALC1220
+ 0x02050036,
+ 0x02042a6a,
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/system76/addw1/variants/addw1/overridetree.cb b/src/mainboard/system76/addw1/variants/addw1/overridetree.cb
new file mode 100644
index 0000000000..ada23b2aa2
--- /dev/null
+++ b/src/mainboard/system76/addw1/variants/addw1/overridetree.cb
@@ -0,0 +1,21 @@
+chip soc/intel/cannonlake
+ # Serial I/O
+ register "SerialIoDevMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
+ [PchSerialIoIndexUART2] = PchSerialIoPci, // Debug console
+ }"
+
+ device domain 0 on
+ subsystemid 0x1558 0x65d1 inherit
+ device pci 15.0 on # I2C #0
+ chip drivers/i2c/hid
+ register "generic.hid" = ""PNP0C50""
+ register "generic.desc" = ""Synaptics Touchpad""
+ register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)"
+ register "generic.probed" = "1"
+ register "hid_desc_reg_offset" = "0x20"
+ device i2c 2c on end
+ end
+ end
+ end
+end
diff --git a/src/mainboard/system76/addw1/variants/addw1/tas5825m.c b/src/mainboard/system76/addw1/variants/addw1/tas5825m.c
new file mode 100644
index 0000000000..97cde851b0
--- /dev/null
+++ b/src/mainboard/system76/addw1/variants/addw1/tas5825m.c
@@ -0,0 +1,1479 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/i2c/tas5825m/tas5825m.h>
+
+int tas5825m_setup(struct device *dev, int id)
+{
+ int res;
+
+ res = tas5825m_set_book(dev, 0x00);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_write_at(dev, 0x03, 0x02);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_write_at(dev, 0x01, 0x11);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x00);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x00);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x00);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x00);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_book(dev, 0x00);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_write_at(dev, 0x03, 0x02);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x00);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x00);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x00);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x00);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_book(dev, 0x00);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_write_at(dev, 0x03, 0x12);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_book(dev, 0x00);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_write_at(dev, 0x48, 0x0C);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_book(dev, 0x64);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x01);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x00, 0xFE, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00,
+ 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+ 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+ 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+ 0x00, 0xFC, 0x50, 0x00, 0x00, 0xFC, 0x00, 0x00,
+ 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+ 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+ 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+ 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+ 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+ 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+ 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+ 0x00, 0x82, 0x00, 0x93, 0x00, 0xFC, 0x00, 0x00,
+ 0x84, 0xC1, 0x02, 0x9F, 0x08, 0x18, 0x10, 0x00,
+ 0x02, 0x28, 0x00, 0x03, 0x8F, 0x00, 0xFF, 0xF8,
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x02);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x02, 0x60, 0x00, 0x01, 0x84, 0xA0, 0x02, 0x00,
+ 0x84, 0x02, 0x04, 0x03, 0x00, 0x26, 0x20, 0x96,
+ 0x84, 0xA2, 0x04, 0x02, 0x84, 0xC1, 0x02, 0xBC,
+ 0x84, 0x49, 0x03, 0x64, 0x08, 0xFC, 0x0C, 0x99,
+ 0x02, 0x70, 0x00, 0x04, 0x84, 0xC1, 0x02, 0xBD,
+ 0xE0, 0x10, 0x31, 0xAD, 0x84, 0xCA, 0x20, 0xE0,
+ 0xF0, 0x1C, 0x31, 0xAE, 0xF0, 0x1C, 0x31, 0xAF,
+ 0x02, 0x68, 0x00, 0x03, 0xF0, 0x1C, 0x31, 0xB0,
+ 0xF0, 0x1D, 0x31, 0xB1, 0x02, 0x78, 0x00, 0x02,
+ 0x84, 0x41, 0x03, 0x78, 0x80, 0x27, 0x80, 0xF9,
+ 0x08, 0xFC, 0x0C, 0x98, 0x84, 0x83, 0x03, 0x6A,
+ 0xE0, 0x10, 0x11, 0xAD, 0x84, 0xC2, 0x00, 0xE0,
+ 0xF0, 0x1C, 0x11, 0xAE, 0xF0, 0x1C, 0x11, 0xAF,
+ 0xF0, 0x1C, 0x11, 0xB0, 0xF0, 0x1D, 0x11, 0xB1,
+ 0x84, 0x59, 0x03, 0x65, 0x80, 0x27, 0x80, 0xF8,
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x03);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x84, 0x83, 0x03, 0x6B, 0xE2, 0x57, 0x91, 0xB2,
+ 0x84, 0xC1, 0x02, 0xBD, 0x84, 0x82, 0x60, 0xE0,
+ 0xF0, 0x1C, 0x71, 0xB3, 0xF0, 0x1C, 0x71, 0xB4,
+ 0xF0, 0x1C, 0x71, 0xB5, 0xF0, 0x1D, 0x71, 0xB6,
+ 0x84, 0x51, 0x03, 0x79, 0x80, 0x27, 0x80, 0xFB,
+ 0x84, 0x83, 0x03, 0x6C, 0xE0, 0x10, 0x11, 0xB2,
+ 0x84, 0xC2, 0x40, 0xE0, 0xF0, 0x1C, 0x51, 0xB3,
+ 0xF0, 0x1C, 0x51, 0xB4, 0xF0, 0x1C, 0x51, 0xB5,
+ 0xF0, 0x1D, 0x51, 0xB6, 0x84, 0x4B, 0x03, 0x64,
+ 0x84, 0x49, 0x03, 0x77, 0x86, 0xA1, 0x01, 0xB7,
+ 0x84, 0x43, 0x03, 0x78, 0x02, 0x11, 0xFF, 0xFC,
+ 0x84, 0x41, 0x03, 0x7E, 0x80, 0x27, 0x80, 0xFA,
+ 0x84, 0x83, 0x03, 0x6D, 0xE2, 0x57, 0x80, 0x00,
+ 0x84, 0xC1, 0x02, 0xBD, 0x84, 0x82, 0x20, 0xE0,
+ 0xF0, 0x1C, 0x31, 0xB8, 0xF0, 0x1C, 0x31, 0xB9,
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x04);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0xF0, 0x1C, 0x31, 0xBA, 0xF0, 0x1D, 0x31, 0xBB,
+ 0x86, 0xA1, 0x01, 0xB7, 0x80, 0x27, 0x80, 0xF9,
+ 0x84, 0x83, 0x03, 0x6E, 0xE0, 0x10, 0x00, 0x00,
+ 0x84, 0xC2, 0x00, 0xE0, 0xF0, 0x1C, 0x11, 0xB8,
+ 0xF0, 0x1C, 0x11, 0xB9, 0xF0, 0x1C, 0x11, 0xBA,
+ 0xF0, 0x1D, 0x11, 0xBB, 0x86, 0xA1, 0x01, 0x9D,
+ 0x80, 0x27, 0x80, 0xF8, 0x84, 0x83, 0x03, 0x6F,
+ 0x84, 0x5B, 0x03, 0x65, 0x66, 0x6D, 0x60, 0x00,
+ 0xEE, 0x64, 0x80, 0x00, 0x02, 0xC3, 0x00, 0x10,
+ 0x62, 0x6D, 0x40, 0x00, 0xEA, 0x64, 0x60, 0x00,
+ 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x81,
+ 0x09, 0x07, 0x08, 0x88, 0x08, 0xFC, 0x28, 0x53,
+ 0x0D, 0x00, 0x10, 0x18, 0x84, 0xC3, 0x03, 0x24,
+ 0x08, 0x60, 0x28, 0x50, 0x84, 0x80, 0x04, 0x02,
+ 0xE4, 0x00, 0x00, 0x80, 0x86, 0xC1, 0x01, 0x9F,
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x05);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x88, 0x47, 0x20, 0x81, 0x0D, 0x00, 0x10, 0x20,
+ 0x84, 0x53, 0x03, 0x79, 0x84, 0x4B, 0x03, 0x77,
+ 0x84, 0x43, 0x03, 0x7E, 0x00, 0x42, 0x20, 0x85,
+ 0x84, 0xDB, 0x03, 0x23, 0x08, 0xFC, 0x38, 0x10,
+ 0x02, 0x48, 0x02, 0xBC, 0x02, 0x40, 0x02, 0xBD,
+ 0xE4, 0x10, 0x11, 0x9E, 0x00, 0xFE, 0x20, 0x88,
+ 0x88, 0x6C, 0x00, 0x00, 0x02, 0x48, 0x02, 0xBC,
+ 0x02, 0x40, 0x02, 0xBD, 0x02, 0x80, 0x00, 0x00,
+ 0x84, 0xA1, 0x03, 0x6F, 0xE4, 0x00, 0x00, 0x00,
+ 0x84, 0xA1, 0x03, 0x6E, 0x84, 0xD1, 0x03, 0x6C,
+ 0xE0, 0x00, 0x00, 0x00, 0xE8, 0x00, 0x00, 0x82,
+ 0x84, 0xC9, 0x03, 0x6D, 0x88, 0x07, 0x00, 0x80,
+ 0xEC, 0x00, 0x00, 0x81, 0x10, 0x00, 0x18, 0x01,
+ 0x88, 0x47, 0x00, 0x80, 0x02, 0x50, 0x02, 0xBC,
+ 0x00, 0xFE, 0x20, 0x99, 0x0C, 0x20, 0x08, 0x20,
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x06);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x02, 0x78, 0x00, 0x02, 0x02, 0x50, 0x02, 0xBC,
+ 0x02, 0x40, 0x02, 0xBD, 0x02, 0x70, 0x00, 0x06,
+ 0x84, 0x59, 0x03, 0x4F, 0xE2, 0x57, 0x91, 0xBC,
+ 0x02, 0xC3, 0x00, 0x10, 0x84, 0xC9, 0x02, 0xBD,
+ 0x84, 0xC2, 0x60, 0xE0, 0xF0, 0x1C, 0x71, 0xBD,
+ 0xF0, 0x1C, 0x71, 0xBE, 0x02, 0x68, 0x00, 0x05,
+ 0xF0, 0x1C, 0x71, 0xBF, 0xF0, 0x1D, 0x71, 0xC0,
+ 0xE4, 0x00, 0x11, 0xC3, 0x80, 0x27, 0x80, 0xE3,
+ 0xF4, 0x00, 0x11, 0xC1, 0xF4, 0x1F, 0x71, 0xC2,
+ 0xF4, 0x1C, 0x71, 0xC4, 0xF4, 0x1D, 0x71, 0xC5,
+ 0x84, 0x49, 0x03, 0x57, 0x80, 0x67, 0x80, 0xFB,
+ 0x02, 0xD3, 0x00, 0x10, 0xE0, 0x10, 0x31, 0xBC,
+ 0x84, 0xCA, 0x20, 0xE0, 0xF0, 0x1C, 0x31, 0xBD,
+ 0xF0, 0x1C, 0x31, 0xBE, 0xF0, 0x1C, 0x31, 0xBF,
+ 0xF0, 0x1D, 0x31, 0xC0, 0xE4, 0x00, 0x11, 0xC3,
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x07);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x80, 0x27, 0x80, 0xE1, 0xF4, 0x00, 0x11, 0xC1,
+ 0xF4, 0x1F, 0x31, 0xC2, 0xF4, 0x1C, 0x31, 0xC4,
+ 0xF4, 0x1D, 0x31, 0xC5, 0x84, 0xC2, 0x04, 0x05,
+ 0x08, 0xFC, 0x58, 0x10, 0x80, 0x67, 0x80, 0xF9,
+ 0x02, 0xD3, 0x00, 0x10, 0x84, 0xCA, 0x04, 0x04,
+ 0x08, 0xFC, 0x58, 0x31, 0x84, 0xCA, 0x04, 0x06,
+ 0x08, 0x00, 0x0A, 0x21, 0x84, 0xC2, 0x04, 0x07,
+ 0x08, 0x00, 0x0A, 0x00, 0xE4, 0x10, 0x31, 0xA3,
+ 0xE0, 0x10, 0x00, 0x00, 0xEA, 0x65, 0x60, 0x00,
+ 0x02, 0xC3, 0x00, 0x10, 0xEE, 0x65, 0x80, 0x00,
+ 0x02, 0xCB, 0x00, 0x10, 0x88, 0x47, 0x00, 0x82,
+ 0x09, 0x07, 0x09, 0x31, 0x08, 0xFC, 0x48, 0x13,
+ 0x0D, 0x00, 0x10, 0x38, 0x84, 0xCB, 0x03, 0x2C,
+ 0x08, 0x60, 0x48, 0x11, 0x84, 0x80, 0x04, 0x02,
+ 0xE4, 0x00, 0x00, 0x81, 0x02, 0x28, 0x00, 0x02,
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x08);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x88, 0x67, 0x20, 0x00, 0xE4, 0x00, 0x02, 0x00,
+ 0x84, 0xDB, 0x03, 0x2B, 0x80, 0x48, 0x00, 0x81,
+ 0x86, 0xD9, 0x01, 0xA9, 0x86, 0xC1, 0x01, 0xAA,
+ 0x0D, 0x00, 0x10, 0x38, 0x08, 0xFC, 0x3C, 0x12,
+ 0x84, 0x5B, 0x03, 0x4F, 0x84, 0x4B, 0x03, 0x57,
+ 0x84, 0xD2, 0x04, 0x02, 0x00, 0x62, 0x20, 0xE4,
+ 0x86, 0xD1, 0x01, 0xAC, 0x0D, 0x00, 0x10, 0x20,
+ 0x86, 0xC9, 0x01, 0xA8, 0x86, 0xC1, 0x01, 0xA7,
+ 0x00, 0xFE, 0x20, 0xE8, 0x08, 0x44, 0x26, 0x30,
+ 0x08, 0xFC, 0x3C, 0x71, 0x86, 0xC1, 0x01, 0xA6,
+ 0x84, 0xCA, 0x04, 0x02, 0x86, 0xD1, 0x01, 0xAB,
+ 0x84, 0x80, 0x04, 0x02, 0xE4, 0x00, 0x00, 0x80,
+ 0x88, 0x40, 0x00, 0x80, 0x08, 0xFC, 0x08, 0x50,
+ 0x02, 0x28, 0x00, 0x01, 0x02, 0xA3, 0x00, 0x18,
+ 0xE4, 0x40, 0x00, 0x00, 0x88, 0xC8, 0x00, 0x82,
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x09);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x84, 0xC9, 0x03, 0x2D, 0x86, 0xC1, 0x01, 0xA5,
+ 0x86, 0xD9, 0x01, 0xA4, 0x0D, 0x00, 0x10, 0x48,
+ 0x08, 0x44, 0x06, 0x13, 0x86, 0xC1, 0x01, 0xEF,
+ 0x84, 0x49, 0x03, 0x37, 0x00, 0xFC, 0x00, 0x00,
+ 0xE4, 0x10, 0x40, 0x83, 0xEC, 0x10, 0x20, 0x00,
+ 0x88, 0x47, 0x00, 0x82, 0x04, 0x80, 0xA8, 0xB3,
+ 0x84, 0x80, 0x04, 0x07, 0xE4, 0x00, 0x00, 0x83,
+ 0x84, 0xDB, 0x03, 0x2D, 0x88, 0x40, 0x00, 0x83,
+ 0x10, 0x00, 0x1A, 0x22, 0xE4, 0x80, 0xC0, 0x00,
+ 0x88, 0x40, 0x00, 0x81, 0x84, 0xD8, 0x04, 0x04,
+ 0x0C, 0x20, 0x08, 0x39, 0x86, 0xD1, 0x01, 0xF0,
+ 0x84, 0x81, 0x02, 0xBC, 0x86, 0xC9, 0x01, 0xF1,
+ 0xE0, 0x00, 0x11, 0xC7, 0x84, 0x82, 0x20, 0xE0,
+ 0x84, 0x82, 0x04, 0x02, 0xF0, 0x1C, 0x31, 0xC8,
+ 0xF0, 0x1C, 0x31, 0xC9, 0xF0, 0x1C, 0x31, 0xCA,
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x0A);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0xF0, 0x1D, 0x31, 0xCB, 0xE4, 0x00, 0x11, 0xCE,
+ 0x80, 0x27, 0x80, 0xE1, 0xF4, 0x00, 0x11, 0xCC,
+ 0xF4, 0x1F, 0x31, 0xCD, 0xF4, 0x1C, 0x31, 0xCF,
+ 0xF4, 0x1D, 0x31, 0xD0, 0x84, 0x41, 0x03, 0x2F,
+ 0x80, 0x67, 0x80, 0xF9, 0x02, 0xDB, 0x00, 0x10,
+ 0x8F, 0x30, 0x00, 0x00, 0x0C, 0x1C, 0x11, 0x74,
+ 0x08, 0x64, 0x66, 0x72, 0x0D, 0x00, 0x10, 0x40,
+ 0x08, 0x44, 0x06, 0x12, 0x84, 0xD2, 0x41, 0x00,
+ 0xE0, 0x10, 0x51, 0xD1, 0xF0, 0x1C, 0x11, 0xD2,
+ 0xF0, 0x1C, 0x11, 0xD3, 0xF0, 0x1C, 0x11, 0xD4,
+ 0xF0, 0x1D, 0x11, 0xD5, 0xE4, 0x00, 0x11, 0xD8,
+ 0x80, 0x27, 0x80, 0xE0, 0xF4, 0x00, 0x11, 0xD6,
+ 0xF4, 0x20, 0x11, 0xD7, 0x84, 0x84, 0x00, 0xF8,
+ 0xF4, 0x1C, 0x11, 0xD9, 0x84, 0x4B, 0x03, 0x37,
+ 0xF4, 0x1D, 0x11, 0xDA, 0x84, 0x49, 0x03, 0x5F,
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x0B);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x80, 0x67, 0x80, 0xF8, 0xE0, 0x00, 0x11, 0xDB,
+ 0x84, 0x82, 0x21, 0x00, 0x84, 0x82, 0x20, 0xE0,
+ 0xF0, 0x1C, 0x31, 0xDC, 0xF0, 0x1C, 0x31, 0xDD,
+ 0xF0, 0x1C, 0x31, 0xDE, 0xF0, 0x1D, 0x31, 0xDF,
+ 0xE4, 0x00, 0x11, 0xE2, 0x80, 0x27, 0x80, 0xE1,
+ 0xF4, 0x00, 0x11, 0xE0, 0xF4, 0x1F, 0x31, 0xE1,
+ 0xF4, 0x1C, 0x31, 0xE3, 0xF4, 0x1D, 0x31, 0xE4,
+ 0x84, 0x51, 0x03, 0x60, 0x80, 0x67, 0x80, 0xF9,
+ 0xE4, 0x00, 0x00, 0x81, 0xE0, 0x80, 0x51, 0xE5,
+ 0x84, 0x82, 0x40, 0xE0, 0xF0, 0x1C, 0x51, 0xE6,
+ 0xF0, 0x1C, 0x51, 0xE7, 0xF0, 0x1C, 0x51, 0xE8,
+ 0x88, 0x47, 0x00, 0x80, 0xF0, 0x1D, 0x51, 0xE9,
+ 0xE4, 0x00, 0x11, 0xEC, 0x80, 0x27, 0x80, 0xE2,
+ 0xF4, 0x00, 0x11, 0xEA, 0xF4, 0x1F, 0x51, 0xEB,
+ 0xF4, 0x1C, 0x51, 0xED, 0xF4, 0x1D, 0x51, 0xEE,
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x0C);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x02, 0x58, 0x02, 0xBC, 0x08, 0xFC, 0x0D, 0x18,
+ 0x80, 0x67, 0x80, 0xFA, 0x02, 0xD3, 0x00, 0x10,
+ 0x10, 0x00, 0x18, 0x03, 0x84, 0x43, 0x03, 0x2F,
+ 0x84, 0x4B, 0x03, 0x5F, 0x84, 0x53, 0x03, 0x60,
+ 0x84, 0x41, 0x03, 0x47, 0x84, 0x51, 0x03, 0x3F,
+ 0x84, 0xC1, 0x02, 0xBD, 0x00, 0xFC, 0x00, 0x00,
+ 0x02, 0x48, 0x02, 0xBD, 0x02, 0x11, 0xFF, 0xF8,
+ 0x86, 0xD1, 0x01, 0xEF, 0x86, 0xC9, 0x01, 0xF0,
+ 0x86, 0x1D, 0x01, 0xF1, 0xE0, 0x10, 0x11, 0xC7,
+ 0x86, 0xA1, 0x01, 0xC8, 0x84, 0xC2, 0x00, 0xE0,
+ 0xF0, 0x1C, 0x00, 0x00, 0xF0, 0x1C, 0x11, 0xC9,
+ 0xF0, 0x1C, 0x11, 0xCA, 0xF0, 0x1D, 0x11, 0xCB,
+ 0xE4, 0x00, 0x11, 0xCE, 0x80, 0x27, 0x80, 0xE0,
+ 0x84, 0x1E, 0x04, 0x02, 0x02, 0x78, 0x00, 0x02,
+ 0xF4, 0x00, 0x11, 0xCC, 0xF4, 0x1F, 0x11, 0xCD,
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x0D);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0xF4, 0x1C, 0x11, 0xCF, 0xF4, 0x1D, 0x11, 0xD0,
+ 0x86, 0xA1, 0x01, 0xD1, 0x80, 0x67, 0x80, 0xF8,
+ 0x84, 0x43, 0x03, 0x47, 0x84, 0x59, 0x03, 0x62,
+ 0x8F, 0xA0, 0x00, 0x00, 0x02, 0xDB, 0x00, 0x10,
+ 0x0C, 0x1C, 0x51, 0x6C, 0x08, 0x64, 0x66, 0x71,
+ 0x0D, 0x00, 0x10, 0x30, 0x08, 0x44, 0x46, 0x51,
+ 0x84, 0xCA, 0x01, 0x00, 0xE0, 0x10, 0x20, 0x00,
+ 0xF0, 0x1C, 0x51, 0xD2, 0xF0, 0x1C, 0x51, 0xD3,
+ 0xF0, 0x1C, 0x51, 0xD4, 0xF0, 0x1D, 0x51, 0xD5,
+ 0xE4, 0x00, 0x11, 0xD8, 0x80, 0x27, 0x80, 0xE2,
+ 0xF4, 0x00, 0x11, 0xD6, 0xF4, 0x1F, 0x51, 0xD7,
+ 0xF4, 0x1C, 0x51, 0xD9, 0xF4, 0x1D, 0x51, 0xDA,
+ 0x84, 0x41, 0x03, 0x61, 0x80, 0x67, 0x80, 0xFA,
+ 0xE0, 0x00, 0x11, 0xDB, 0x84, 0x82, 0x01, 0x00,
+ 0x84, 0x82, 0x00, 0xE0, 0xF0, 0x1C, 0x11, 0xDC,
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x0E);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0xF0, 0x1C, 0x11, 0xDD, 0xF0, 0x1C, 0x11, 0xDE,
+ 0xF0, 0x1D, 0x11, 0xDF, 0xE4, 0x00, 0x11, 0xE2,
+ 0x80, 0x27, 0x80, 0xE0, 0xF4, 0x00, 0x11, 0xE0,
+ 0xF4, 0x1F, 0x11, 0xE1, 0xF4, 0x1C, 0x11, 0xE3,
+ 0x02, 0x83, 0x00, 0x18, 0x84, 0xC2, 0x60, 0xE0,
+ 0x86, 0xC1, 0x01, 0xE4, 0xE0, 0x00, 0x11, 0xE5,
+ 0xF4, 0x1D, 0x00, 0x80, 0x84, 0xA0, 0x04, 0x02,
+ 0x80, 0x67, 0x80, 0xF8, 0xE4, 0x00, 0x00, 0x00,
+ 0xF0, 0x1C, 0x71, 0xE6, 0xF0, 0x1C, 0x71, 0xE7,
+ 0xF0, 0x1C, 0x71, 0xE8, 0xF0, 0x1D, 0x71, 0xE9,
+ 0x86, 0xA1, 0x01, 0xEC, 0x88, 0x47, 0x00, 0x80,
+ 0xE4, 0x00, 0x00, 0x00, 0x80, 0x27, 0x80, 0xE3,
+ 0xF4, 0x00, 0x11, 0xEA, 0xF4, 0x1F, 0x71, 0xEB,
+ 0xF4, 0x1C, 0x71, 0xED, 0xF4, 0x1D, 0x71, 0xEE,
+ 0x86, 0xC9, 0x01, 0xA1, 0x80, 0x67, 0x80, 0xFB,
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x0F);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x84, 0x5B, 0x03, 0x62, 0x08, 0x00, 0x10, 0x20,
+ 0x02, 0xD3, 0x00, 0x10, 0x84, 0x53, 0x03, 0x3F,
+ 0x84, 0x43, 0x03, 0x61, 0x08, 0xFC, 0x0D, 0x18,
+ 0x02, 0x50, 0x02, 0xBD, 0x00, 0x26, 0x21, 0xB7,
+ 0x10, 0x00, 0x18, 0x01, 0x86, 0xC1, 0x01, 0xC6,
+ 0x84, 0xC3, 0x03, 0x63, 0x02, 0xC0, 0x03, 0x63,
+ 0x84, 0x52, 0x04, 0x00, 0x02, 0x48, 0x02, 0xBC,
+ 0x84, 0xC2, 0x04, 0x01, 0x00, 0xFF, 0x10, 0xB0,
+ 0x8C, 0xFF, 0x02, 0xBC, 0x00, 0xFE, 0x21, 0xDA,
+ 0x00, 0xFC, 0x00, 0x00, 0x86, 0xC9, 0x01, 0xA0,
+ 0x84, 0x81, 0x02, 0xBC, 0x02, 0xA3, 0x00, 0x10,
+ 0xE4, 0x00, 0x00, 0x00, 0x84, 0x81, 0x02, 0xBD,
+ 0x88, 0x47, 0x13, 0x25, 0x02, 0xA3, 0x00, 0x10,
+ 0xE4, 0x00, 0x00, 0x00, 0x88, 0x47, 0x13, 0x26,
+ 0x02, 0x40, 0x03, 0x28, 0x84, 0xC1, 0x03, 0x25,
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x10);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x00, 0xFF, 0x11, 0x4E, 0x00, 0xFC, 0x00, 0x00,
+ 0x02, 0x40, 0x03, 0x29, 0x86, 0xC9, 0x01, 0xA0,
+ 0x84, 0xC1, 0x03, 0x26, 0x00, 0xFF, 0x11, 0x4E,
+ 0x00, 0xFC, 0x00, 0x00, 0x86, 0xC1, 0x01, 0xA2,
+ 0x84, 0xC3, 0x03, 0x2A, 0x02, 0xC0, 0x03, 0x29,
+ 0x02, 0xC8, 0x03, 0x26, 0x02, 0x40, 0x03, 0x28,
+ 0x02, 0x48, 0x03, 0x25, 0x02, 0x50, 0x03, 0x2A,
+ 0x84, 0xC2, 0x04, 0x00, 0x84, 0xCA, 0x04, 0x01,
+ 0x00, 0xFF, 0x21, 0xDF, 0x00, 0xFC, 0x00, 0x00,
+ 0x84, 0xA1, 0x02, 0xBC, 0xE6, 0x64, 0xA0, 0x00,
+ 0x88, 0x47, 0x12, 0xBC, 0x84, 0xA1, 0x03, 0x26,
+ 0xE6, 0x57, 0xA0, 0x00, 0x88, 0x47, 0x12, 0xBD,
+ 0x84, 0x00, 0x04, 0x03, 0x00, 0xFC, 0x00, 0x00,
+ 0x02, 0xC0, 0x00, 0x00, 0x00, 0xFC, 0x50, 0x00,
+ 0x8F, 0x00, 0x00, 0x08, 0x8F, 0x00, 0xFF, 0xFF,
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x11);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x84, 0x58, 0x04, 0x01, 0x84, 0xA1, 0x03, 0x68,
+ 0x84, 0xC1, 0x03, 0x67, 0xE0, 0xE0, 0x00, 0x00,
+ 0x02, 0xCA, 0x60, 0x00, 0x40, 0x40, 0xA0, 0x00,
+ 0x80, 0x00, 0xC0, 0x82, 0x08, 0xFC, 0x48, 0x3A,
+ 0x08, 0xFC, 0x38, 0x52, 0x84, 0x58, 0x04, 0x02,
+ 0xE0, 0x10, 0x40, 0x00, 0x84, 0xA0, 0x41, 0x00,
+ 0x40, 0x47, 0x20, 0x00, 0x02, 0xD3, 0x00, 0x10,
+ 0x84, 0xA2, 0x04, 0x00, 0x84, 0xA1, 0x03, 0x66,
+ 0xE4, 0x20, 0x00, 0x00, 0x08, 0x00, 0x28, 0x42,
+ 0x45, 0x40, 0xA0, 0x00, 0x80, 0x40, 0xC0, 0x83,
+ 0x08, 0xFC, 0x68, 0x3B, 0x08, 0xFC, 0x38, 0x71,
+ 0x84, 0xD3, 0x03, 0x68, 0xE4, 0x10, 0x20, 0x00,
+ 0x84, 0xA0, 0x04, 0x00, 0x45, 0x47, 0x20, 0x00,
+ 0x02, 0xD3, 0x00, 0x10, 0x80, 0x40, 0xC0, 0x81,
+ 0x0D, 0x00, 0x10, 0x20, 0x08, 0x00, 0x28, 0x42,
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x12);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x84, 0xD3, 0x03, 0x66, 0x86, 0xD1, 0x01, 0x9C,
+ 0x86, 0xD9, 0x01, 0x9B, 0x08, 0xFC, 0x3C, 0x11,
+ 0x08, 0x44, 0x46, 0x53, 0x00, 0xFC, 0x00, 0x00,
+ 0x02, 0x83, 0x00, 0x19, 0x02, 0xA3, 0x00, 0x1B,
+ 0x80, 0x00, 0xC0, 0x83, 0x84, 0xC9, 0x03, 0x69,
+ 0x0D, 0x00, 0x10, 0x68, 0x08, 0xFC, 0x7C, 0x33,
+ 0xE0, 0x00, 0x00, 0x00, 0x02, 0x83, 0x00, 0x1B,
+ 0x86, 0xD9, 0x01, 0x9B, 0x08, 0x44, 0x46, 0x53,
+ 0x80, 0x07, 0x00, 0x82, 0xE0, 0x00, 0x00, 0x83,
+ 0x80, 0x07, 0x00, 0x83, 0x0C, 0x60, 0x0C, 0x10,
+ 0x0C, 0xE0, 0x0C, 0x39, 0x84, 0xC3, 0x03, 0x67,
+ 0x84, 0xCB, 0x03, 0x69, 0x00, 0xFC, 0x50, 0x00,
+ 0x8F, 0x00, 0x00, 0x01
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_book(dev, 0x78);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x18);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00
+ };
+ res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_book(dev, 0x78);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x1C);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x03, 0x30, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ };
+ res = tas5825m_write_block_at(dev, 0x0C, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_book(dev, 0x78);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x1C);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x00, 0x00, 0x03, 0x38, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ };
+ res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_book(dev, 0x78);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x1C);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x00, 0x00, 0x03, 0x40, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ };
+ res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_book(dev, 0x78);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x1C);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x00, 0x00, 0x03, 0x48
+ };
+ res = tas5825m_write_block_at(dev, 0x7C, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x1D);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_book(dev, 0x78);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x1D);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x00, 0x00, 0x03, 0x50, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ };
+ res = tas5825m_write_block_at(dev, 0x24, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_book(dev, 0x78);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x1D);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x00, 0x00, 0x03, 0x58, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ };
+ res = tas5825m_write_block_at(dev, 0x44, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_book(dev, 0x78);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x1D);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x00, 0x00, 0x03, 0x70, 0x00, 0x00, 0x03, 0x80,
+ 0x00, 0x00, 0x03, 0x88, 0x00, 0x00, 0x03, 0x90,
+ 0x00, 0x00, 0x00, 0x00
+ };
+ res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_book(dev, 0x78);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x1D);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x00, 0x00, 0x03, 0x98, 0x00, 0x00, 0x03, 0xA0,
+ };
+ res = tas5825m_write_block_at(dev, 0x78, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x1E);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_book(dev, 0x78);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x1E);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x00, 0x00, 0x03, 0xA8, 0x00, 0x00, 0x03, 0xB0,
+ 0x00, 0x00, 0x03, 0xB8, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00
+ };
+ res = tas5825m_write_block_at(dev, 0x4C, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_book(dev, 0x78);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x1E);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x00, 0x00, 0x03, 0xC0
+ };
+ res = tas5825m_write_block_at(dev, 0x68, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_book(dev, 0x8C);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x0E);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x00, 0x20, 0xC4, 0x9C, 0x00, 0x20, 0xC4, 0x9C,
+ 0x02, 0xDE, 0xAD, 0x00, 0x74, 0x01, 0x39, 0x01,
+ 0x00, 0x20, 0xC4, 0x9B, 0x00, 0xA7, 0x26, 0x4A,
+ 0x00, 0x00, 0x00, 0x00, 0x7F, 0xFF, 0xFF, 0xFF,
+ 0x7F, 0xFF, 0xFF, 0xFF
+ };
+ res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x0F);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x7F, 0xFF, 0xFF, 0xFF, 0x7F, 0xFF, 0xFF, 0xFF,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0xE7, 0x00, 0x00, 0x00,
+ 0xFE, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_book(dev, 0x8C);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x0F);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00
+ };
+ res = tas5825m_write_block_at(dev, 0x2C, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_book(dev, 0x8C);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x0F);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+ };
+ res = tas5825m_write_block_at(dev, 0x68, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x10);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x7F, 0xFF, 0xFF, 0xFF, 0x00, 0x62, 0x48, 0x8E,
+ 0xFF, 0x83, 0xE9, 0x30, 0x00, 0x2E, 0x18, 0x72,
+ 0x0F, 0x40, 0xAE, 0x1F, 0xF8, 0x9A, 0x41, 0xD5,
+ 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x07, 0xFF, 0xFF, 0xFF,
+ 0xF0, 0xBF, 0x51, 0xE1, 0x07, 0x65, 0xBE, 0x2B,
+ 0x0A, 0x19, 0xBB, 0x39, 0xFC, 0x3F, 0x79, 0xE8,
+ 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x5C, 0x79, 0x55,
+ 0x00, 0xB8, 0xF2, 0xAB, 0x00, 0x5C, 0x79, 0x55,
+ 0x0D, 0x98, 0xCC, 0x51, 0xFA, 0x16, 0x2B, 0x95,
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x11);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x00, 0x5C, 0x79, 0x55, 0x00, 0xB8, 0xF2, 0xAB,
+ 0x00, 0x5C, 0x79, 0x55, 0x0D, 0x98, 0xCC, 0x51,
+ 0xFA, 0x16, 0x2B, 0x95, 0x06, 0xE0, 0xA8, 0x2F,
+ 0xF2, 0x3E, 0xAF, 0xA2, 0x06, 0xE0, 0xA8, 0x2F,
+ 0x0D, 0x98, 0xCC, 0x51, 0xFA, 0x16, 0x2B, 0x95,
+ 0x06, 0xE0, 0xA8, 0x2F, 0xF2, 0x3E, 0xAF, 0xA2,
+ 0x06, 0xE0, 0xA8, 0x2F, 0x0D, 0x98, 0xCC, 0x51,
+ 0xFA, 0x16, 0x2B, 0x95, 0x02, 0x4D, 0x99, 0x99,
+ 0xFD, 0xB2, 0x66, 0x67, 0x00, 0x80, 0x00, 0x00,
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_book(dev, 0x00);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_write_at(dev, 0x40, 0x00);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_book(dev, 0x00);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_write_at(dev, 0x7D, 0x11);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_write_at(dev, 0x7E, 0xFF);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x01);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_write_at(dev, 0x51, 0x05);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x02);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_write_at(dev, 0x19, 0xDF);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_book(dev, 0x00);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_write_at(dev, 0x46, 0x11);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x00);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_write_at(dev, 0x02, 0x00);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_write_at(dev, 0x53, 0x00);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_write_at(dev, 0x54, 0x00);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_book(dev, 0x00);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_write_at(dev, 0x03, 0x02);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x00);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x00);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x00);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_book(dev, 0x8C);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x0B);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+ };
+ res = tas5825m_write_block_at(dev, 0x28, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ {
+ const uint8_t values[] = {
+ 0x00, 0x20, 0xC4, 0x9C
+ };
+ res = tas5825m_write_block_at(dev, 0x50, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ {
+ const uint8_t values[] = {
+ 0x7F, 0xFF, 0xFF, 0xFF
+ };
+ res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_book(dev, 0x8C);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x01);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0xC0, 0x00, 0x00, 0x00, 0x00, 0x71, 0x94, 0x9A,
+ };
+ res = tas5825m_write_block_at(dev, 0x28, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x0A);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00,
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00
+ };
+ res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x0B);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x39, 0x2C, 0xEE,
+ 0x00, 0x39, 0x2C, 0xEE, 0x00, 0x80, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x80, 0x00, 0x00
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ {
+ const uint8_t values[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x57, 0x62, 0x00, 0x00, 0x00, 0x00,
+ };
+ res = tas5825m_write_block_at(dev, 0x28, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ {
+ const uint8_t values[] = {
+ 0x02, 0x96, 0x7E, 0x0C, 0x00, 0x01, 0xB4, 0xE8,
+ };
+ res = tas5825m_write_block_at(dev, 0x48, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ {
+ const uint8_t values[] = {
+ 0x7D, 0x69, 0x81, 0xF4, 0x00, 0x00, 0x2B, 0xB1,
+ };
+ res = tas5825m_write_block_at(dev, 0x54, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x0E);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x00, 0x22, 0x1D, 0x95, 0x00, 0x03, 0x69, 0xC5,
+ 0x00, 0x03, 0x69, 0xC5, 0x1C, 0x1B, 0xF0, 0x41,
+ 0x04, 0x0C, 0x37, 0x14, 0x00, 0x03, 0x69, 0xC5,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x5C, 0x42, 0xC9,
+ 0x00, 0xD0, 0xC9, 0x04
+ };
+ res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x0F);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x00, 0x8B, 0x56, 0xA0, 0x00, 0x2E, 0x83, 0x1A,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0xFF, 0xA0, 0x00, 0x00, 0xF7, 0x5C, 0x28, 0xF6,
+ 0xFB, 0x44, 0x29, 0x20, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x10);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x00, 0xCE, 0xC0, 0x8A
+ };
+ res = tas5825m_write_block_at(dev, 0x18, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x11);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x01, 0xE2, 0x0E, 0x98, 0xFE, 0x1D, 0xF1, 0x68,
+ 0x01, 0x00, 0x00, 0x00
+ };
+ res = tas5825m_write_block_at(dev, 0x44, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x07);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x00, 0x80, 0x00, 0x00
+ };
+ res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ {
+ const uint8_t values[] = {
+ 0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00,
+ };
+ res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_book(dev, 0xAA);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_page(dev, 0x01);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ };
+ res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x02);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x03);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x07, 0xD2, 0xC1, 0x31,
+ 0xF0, 0x5A, 0x7D, 0x9F, 0x07, 0xD2, 0xC1, 0x31,
+ 0x0F, 0xA4, 0xFB, 0xF0, 0xF8, 0x59, 0xF7, 0x2E,
+ 0x07, 0xD9, 0x78, 0x8E, 0xF0, 0x4D, 0x0E, 0xE5,
+ 0x07, 0xD9, 0x78, 0x8E, 0x0F, 0xB2, 0x6A, 0x37,
+ 0xF8, 0x4C, 0x88, 0x00, 0x07, 0xE6, 0x02, 0x7A,
+ 0xF0, 0x33, 0xFB, 0x0B, 0x07, 0xE6, 0x02, 0x7A,
+ 0x0F, 0xCB, 0x7D, 0x39, 0xF8, 0x33, 0x73, 0x4F,
+ 0x07, 0xD0, 0x20, 0x0B, 0xF0, 0x8B, 0x82, 0x11,
+ 0x07, 0xA8, 0xF6, 0xDE, 0x0F, 0x74, 0x7D, 0xEF,
+ 0xF8, 0x86, 0xE9, 0x17, 0x08, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x04);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x05);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x07, 0xD2, 0xC1, 0x31, 0xF0, 0x5A, 0x7D, 0x9F,
+ 0x07, 0xD2, 0xC1, 0x31, 0x0F, 0xA4, 0xFB, 0xF0,
+ 0xF8, 0x59, 0xF7, 0x2E, 0x07, 0xD9, 0x78, 0x8E,
+ 0xF0, 0x4D, 0x0E, 0xE5, 0x07, 0xD9, 0x78, 0x8E,
+ 0x0F, 0xB2, 0x6A, 0x37, 0xF8, 0x4C, 0x88, 0x00,
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x06);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x07, 0xE6, 0x02, 0x7A, 0xF0, 0x33, 0xFB, 0x0B,
+ 0x07, 0xE6, 0x02, 0x7A, 0x0F, 0xCB, 0x7D, 0x39,
+ 0xF8, 0x33, 0x73, 0x4F, 0x07, 0xD0, 0x20, 0x0B,
+ 0xF0, 0x8B, 0x82, 0x11, 0x07, 0xA8, 0xF6, 0xDE,
+ 0x0F, 0x74, 0x7D, 0xEF, 0xF8, 0x86, 0xE9, 0x17,
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x0F);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x3D, 0x48, 0x3E,
+ 0xF0, 0x15, 0x1E, 0x41, 0x07, 0xB2, 0x55, 0xB4,
+ 0x0F, 0xEC, 0xB6, 0xFF, 0xF8, 0x12, 0x37, 0x4E,
+ 0x08, 0x00, 0x00, 0x00
+ };
+ res = tas5825m_write_block_at(dev, 0x2C, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x10);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ {
+ const uint8_t values[] = {
+ 0x00, 0x91, 0x1E, 0x24, 0xFF, 0x05, 0x01, 0xCF,
+ 0x00, 0x6E, 0x95, 0x34, 0x0F, 0xD3, 0x31, 0xB6,
+ 0xF8, 0x28, 0x19, 0x23, 0x08, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x38, 0x73, 0x61, 0xE0, 0x90, 0x55, 0x66, 0x81,
+ 0x37, 0x58, 0x6F, 0x94, 0x0D, 0xD6, 0x2E, 0xBA,
+ 0xF9, 0xE7, 0x61, 0x5B, 0x08, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0xEC, 0x38, 0x00, 0x03, 0xD8, 0x70,
+ 0x00, 0x01, 0xEC, 0x38, 0x0F, 0x4A, 0xB5, 0x41,
+ 0xF8, 0xAD, 0x99, 0xDE
+ };
+ res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_page(dev, 0x11);
+ if (res < 0)
+ return res;
+
+ {
+ const uint8_t values[] = {
+ 0x00, 0x01, 0xEC, 0x38, 0x00, 0x03, 0xD8, 0x70,
+ 0x00, 0x01, 0xEC, 0x38, 0x0F, 0x4A, 0xB5, 0x41,
+ 0xF8, 0xAD, 0x99, 0xDE, 0x07, 0xA7, 0x46, 0xD9,
+ 0xF0, 0xB1, 0x72, 0x4F, 0x07, 0xA7, 0x46, 0xD9,
+ 0x0F, 0x4A, 0xB5, 0x41, 0xF8, 0xAD, 0x99, 0xDE,
+ 0x07, 0xA7, 0x46, 0xD9, 0xF0, 0xB1, 0x72, 0x4F,
+ 0x07, 0xA7, 0x46, 0xD9, 0x0F, 0x4A, 0xB5, 0x41,
+ 0xF8, 0xAD, 0x99, 0xDE
+ };
+ res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+ if (res < 0)
+ return res;
+ }
+
+ res = tas5825m_set_book(dev, 0x00);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_write_at(dev, 0x30, 0x00);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_write_at(dev, 0x60, 0x02);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_write_at(dev, 0x62, 0x09);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_write_at(dev, 0x4C, 0x30);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_write_at(dev, 0x03, 0x03);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_set_book(dev, 0x00);
+ if (res < 0)
+ return res;
+
+ res = tas5825m_write_at(dev, 0x78, 0x80);
+ if (res < 0)
+ return res;
+
+ return 0;
+}