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-rw-r--r--src/mainboard/supermicro/h8dme/romstage.c19
-rw-r--r--src/mainboard/supermicro/h8dmr/romstage.c35
-rw-r--r--src/mainboard/supermicro/h8dmr_fam10/romstage.c17
-rw-r--r--src/mainboard/supermicro/h8qme_fam10/romstage.c16
-rw-r--r--src/mainboard/supermicro/x6dai_g/romstage.c11
-rw-r--r--src/mainboard/supermicro/x6dhe_g/romstage.c19
-rw-r--r--src/mainboard/supermicro/x6dhe_g2/romstage.c19
-rw-r--r--src/mainboard/supermicro/x6dhr_ig/romstage.c11
-rw-r--r--src/mainboard/supermicro/x6dhr_ig2/romstage.c19
9 files changed, 36 insertions, 130 deletions
diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index de3bc2c35f..ac3ee68857 100644
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -49,9 +49,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void dump_smbus_registers(void)
{
@@ -183,25 +181,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
sio_setup();
-
- /* Setup the mcp55 */
mcp55_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
pnp_enter_ext_func_mode(SERIAL_DEV);
pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
@@ -243,7 +235,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
-
{
msr_t msr;
msr = rdmsr(0xc0010042);
@@ -251,15 +242,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
print_debug("\n");
-
}
-
enable_fid_change();
-
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
init_fidvid_bsp(bsp_apicid);
-
// show final fid and vid
{
msr_t msr;
@@ -268,7 +254,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
print_debug("\n");
-
}
#endif
diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index 573f69eb30..d41067a2d2 100644
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -52,14 +52,8 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -85,6 +79,7 @@ static void sio_setup(void)
{
uint32_t dword;
uint8_t byte;
+
enable_smbus();
// smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
@@ -105,35 +100,29 @@ static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
- // Node 0
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
- // Node 1
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
+ // Node 0
+ DIMM0, DIMM2, 0, 0,
+ DIMM1, DIMM3, 0, 0,
+ // Node 1
+ DIMM4, DIMM6, 0, 0,
+ DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
sio_setup();
-
- /* Setup the mcp55 */
mcp55_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
pnp_enter_ext_func_mode(SERIAL_DEV);
pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
@@ -177,13 +166,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid %08x, %08x\n", msr.hi, msr.lo);
}
-
enable_fid_change();
-
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
init_fidvid_bsp(bsp_apicid);
-
// show final fid and vid
{
msr_t msr;
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index 174a6cefcf..61551a718c 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -51,10 +51,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -111,30 +108,22 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
- u32 bsp_apicid = 0;
- u32 val;
- u32 wants_reset;
+ u32 bsp_apicid = 0, val, wants_reset;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
-
sio_setup();
-
- /* Setup the mcp55 */
mcp55_enable_rom();
}
post_code(0x30);
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
post_code(0x32);
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index e77b139745..dac57f977b 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -117,6 +117,7 @@ static const u8 spd_addr[] = {
#define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1)
#define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2)
#define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3)
+
static void write_GPIO(void)
{
pnp_enter_ext_func_mode(GPIO1_DEV);
@@ -156,31 +157,24 @@ static void write_GPIO(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
- struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
- u32 bsp_apicid = 0;
- u32 val;
- u32 wants_reset;
+ struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+ u32 bsp_apicid = 0, val, wants_reset;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
-
sio_setup();
-
- /* Setup the mcp55 */
mcp55_enable_rom();
}
post_code(0x30);
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
post_code(0x32);
diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c
index b95bbc9ebf..2873d8af99 100644
--- a/src/mainboard/supermicro/x6dai_g/romstage.c
+++ b/src/mainboard/supermicro/x6dai_g/romstage.c
@@ -60,9 +60,8 @@ static void main(unsigned long bist)
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
- if (memory_initialized()) {
+ if (memory_initialized())
skip_romstage();
- }
}
/* Setup the console */
@@ -77,16 +76,13 @@ static void main(unsigned long bist)
/* config LPC decode for flash memory access */
device_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
- if (dev == PCI_DEV_INVALID) {
+ if (dev == PCI_DEV_INVALID)
die("Missing 6300ESB?");
- }
pci_write_config32(dev, 0xe8, 0x00000000);
pci_write_config8(dev, 0xf0, 0x00);
#if 0
display_cpuid_update_microcode();
-#endif
-#if 0
print_pci_devices();
#endif
#if 1
@@ -94,9 +90,8 @@ static void main(unsigned long bist)
#endif
#if 0
int i;
- for(i = 0; i < 1; i++) {
+ for(i = 0; i < 1; i++)
dump_spd_registers();
- }
#endif
disable_watchdogs();
sdram_initialize(ARRAY_SIZE(mch), mch);
diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c
index 995234b808..c5107d9fc1 100644
--- a/src/mainboard/supermicro/x6dhe_g/romstage.c
+++ b/src/mainboard/supermicro/x6dhe_g/romstage.c
@@ -49,12 +49,6 @@ static void main(unsigned long bist)
static const struct mem_controller mch[] = {
{
.node_id = 0,
- /*
- .f0 = PCI_DEV(0, 0x00, 0),
- .f1 = PCI_DEV(0, 0x00, 1),
- .f2 = PCI_DEV(0, 0x00, 2),
- .f3 = PCI_DEV(0, 0x00, 3),
- */
.channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, },
.channel1 = {DIMM4, DIMM5, DIMM6, DIMM7, },
}
@@ -63,9 +57,8 @@ static void main(unsigned long bist)
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
- if (memory_initialized()) {
+ if (memory_initialized())
skip_romstage();
- }
}
/* Setup the console */
@@ -83,16 +76,13 @@ static void main(unsigned long bist)
/* config LPC decode for flash memory access */
device_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
- if (dev == PCI_DEV_INVALID) {
+ if (dev == PCI_DEV_INVALID)
die("Missing esb6300?");
- }
pci_write_config32(dev, 0xe8, 0x00000000);
pci_write_config8(dev, 0xf0, 0x00);
#if 0
display_cpuid_update_microcode();
-#endif
-#if 0
print_pci_devices();
#endif
#if 1
@@ -101,9 +91,8 @@ static void main(unsigned long bist)
#if 0
// dump_spd_registers(&cpu[0]);
int i;
- for(i = 0; i < 1; i++) {
+ for(i = 0; i < 1; i++)
dump_spd_registers();
- }
#endif
disable_watchdogs();
// dump_ipmi_registers();
@@ -111,8 +100,6 @@ static void main(unsigned long bist)
sdram_initialize(ARRAY_SIZE(mch), mch);
#if 0
dump_pci_devices();
-#endif
-#if 0
dump_pci_device(PCI_DEV(0, 0x00, 0));
dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
diff --git a/src/mainboard/supermicro/x6dhe_g2/romstage.c b/src/mainboard/supermicro/x6dhe_g2/romstage.c
index eef04d4f28..af042477d2 100644
--- a/src/mainboard/supermicro/x6dhe_g2/romstage.c
+++ b/src/mainboard/supermicro/x6dhe_g2/romstage.c
@@ -47,13 +47,7 @@ static void main(unsigned long bist)
static const struct mem_controller mch[] = {
{
.node_id = 0,
- /*
- .f0 = PCI_DEV(0, 0x00, 0),
- .f1 = PCI_DEV(0, 0x00, 1),
- .f2 = PCI_DEV(0, 0x00, 2),
- .f3 = PCI_DEV(0, 0x00, 3),
- */
- .channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
+ .channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
.channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
}
};
@@ -61,9 +55,8 @@ static void main(unsigned long bist)
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
- if (memory_initialized()) {
+ if (memory_initialized())
skip_romstage();
- }
}
/* Setup the console */
@@ -81,16 +74,13 @@ static void main(unsigned long bist)
/* config LPC decode for flash memory access */
device_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
- if (dev == PCI_DEV_INVALID) {
+ if (dev == PCI_DEV_INVALID)
die("Missing ich5r?");
- }
pci_write_config32(dev, 0xe8, 0x00000000);
pci_write_config8(dev, 0xf0, 0x00);
#if 0
display_cpuid_update_microcode();
-#endif
-#if 0
print_pci_devices();
#endif
#if 1
@@ -99,9 +89,8 @@ static void main(unsigned long bist)
#if 0
// dump_spd_registers(&cpu[0]);
int i;
- for(i = 0; i < 1; i++) {
+ for(i = 0; i < 1; i++)
dump_spd_registers();
- }
#endif
disable_watchdogs();
// dump_ipmi_registers();
diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c
index 89429466cf..839be04184 100644
--- a/src/mainboard/supermicro/x6dhr_ig/romstage.c
+++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c
@@ -62,9 +62,8 @@ static void main(unsigned long bist)
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
- if (memory_initialized()) {
+ if (memory_initialized())
skip_romstage();
- }
}
/* Setup the console */
@@ -82,16 +81,13 @@ static void main(unsigned long bist)
/* config LPC decode for flash memory access */
device_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
- if (dev == PCI_DEV_INVALID) {
+ if (dev == PCI_DEV_INVALID)
die("Missing ich5?");
- }
pci_write_config32(dev, 0xe8, 0x00000000);
pci_write_config8(dev, 0xf0, 0x00);
#if 0
display_cpuid_update_microcode();
-#endif
-#if 0
print_pci_devices();
#endif
#if 1
@@ -100,9 +96,8 @@ static void main(unsigned long bist)
#if 0
// dump_spd_registers(&cpu[0]);
int i;
- for(i = 0; i < 1; i++) {
+ for(i = 0; i < 1; i++)
dump_spd_registers();
- }
#endif
disable_watchdogs();
// dump_ipmi_registers();
diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c
index ba6ba914be..76c94b228f 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c
+++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c
@@ -48,12 +48,6 @@ static void main(unsigned long bist)
static const struct mem_controller mch[] = {
{
.node_id = 0,
- /*
- .f0 = PCI_DEV(0, 0x00, 0),
- .f1 = PCI_DEV(0, 0x00, 1),
- .f2 = PCI_DEV(0, 0x00, 2),
- .f3 = PCI_DEV(0, 0x00, 3),
- */
.channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
.channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
}
@@ -62,9 +56,8 @@ static void main(unsigned long bist)
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
- if (memory_initialized()) {
+ if (memory_initialized())
skip_romstage();
- }
}
/* Setup the console */
@@ -82,16 +75,13 @@ static void main(unsigned long bist)
/* config LPC decode for flash memory access */
device_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
- if (dev == PCI_DEV_INVALID) {
+ if (dev == PCI_DEV_INVALID)
die("Missing ich5?");
- }
pci_write_config32(dev, 0xe8, 0x00000000);
pci_write_config8(dev, 0xf0, 0x00);
#if 0
display_cpuid_update_microcode();
-#endif
-#if 0
print_pci_devices();
#endif
#if 1
@@ -100,9 +90,8 @@ static void main(unsigned long bist)
#if 0
// dump_spd_registers(&cpu[0]);
int i;
- for(i = 0; i < 1; i++) {
+ for(i = 0; i < 1; i++)
dump_spd_registers();
- }
#endif
disable_watchdogs();
// dump_ipmi_registers();
@@ -110,8 +99,6 @@ static void main(unsigned long bist)
sdram_initialize(ARRAY_SIZE(mch), mch);
#if 0
dump_pci_devices();
-#endif
-#if 0
dump_pci_device(PCI_DEV(0, 0x00, 0));
dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 08:38:48 +0000