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-rw-r--r--src/mainboard/supermicro/h8qgi/get_bus_conf.c33
-rw-r--r--src/mainboard/supermicro/h8qgi/mptable.c13
-rw-r--r--src/mainboard/supermicro/h8scm/get_bus_conf.c33
-rw-r--r--src/mainboard/supermicro/h8scm/mptable.c13
4 files changed, 2 insertions, 90 deletions
diff --git a/src/mainboard/supermicro/h8qgi/get_bus_conf.c b/src/mainboard/supermicro/h8qgi/get_bus_conf.c
index f604e21fa8..549334e793 100644
--- a/src/mainboard/supermicro/h8qgi/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8qgi/get_bus_conf.c
@@ -31,11 +31,6 @@
* and acpi_tables busnum is default.
*/
u8 bus_sp5100[2];
-u8 bus_sr5650[14];
-
-
-
-u32 sbdn_sr5650;
u32 sbdn_sp5100;
void get_bus_conf(void)
@@ -48,13 +43,8 @@ void get_bus_conf(void)
for (i = 0; i < ARRAY_SIZE(bus_sp5100); i++) {
bus_sp5100[i] = 0;
}
- for (i = 0; i < ARRAY_SIZE(bus_sr5650); i++) {
- bus_sr5650[i] = 0;
- }
-
- bus_sr5650[0] = 0;
- bus_sp5100[0] = bus_sr5650[0];
+ bus_sp5100[0] = 0;
/* sp5100 */
dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, 4));
@@ -62,25 +52,4 @@ void get_bus_conf(void)
if (dev) {
bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
-
- /* sr5650 */
- for (i = 1; i < ARRAY_SIZE(bus_sr5650); i++) {
- dev = dev_find_slot(bus_sr5650[0], PCI_DEVFN(sbdn_sr5650 + i, 0));
- if (dev) {
- bus_sr5650[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-/*
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, i));
- if (dev) {
- bus_sp5100[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-*/
-
-
- /* I/O APICs: APIC ID Version State Address */
-
}
diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c
index 8a248cc70f..754ed549bf 100644
--- a/src/mainboard/supermicro/h8qgi/mptable.c
+++ b/src/mainboard/supermicro/h8qgi/mptable.c
@@ -28,9 +28,7 @@
#include <cpu/x86/lapic.h>
#include <cpu/amd/amdfam10_sysconf.h>
-extern u8 bus_sr5650[14];
extern u8 bus_sp5100[2];
-extern u32 sbdn_sr5650;
extern u32 sbdn_sp5100;
static void *smp_write_config_table(void *v)
@@ -144,17 +142,6 @@ static void *smp_write_config_table(void *v)
/* SATA */
PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
- /* on board NIC & Slot PCIE. */
- /* configuration B doesnt need dev 5,6,7 */
- /*
- * PCI_INT(bus_sr5650[0x5], 0x0, 0x0, 0x11);
- * PCI_INT(bus_sr5650[0x6], 0x0, 0x0, 0x12);
- * PCI_INT(bus_sr5650[0x7], 0x0, 0x0, 0x13);
- */
-
- //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 28); /* dev d */
- //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[13], (((0)<<2)|(1)), apicid_sr5650, 0); /* card behind dev13 */
-
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14);
diff --git a/src/mainboard/supermicro/h8scm/get_bus_conf.c b/src/mainboard/supermicro/h8scm/get_bus_conf.c
index 3cae35a135..28c4bf7924 100644
--- a/src/mainboard/supermicro/h8scm/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8scm/get_bus_conf.c
@@ -31,11 +31,6 @@
* and acpi_tables busnum is default.
*/
u8 bus_sp5100[2];
-u8 bus_sr5650[14];
-
-
-
-u32 sbdn_sr5650;
u32 sbdn_sp5100;
void get_bus_conf(void)
@@ -48,13 +43,8 @@ void get_bus_conf(void)
for (i = 0; i < 0; i++) {
bus_sp5100[i] = 0;
}
- for (i = 0; i < ARRAY_SIZE(bus_sr5650); i++) {
- bus_sr5650[i] = 0;
- }
-
- bus_sr5650[0] = 0;
- bus_sp5100[0] = bus_sr5650[0];
+ bus_sp5100[0] = 0;
/* sp5100 */
dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, 4));
@@ -62,25 +52,4 @@ void get_bus_conf(void)
if (dev) {
bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
-
- /* sr5650 */
- for (i = 1; i < ARRAY_SIZE(bus_sr5650); i++) {
- dev = dev_find_slot(bus_sr5650[0], PCI_DEVFN(sbdn_sr5650 + i, 0));
- if (dev) {
- bus_sr5650[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-/*
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, i));
- if (dev) {
- bus_sp5100[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-*/
-
-
- /* I/O APICs: APIC ID Version State Address */
-
}
diff --git a/src/mainboard/supermicro/h8scm/mptable.c b/src/mainboard/supermicro/h8scm/mptable.c
index 8a248cc70f..754ed549bf 100644
--- a/src/mainboard/supermicro/h8scm/mptable.c
+++ b/src/mainboard/supermicro/h8scm/mptable.c
@@ -28,9 +28,7 @@
#include <cpu/x86/lapic.h>
#include <cpu/amd/amdfam10_sysconf.h>
-extern u8 bus_sr5650[14];
extern u8 bus_sp5100[2];
-extern u32 sbdn_sr5650;
extern u32 sbdn_sp5100;
static void *smp_write_config_table(void *v)
@@ -144,17 +142,6 @@ static void *smp_write_config_table(void *v)
/* SATA */
PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
- /* on board NIC & Slot PCIE. */
- /* configuration B doesnt need dev 5,6,7 */
- /*
- * PCI_INT(bus_sr5650[0x5], 0x0, 0x0, 0x11);
- * PCI_INT(bus_sr5650[0x6], 0x0, 0x0, 0x12);
- * PCI_INT(bus_sr5650[0x7], 0x0, 0x0, 0x13);
- */
-
- //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 28); /* dev d */
- //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[13], (((0)<<2)|(1)), apicid_sr5650, 0); /* card behind dev13 */
-
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 02:35:26 +0000