diff options
Diffstat (limited to 'src/mainboard/supermicro/x7db8/devicetree.cb')
| -rw-r--r-- | src/mainboard/supermicro/x7db8/devicetree.cb | 121 |
1 files changed, 121 insertions, 0 deletions
diff --git a/src/mainboard/supermicro/x7db8/devicetree.cb b/src/mainboard/supermicro/x7db8/devicetree.cb new file mode 100644 index 0000000000..7c90ba25dd --- /dev/null +++ b/src/mainboard/supermicro/x7db8/devicetree.cb @@ -0,0 +1,121 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +chip northbridge/intel/i5000 + + device lapic_cluster 0 on + chip cpu/intel/socket_LGA771 + device lapic 0 on end + end + end + + device pci_domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x15d9 0x2017 + end + + device pci 02.0 on # PCIe bridge + device pci 00.0 on + device pci 00.0 on + device pci 00.0 on end + device pci 02.0 on end + end + device pci 02.0 on + device pci 00.0 on + device pci 02.0 on + device pci 00.0 on end # e1000 #1 + device pci 00.1 on end # e1000 #2 + end + end + device pci 00.1 on end + end + end + device pci 00.1 on end + device pci 00.3 on end + end + + device pci 03.0 on end + device pci 04.0 on end + device pci 05.0 on end + device pci 06.0 on end + device pci 07.0 on end + device pci 10.0 on end # FBD + device pci 10.1 on end # FBD + device pci 10.2 on end # FBD + device pci 11.0 on end # FBD reserved + device pci 13.0 on end # FBD reserved + device pci 15.0 on end # FBD + device pci 16.0 on end # FBD + + chip southbridge/intel/i3100 + register "pirq_a_d" = "0x0b0b0b0b" + register "pirq_e_h" = "0x80808080" + register "sata_ports_implemented" = "0x3f" + + device pci 1c.0 on end # PCIe bridge + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI + device pci 1d.3 on end # USB UHCI + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on + device pci 01.0 on + end + end + + device pci 1f.0 on # PCI-LPC bridge + subsystemid 0x15d9 0x2009 + chip superio/winbond/w83627hf + device pnp 2e.0 off end # FDC + device pnp 2e.1 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Serial Port 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + + device pnp 2e.3 off end + device pnp 2e.5 on # KBC + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + + end + + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # Game port / MIDI + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 on end # GPIO3 + device pnp 2e.a on end # ACPI + device pnp 2e.b off end # HWMON + end + end + device pci 1f.1 off end # IDE + device pci 1f.2 on end # SATA + device pci 1f.3 off end # SMBUS + + end + end +end |