summaryrefslogtreecommitdiff
path: root/src/mainboard/supermicro/x6dhe_g
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard/supermicro/x6dhe_g')
-rw-r--r--src/mainboard/supermicro/x6dhe_g/debug.c64
-rw-r--r--src/mainboard/supermicro/x6dhe_g/devicetree.cb22
-rw-r--r--src/mainboard/supermicro/x6dhe_g/mptable.c6
-rw-r--r--src/mainboard/supermicro/x6dhe_g/romstage.c12
-rw-r--r--src/mainboard/supermicro/x6dhe_g/watchdog.c8
-rw-r--r--src/mainboard/supermicro/x6dhe_g/x6dhe_g_fixups.c4
6 files changed, 58 insertions, 58 deletions
diff --git a/src/mainboard/supermicro/x6dhe_g/debug.c b/src/mainboard/supermicro/x6dhe_g/debug.c
index b4f2a185b3..87c67b5964 100644
--- a/src/mainboard/supermicro/x6dhe_g/debug.c
+++ b/src/mainboard/supermicro/x6dhe_g/debug.c
@@ -5,7 +5,7 @@
static void print_reg(unsigned char index)
{
unsigned char data;
-
+
outb(index, 0x2e);
data = inb(0x2f);
print_debug("0x");
@@ -15,7 +15,7 @@ static void print_reg(unsigned char index)
print_debug("\n");
return;
}
-
+
static void xbus_en(void)
{
/* select the XBUS function in the SIO */
@@ -25,7 +25,7 @@ static void xbus_en(void)
outb(0x01, 0x2f);
return;
}
-
+
static void setup_func(unsigned char func)
{
/* select the function in the SIO */
@@ -43,27 +43,27 @@ static void setup_func(unsigned char func)
print_reg(0x75);
return;
}
-
+
static void siodump(void)
{
int i;
unsigned char data;
-
+
print_debug("\n*** SERVER I/O REGISTERS ***\n");
for (i=0x10; i<=0x2d; i++) {
print_reg((unsigned char)i);
}
-#if 0
+#if 0
print_debug("\n*** XBUS REGISTERS ***\n");
setup_func(0x0f);
for (i=0xf0; i<=0xff; i++) {
print_reg((unsigned char)i);
}
-
+
print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n");
setup_func(0x03);
print_reg(0xf0);
-
+
print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n");
setup_func(0x02);
print_reg(0xf0);
@@ -82,13 +82,13 @@ static void siodump(void)
print_debug("\nGPDI 4: 0x");
print_debug_hex8(data);
print_debug("\n");
-
-#if 0
-
+
+#if 0
+
print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n");
setup_func(0x0a);
print_reg(0xf0);
-
+
print_debug("\n*** FAN CONTROL REGISTERS ***\n");
setup_func(0x09);
print_reg(0xf0);
@@ -103,11 +103,11 @@ static void siodump(void)
print_reg(0xf7);
print_reg(0xfe);
print_reg(0xff);
-
+
print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n");
setup_func(0x14);
print_reg(0xf0);
-#endif
+#endif
return;
}
@@ -124,8 +124,8 @@ static void print_debug_pci_dev(unsigned dev)
static void print_pci_devices(void)
{
device_t dev;
- for(dev = PCI_DEV(0, 0, 0);
- dev <= PCI_DEV(0, 0x1f, 0x7);
+ for(dev = PCI_DEV(0, 0, 0);
+ dev <= PCI_DEV(0, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
uint32_t id;
id = pci_read_config32(dev, PCI_VENDOR_ID);
@@ -144,7 +144,7 @@ static void dump_pci_device(unsigned dev)
int i;
print_debug_pci_dev(dev);
print_debug("\n");
-
+
for(i = 0; i <= 255; i++) {
unsigned char val;
if ((i & 0x0f) == 0) {
@@ -164,19 +164,19 @@ static void dump_bar14(unsigned dev)
{
int i;
unsigned long bar;
-
+
print_debug("BAR 14 Dump\n");
-
+
bar = pci_read_config32(dev, 0x14);
for(i = 0; i <= 0x300; i+=4) {
-#if 0
+#if 0
unsigned char val;
if ((i & 0x0f) == 0) {
print_debug_hex8(i);
print_debug_char(':');
}
val = pci_read_config8(dev, i);
-#endif
+#endif
if((i%4)==0) {
print_debug("\n");
print_debug_hex16(i);
@@ -191,8 +191,8 @@ static void dump_bar14(unsigned dev)
static void dump_pci_devices(void)
{
device_t dev;
- for(dev = PCI_DEV(0, 0, 0);
- dev <= PCI_DEV(0, 0x1f, 0x7);
+ for(dev = PCI_DEV(0, 0, 0);
+ dev <= PCI_DEV(0, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
uint32_t id;
id = pci_read_config32(dev, PCI_VENDOR_ID);
@@ -215,8 +215,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
device = ctrl->channel0[i];
if (device) {
int j;
- print_debug("dimm: ");
- print_debug_hex8(i);
+ print_debug("dimm: ");
+ print_debug_hex8(i);
print_debug(".0: ");
print_debug_hex8(device);
for(j = 0; j < 256; j++) {
@@ -241,8 +241,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
device = ctrl->channel1[i];
if (device) {
int j;
- print_debug("dimm: ");
- print_debug_hex8(i);
+ print_debug("dimm: ");
+ print_debug_hex8(i);
print_debug(".1: ");
print_debug_hex8(device);
for(j = 0; j < 256; j++) {
@@ -278,7 +278,7 @@ void dump_spd_registers(void)
print_debug("\n");
print_debug("dimm ");
print_debug_hex8(device);
-
+
for(i = 0; (i < 256) ; i++) {
unsigned char byte;
if ((i % 16) == 0) {
@@ -291,7 +291,7 @@ void dump_spd_registers(void)
print_debug("bad device: ");
print_debug_hex8(-status);
print_debug("\n");
- break;
+ break;
}
print_debug_hex8(status);
print_debug_char(' ');
@@ -311,7 +311,7 @@ void dump_ipmi_registers(void)
print_debug("\n");
print_debug("ipmi ");
print_debug_hex8(device);
-
+
for(i = 0; (i < 8) ; i++) {
unsigned char byte;
status = smbus_read_byte(device, 2);
@@ -319,7 +319,7 @@ void dump_ipmi_registers(void)
print_debug("bad device: ");
print_debug_hex8(-status);
print_debug("\n");
- break;
+ break;
}
print_debug_hex8(status);
print_debug_char(' ');
@@ -327,4 +327,4 @@ void dump_ipmi_registers(void)
device += SMBUS_MEM_DEVICE_INC;
print_debug("\n");
}
-}
+}
diff --git a/src/mainboard/supermicro/x6dhe_g/devicetree.cb b/src/mainboard/supermicro/x6dhe_g/devicetree.cb
index d5625e4c7c..075acfc232 100644
--- a/src/mainboard/supermicro/x6dhe_g/devicetree.cb
+++ b/src/mainboard/supermicro/x6dhe_g/devicetree.cb
@@ -10,8 +10,8 @@ chip northbridge/intel/e7520 # MCH
register "pirq_a_d" = "0x0b070a05"
register "pirq_e_h" = "0x0a808080"
- device pci 1c.0 on
- chip drivers/generic/generic
+ device pci 1c.0 on
+ chip drivers/generic/generic
device pci 01.0 on end # onboard gige1
device pci 02.0 on end # onboard gige2
end
@@ -25,9 +25,9 @@ chip northbridge/intel/e7520 # MCH
device pci 1d.7 on end
# VGA / PCI 32-bit
- device pci 1e.0 on
+ device pci 1e.0 on
chip drivers/generic/generic
- device pci 01.0 on end
+ device pci 01.0 on end
end
end
@@ -35,7 +35,7 @@ chip northbridge/intel/e7520 # MCH
device pci 1f.0 on # ISA bridge
chip superio/winbond/w83627hf
device pnp 2e.0 off end
- device pnp 2e.2 on
+ device pnp 2e.2 on
io 0x60 = 0x3f8
irq 0x70 = 4
end
@@ -62,17 +62,17 @@ chip northbridge/intel/e7520 # MCH
device pci 00.0 on end # Northbridge
device pci 00.1 on end # Northbridge Error reporting
device pci 01.0 on end
- device pci 02.0 on
- chip southbridge/intel/pxhd # PXHD 6700
- device pci 00.0 on end # bridge
+ device pci 02.0 on
+ chip southbridge/intel/pxhd # PXHD 6700
+ device pci 00.0 on end # bridge
device pci 00.1 on end # I/O apic
device pci 00.2 on end # bridge
device pci 00.3 on end # I/O apic
end
end
-# device register "intrline" = "0x00070105"
- device pci 04.0 on end
- device pci 06.0 on end
+# device register "intrline" = "0x00070105"
+ device pci 04.0 on end
+ device pci 06.0 on end
end
device apic_cluster 0 on
diff --git a/src/mainboard/supermicro/x6dhe_g/mptable.c b/src/mainboard/supermicro/x6dhe_g/mptable.c
index c50fabb0f3..81ccf85458 100644
--- a/src/mainboard/supermicro/x6dhe_g/mptable.c
+++ b/src/mainboard/supermicro/x6dhe_g/mptable.c
@@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v)
mc->reserved = 0;
smp_write_processors(mc);
-
+
{
device_t dev;
@@ -75,7 +75,7 @@ static void *smp_write_config_table(void *v)
bus_pxhd_2 = 3;
}
}
-
+
/* define bus and isa numbers */
for(bus_num = 0; bus_num < bus_isa; bus_num++) {
smp_write_bus(mc, bus_num, "PCI ");
@@ -162,7 +162,7 @@ static void *smp_write_config_table(void *v)
bus_esb6300_2, 0x04, 0x02, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
bus_esb6300_2, 0x08, 0x02, 0x14);
-
+
/* Standard local interrupt assignments */
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x00, MP_APIC_ALL, 0x00);
diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c
index 67bd2cfb56..2549cb1327 100644
--- a/src/mainboard/supermicro/x6dhe_g/romstage.c
+++ b/src/mainboard/supermicro/x6dhe_g/romstage.c
@@ -55,8 +55,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void main(unsigned long bist)
{
/*
- *
- *
+ *
+ *
*/
static const struct mem_controller mch[] = {
{
@@ -118,7 +118,7 @@ static void main(unsigned long bist)
#endif
disable_watchdogs();
// dump_ipmi_registers();
-// mainboard_set_e7520_leds();
+// mainboard_set_e7520_leds();
sdram_initialize(ARRAY_SIZE(mch), mch);
#if 0
dump_pci_devices();
@@ -128,7 +128,7 @@ static void main(unsigned long bist)
dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
-#if 0 // temporarily disabled
+#if 0 // temporarily disabled
/* Check the first 1M */
// ram_check(0x00000000, 0x000100000);
// ram_check(0x00000000, 0x000a0000);
@@ -139,8 +139,8 @@ static void main(unsigned long bist)
#if 0
ram_check(0x00000000, 0x02000000);
#endif
-
-#if 0
+
+#if 0
while(1) {
hlt();
}
diff --git a/src/mainboard/supermicro/x6dhe_g/watchdog.c b/src/mainboard/supermicro/x6dhe_g/watchdog.c
index 17ec9621ad..a3c55c1543 100644
--- a/src/mainboard/supermicro/x6dhe_g/watchdog.c
+++ b/src/mainboard/supermicro/x6dhe_g/watchdog.c
@@ -31,17 +31,17 @@ static void disable_esb6300_watchdog(void)
value = pci_read_config16(dev, 0x04);
value |= (1 << 10);
pci_write_config16(dev, 0x04, value);
-
+
/* Set and enable acpibase */
pci_write_config32(dev, 0x40, ESB6300_WDBASE | 1);
pci_write_config8(dev, 0x44, 0x10);
base = ESB6300_WDBASE + 0x60;
-
+
/* Set bit 11 in TCO1_CNT */
value = inw(base + 0x08);
value |= 1 << 11;
outw(value, base + 0x08);
-
+
/* Clear TCO timeout status */
outw(0x0008, base + 0x04);
outw(0x0002, base + 0x06);
@@ -86,7 +86,7 @@ static void disable_jarell_frb3(void)
outl(value, base + 0x38);
value &= ~(1 << 16);
outl(value, base + 0x38);
-#endif
+#endif
}
static void disable_watchdogs(void)
diff --git a/src/mainboard/supermicro/x6dhe_g/x6dhe_g_fixups.c b/src/mainboard/supermicro/x6dhe_g/x6dhe_g_fixups.c
index 82c070b0c1..cc3e41eb9f 100644
--- a/src/mainboard/supermicro/x6dhe_g/x6dhe_g_fixups.c
+++ b/src/mainboard/supermicro/x6dhe_g/x6dhe_g_fixups.c
@@ -9,13 +9,13 @@ static void mch_reset(void)
static void mainboard_set_e7520_pll(unsigned bits)
{
- return;
+ return;
}
static void mainboard_set_e7520_leds(void)
{
- return;
+ return;
}