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Diffstat (limited to 'src/mainboard/supermicro/h8dmr_fam10/romstage.c')
-rw-r--r--src/mainboard/supermicro/h8dmr_fam10/romstage.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index 405ec2e4ae..d94d9176fd 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -240,8 +240,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
amdmct_cbmem_store_info(sysinfo);
- timestamp_add_now(TS_END_ROMSTAGE);
-
post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2
post_code(0x42); // Should never see this post code.
}