aboutsummaryrefslogtreecommitdiff
path: root/src/mainboard/supermicro/h8dmr_fam10/romstage.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard/supermicro/h8dmr_fam10/romstage.c')
-rw-r--r--src/mainboard/supermicro/h8dmr_fam10/romstage.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index 980437b201..e1707ac95e 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -238,6 +238,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
cbmem_initialize_empty();
post_code(0x41);
+ amdmct_cbmem_store_info(sysinfo);
+
timestamp_add_now(TS_END_ROMSTAGE);
post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2