diff options
Diffstat (limited to 'src/mainboard/supermicro/h8dmr')
| -rw-r--r-- | src/mainboard/supermicro/h8dmr/ap_romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/supermicro/h8dmr/romstage.c | 8 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/supermicro/h8dmr/ap_romstage.c b/src/mainboard/supermicro/h8dmr/ap_romstage.c index 05c62c3e2c..60dd1b275e 100644 --- a/src/mainboard/supermicro/h8dmr/ap_romstage.c +++ b/src/mainboard/supermicro/h8dmr/ap_romstage.c @@ -86,7 +86,7 @@ void hardwaremain(int ret_addr) id = get_node_core_id_x(); - print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n"); + print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n"); train_ram(id.nodeid, sysinfo, sysinfox); diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index a56f799c7a..7245b37fb2 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -202,7 +202,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_mb_resource_map(); - print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); + print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram @@ -228,7 +228,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } @@ -242,7 +242,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif @@ -254,7 +254,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } #endif |