diff options
Diffstat (limited to 'src/mainboard/supermicro/h8dmr')
| -rw-r--r-- | src/mainboard/supermicro/h8dmr/Kconfig | 104 | ||||
| -rw-r--r-- | src/mainboard/supermicro/h8dmr/Makefile.inc | 78 |
2 files changed, 182 insertions, 0 deletions
diff --git a/src/mainboard/supermicro/h8dmr/Kconfig b/src/mainboard/supermicro/h8dmr/Kconfig new file mode 100644 index 0000000000..4cb20f4c60 --- /dev/null +++ b/src/mainboard/supermicro/h8dmr/Kconfig @@ -0,0 +1,104 @@ +config BOARD_SUPERMICRO_H8DMR + bool "H8DMR" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_F + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_NVIDIA_MCP55 + select SUPERIO_WINBOND_W83627HF + select HAVE_PIRQ_TABLE + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + select HAVE_HARD_RESET + select IOAPIC + +config MAINBOARD_DIR + string + default supermicro/h8dmr + depends on BOARD_SUPERMICRO_H8DMR + +config DCACHE_RAM_BASE + hex + default 0xc8000 + depends on BOARD_SUPERMICRO_H8DMR + +config DCACHE_RAM_SIZE + hex + default 0x08000 + depends on BOARD_SUPERMICRO_H8DMR + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x01000 + depends on BOARD_SUPERMICRO_H8DMR + +config APIC_ID_OFFSET + hex + default 0x10 + depends on BOARD_SUPERMICRO_H8DMR + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_SUPERMICRO_H8DMR + +config SB_HT_CHAIN_UNITID_OFFSET_ONLY + bool + default n + depends on BOARD_SUPERMICRO_H8DMR + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_SUPERMICRO_H8DMR + +config LB_CKS_LOC + int + default 123 + depends on BOARD_SUPERMICRO_H8DMR + +config MAINBOARD_PART_NUMBER + string + default "H8DMR" + depends on BOARD_SUPERMICRO_H8DMR + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_SUPERMICRO_H8DMR + +config MAX_CPUS + int + default 4 + depends on BOARD_SUPERMICRO_H8DMR + +config MAX_PHYSICAL_CPUS + int + default 2 + depends on BOARD_SUPERMICRO_H8DMR + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x0 + depends on BOARD_SUPERMICRO_H8DMR + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + depends on BOARD_SUPERMICRO_H8DMR + +config USE_INIT + bool + default n + depends on BOARD_SUPERMICRO_H8DMR + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_SUPERMICRO_H8DMR + +config IRQ_SLOT_COUNT + int + default 11 + depends on BOARD_SUPERMICRO_H8DMR diff --git a/src/mainboard/supermicro/h8dmr/Makefile.inc b/src/mainboard/supermicro/h8dmr/Makefile.inc new file mode 100644 index 0000000000..085b7d0df3 --- /dev/null +++ b/src/mainboard/supermicro/h8dmr/Makefile.inc @@ -0,0 +1,78 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +driver-y += mainboard.o + +# Needed by irq_tables and mptable and acpi_tables. +obj-y += get_bus_conf.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc +crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds +ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl + iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl + mv dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl + iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl + perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex + mv pci2.hex ssdt2.c + +$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl" + iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/ + perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex + mv pci3.hex ssdt3.c + +$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl" + iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl + perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex + mv pci4.hex ssdt4.c + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + |