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-rw-r--r--src/mainboard/sunw/ultra40m2/devicetree.cb109
1 files changed, 38 insertions, 71 deletions
diff --git a/src/mainboard/sunw/ultra40m2/devicetree.cb b/src/mainboard/sunw/ultra40m2/devicetree.cb
index 5709db75eb..9928d456fd 100644
--- a/src/mainboard/sunw/ultra40m2/devicetree.cb
+++ b/src/mainboard/sunw/ultra40m2/devicetree.cb
@@ -5,66 +5,45 @@ chip northbridge/amd/amdk8/root_complex # Root complex
end
end
device domain 0 on # PCI domain
- subsystemid 0x1022 0x2b80 inherit
+ subsystemid 0x108e 0x6676 inherit
chip northbridge/amd/amdk8 # Northbridge / RAM controller
- device pci 18.0 on # Link 0 == LDT 0
+ device pci 18.0 on end # Link 0 == LDT 0
+ device pci 18.0 on # Link 1 == LDT 1
chip southbridge/nvidia/mcp55 # Southbridge
device pci 0.0 on end # HT
device pci 1.0 on # LPC
- chip superio/winbond/w83627ehg # Super I/O
+ chip superio/smsc/dme1737 # Super I/O
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
- device pnp 2e.1 off # Parallel port
+ device pnp 2e.3 off # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
+ drq 0x74 = 2
end
- device pnp 2e.2 on # Com1
+ device pnp 2e.4 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
- device pnp 2e.3 off # Com2
+ device pnp 2e.5 off # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
end
- device pnp 2e.5 on # PS/2 keyboard & mouse
+ device pnp 2e.7 on # PS/2 (connectors not populated)
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
- device pnp 2e.106 off # Serial flash interface (SFI)
- io 0x60 = 0x100
- end
- device pnp 2e.007 off # GPIO 1
- end
- device pnp 2e.107 off # Game port
- io 0x60 = 0x220
- end
- device pnp 2e.207 off # MIDI
- io 0x62 = 0x300
- irq 0x70 = 9
- end
- device pnp 2e.307 off # GPIO 6
- end
- device pnp 2e.8 off # WDTO#, PLED
- end
- device pnp 2e.009 off # GPIO 2
- end
- device pnp 2e.109 off # GPIO 3
- end
- device pnp 2e.209 off # GPIO 4
- end
- device pnp 2e.309 off # GPIO 5
- end
- device pnp 2e.a off end # ACPI
- device pnp 2e.b on # Hardware monitor
- io 0x60 = 0x290
- irq 0x70 = 5
+ device pnp 2e.a on # Runtime Registers
+ io 0x60 = 0x600
end
end
+ # There's an Infineon SLB9635TT12 TPM on this LPC bus.
+ # There's also an Akom AK2001 7-segment port 0x80 decoder on
+ # this LPC bus.
end
device pci 1.1 on # SM 0
chip drivers/generic/generic # DIMM 0-0-0
@@ -93,41 +72,36 @@ chip northbridge/amd/amdk8/root_complex # Root complex
end
end
device pci 1.1 on # SM 1
- # PCI device SMBus address will
- # depend on addon PCI device, do
- # we need to scan_smbus_bus?
- # chip drivers/generic/generic # PCIXA slot 1
- # device i2c 50 on end
- # end
- # chip drivers/generic/generic # PCIXB slot 1
- # device i2c 51 on end
- # end
- # chip drivers/generic/generic # PCIXB slot 2
- # device i2c 52 on end
- # end
- # chip drivers/generic/generic # PCI slot 1
- # device i2c 53 on end
- # end
- # chip drivers/generic/generic # Master MCP55 PCI-E
- # device i2c 54 on end
- # end
- # chip drivers/generic/generic # Slave MCP55 PCI-E
- # device i2c 55 on end
- # end
- chip drivers/generic/generic # MAC EEPROM
- device i2c 51 on end
- end
+ #chip drivers/generic/generic # PCA9556 GPIO on HDD backplanes (address conflict!)
+ # device i2c 18 on end
+ #end
+ #chip drivers/generic/generic # EMC6D103 HWM (for CPUs)
+ # device i2c 2d on end
+ #end
+ #chip drivers/generic/generic # DME1737 HWM
+ # device i2c 2e on end
+ #end
+ #chip drivers/generic/generic # HDD 4-7 backplane FRU 24C64 EEPROM
+ # device i2c 51 on end
+ #end
+ #chip drivers/generic/generic # front panel module FRU 24C64 EEPROM
+ # device i2c 52 on end
+ #end
+ #chip drivers/generic/generic # HDD 0-3 backplane FRU 24C64 EEPROM
+ # device i2c 53 on end
+ #end
+ # there are more SMbus devices on this bus
end
device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2
device pci 4.0 on end # IDE
device pci 5.0 on end # SATA 0
device pci 5.1 on end # SATA 1
- device pci 5.2 on end # SATA 2
+ device pci 5.2 off end # SATA 2
device pci 6.0 on end # PCI
device pci 6.1 on end # AZA
- device pci 8.0 on end # NIC
- device pci 9.0 on end # NIC
+ device pci 8.0 off end # NIC
+ device pci 9.0 off end # NIC
device pci a.0 on end # PCI E 5
device pci b.0 off end # PCI E 4
device pci c.0 off end # PCI E 3
@@ -137,12 +111,8 @@ chip northbridge/amd/amdk8/root_complex # Root complex
register "ide0_enable" = "1"
register "sata0_enable" = "1"
register "sata1_enable" = "1"
- # 1: SMBus under 2e.8, 2: SM0 3: SM1
- register "mac_eeprom_smbus" = "3"
- register "mac_eeprom_addr" = "0x51"
end
end
- device pci 18.0 on end # Link 1
device pci 18.0 on # Link 2 == LDT 2
chip southbridge/nvidia/mcp55 # Southbridge
device pci 0.0 on end # HT
@@ -153,7 +123,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex
device pci 4.0 off end # IDE
device pci 5.0 on end # SATA 0
device pci 5.1 on end # SATA 1
- device pci 5.2 on end # SATA 2
+ device pci 5.2 off end # SATA 2
device pci 6.0 off end # PCI
device pci 6.1 off end # AZA
device pci 8.0 on end # NIC
@@ -162,14 +132,11 @@ chip northbridge/amd/amdk8/root_complex # Root complex
device pci b.0 off end # PCI E 4
device pci c.0 off end # PCI E 3
device pci d.0 on end # PCI E 2
- device pci e.0 on end # PCI E 1
+ device pci e.0 off end # PCI E 1
device pci f.0 on end # PCI E 0
register "ide0_enable" = "1"
register "sata0_enable" = "1"
register "sata1_enable" = "1"
- # 1: SMBus under 2e.8, 2: SM0 3: SM1
- register "mac_eeprom_smbus" = "3"
- register "mac_eeprom_addr" = "0x51"
end
end
device pci 18.1 on end
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-23 06:39:24 +0000