2 files changed, 14 insertions, 14 deletions
diff --git a/src/mainboard/sunw/ultra40/Config.lb b/src/mainboard/sunw/ultra40/Config.lb
index 82de7c3e1c..22c13e406e 100644
--- a/src/mainboard/sunw/ultra40/Config.lb
+++ b/src/mainboard/sunw/ultra40/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,19 +12,19 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 default CONFIG_ROM_PAYLOAD     = 1
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -90,7 +90,7 @@ else
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/entry16.inc
@@ -111,7 +111,7 @@ end
 
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -151,7 +151,7 @@ if USE_DCACHE_RAM
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/sunw/ultra40/Options.lb b/src/mainboard/sunw/ultra40/Options.lb
index 7e62ae6aae..3c15841cf9 100644
--- a/src/mainboard/sunw/ultra40/Options.lb
+++ b/src/mainboard/sunw/ultra40/Options.lb
@@ -35,7 +35,7 @@ uses MAINBOARD_PART_NUMBER
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID 
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses CONFIG_GDB_STUB
 uses CROSS_COMPILE
@@ -95,7 +95,7 @@ default FALLBACK_SIZE=0x40000
 default HAVE_FALLBACK_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -117,7 +117,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -185,10 +185,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x108e
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x40
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -207,7 +207,7 @@ default HEAP_SIZE=0x4000
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -256,7 +256,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately