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-rw-r--r--src/mainboard/starlabs/starbook/variants/adl/devicetree.cb2
-rw-r--r--src/mainboard/starlabs/starbook/variants/cml/devicetree.cb2
-rw-r--r--src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb2
-rw-r--r--src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb2
4 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
index f7096641e4..a555394214 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
@@ -15,7 +15,7 @@ chip soc/intel/alderlake
register "sagv" = "SaGv_Enabled"
# FSP Silicon
- register "eist_enable" = "1"
+ register "eist_enable" = "true"
# Serial I/O
register "serial_io_i2c_mode" = "{
diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
index 81d593f170..df8bd990ec 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
@@ -1,7 +1,7 @@
chip soc/intel/cannonlake
# CPU
# Enable Enhanced Intel SpeedStep
- register "eist_enable" = "1"
+ register "eist_enable" = "true"
# Graphics
# IGD Displays
diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
index 08f5006d4f..87ccb8a035 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
@@ -1,7 +1,7 @@
chip soc/intel/skylake
# CPU
# Enable Enhanced Intel SpeedStep
- register "eist_enable" = "1"
+ register "eist_enable" = "true"
# Graphics
# IGD Displays
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
index 26197a2e1d..11441621c2 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
@@ -1,7 +1,7 @@
chip soc/intel/tigerlake
# CPU
# Enable Enhanced Intel SpeedStep
- register "eist_enable" = "1"
+ register "eist_enable" = "true"
# Graphics
# Not used but timings left for reference