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-rw-r--r--src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
index 0880569669..a302e4f1c4 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
@@ -9,7 +9,6 @@ chip soc/intel/alderlake
}"
# FSP Memory
- register "enable_c6dram" = "1"
register "sagv" = "SaGv_Enabled"
# FSP Silicon