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-rw-r--r--src/mainboard/starlabs/starfighter/variants/rpl/devtree.c23
1 files changed, 11 insertions, 12 deletions
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c b/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
index ec72aa68c7..5d2b8f6973 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
@@ -25,31 +25,30 @@ void devtree_update(void)
struct device *tbt_pci_dev_1 = pcidev_on_root(0x07, 0);
struct device *tbt_dma_dev = pcidev_on_root(0x0d, 2);
+ uint8_t performance_scale = 100;
+
/* Update PL1 & PL2 based on CMOS settings */
switch (get_power_profile(PP_POWER_SAVER)) {
case PP_POWER_SAVER:
- soc_conf_6core->tdp_pl1_override = 15;
- soc_conf_14core->tdp_pl1_override = 15;
- soc_conf_6core->tdp_pl2_override = 15;
- soc_conf_14core->tdp_pl2_override = 15;
+ performance_scale -= 25;
common_config->pch_thermal_trip = 30;
break;
case PP_BALANCED:
- soc_conf_6core->tdp_pl1_override = 15;
- soc_conf_14core->tdp_pl1_override = 15;
- soc_conf_6core->tdp_pl2_override = 20;
- soc_conf_14core->tdp_pl2_override = 25;
+ /* Use the Intel defaults */
common_config->pch_thermal_trip = 25;
break;
case PP_PERFORMANCE:
- soc_conf_6core->tdp_pl1_override = 15;
- soc_conf_14core->tdp_pl1_override = 28;
- soc_conf_6core->tdp_pl2_override = 25;
- soc_conf_14core->tdp_pl2_override = 40;
+ performance_scale += 25;
common_config->pch_thermal_trip = 20;
break;
}
+ soc_conf_6core->tdp_pl1_override = (soc_conf_6core->tdp_pl1_override * performance_scale) / 100;
+ soc_conf_6core->tdp_pl2_override = (soc_conf_6core->tdp_pl2_override * performance_scale) / 100;
+
+ soc_conf_14core->tdp_pl1_override = (soc_conf_14core->tdp_pl1_override * performance_scale) / 100;
+ soc_conf_14core->tdp_pl2_override = (soc_conf_14core->tdp_pl2_override * performance_scale) / 100;
+
/* Set PL4 to 1.0C */
soc_conf_6core->tdp_pl4 = 65;
soc_conf_14core->tdp_pl4 = 65;