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-rw-r--r--src/mainboard/starlabs/lite/devtree.c14
1 files changed, 8 insertions, 6 deletions
diff --git a/src/mainboard/starlabs/lite/devtree.c b/src/mainboard/starlabs/lite/devtree.c
index 82517df36e..2e192e3548 100644
--- a/src/mainboard/starlabs/lite/devtree.c
+++ b/src/mainboard/starlabs/lite/devtree.c
@@ -25,25 +25,27 @@ void devtree_update(void)
struct device *nic_dev = pcidev_on_root(0x0c, 0);
+ uint8_t performance_scale = 100;
+
/* Update PL1 & PL2 based on CMOS settings */
switch (get_power_profile(PP_POWER_SAVER)) {
case PP_POWER_SAVER:
- soc_conf->tdp_pl1_override = 6;
- soc_conf->tdp_pl2_override = 10;
+ performance_scale -= 25;
cfg->tcc_offset = 15;
break;
case PP_BALANCED:
- soc_conf->tdp_pl1_override = 10;
- soc_conf->tdp_pl2_override = 15;
+ /* Use the Intel defaults */
cfg->tcc_offset = 10;
break;
case PP_PERFORMANCE:
- soc_conf->tdp_pl1_override = 10;
- soc_conf->tdp_pl2_override = 20;
+ performance_scale += 25;
cfg->tcc_offset = 5;
break;
}
+ soc_conf->tdp_pl1_override = (soc_conf->tdp_pl1_override * performance_scale) / 100;
+ soc_conf->tdp_pl2_override = (soc_conf->tdp_pl2_override * performance_scale) / 100;
+
/* Set PL4 to 1.0C */
soc_conf->tdp_pl4 = 31;